| Message ID | 20231129063701.1988235-1-pan2.li@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v1] RISC-V: Bugfix for ICE in block move when zve32f | expand |
pr112743-0.c -> pr112743-1.c for consistent. Otherwise LGTM. No need to send V2. juzhe.zhong@rivai.ai From: pan2.li Date: 2023-11-29 14:37 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Bugfix for ICE in block move when zve32f From: Pan Li <pan2.li@intel.com> The exact_div requires the exactly multiple of the divider. Unfortunately, the condition will be broken when zve32f in some cases. For example, potential_ew is 8 BYTES_PER_RISCV_VECTOR * lmul1 is [4, 4] This patch would like to ensure the precondition of exact_div when get_vec_mode. PR 112743 gcc/ChangeLog: * config/riscv/riscv-string.cc (expand_block_move): Add precondition check for exact_div. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112743-0.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com> --- gcc/config/riscv/riscv-string.cc | 1 + .../gcc.target/riscv/rvv/base/pr112743-0.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-0.c diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc index 3b5e05e2c44..80e3b5981af 100644 --- a/gcc/config/riscv/riscv-string.cc +++ b/gcc/config/riscv/riscv-string.cc @@ -866,6 +866,7 @@ expand_block_move (rtx dst_in, rtx src_in, rtx length_in) if (TARGET_MIN_VLEN * lmul <= nunits * BITS_PER_UNIT /* Avoid loosing the option of using vsetivli . */ && (nunits <= 31 * lmul || nunits > 31 * 8) + && multiple_p (BYTES_PER_RISCV_VECTOR * lmul, potential_ew) && (riscv_vector::get_vector_mode (elem_mode, exact_div (BYTES_PER_RISCV_VECTOR * lmul, potential_ew)).exists (&vmode))) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-0.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-0.c new file mode 100644 index 00000000000..2e62e60d89b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-0.c @@ -0,0 +1,16 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvfh_zfh -mabi=lp64 -O2" } */ + +typedef struct test_a { + void *x; + char a[10]; + short b[2]; + int c[1]; +} test_type_t; + +void +test_copy_memory (test_type_t *out, test_type_t *in) +{ + *out = *in; +}
Committed with the test file rename, thanks Juzhe.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Wednesday, November 29, 2023 2:45 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH v1] RISC-V: Bugfix for ICE in block move when zve32f
pr112743-0.c -> pr112743-1.c for consistent.
Otherwise LGTM. No need to send V2.
diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc index 3b5e05e2c44..80e3b5981af 100644 --- a/gcc/config/riscv/riscv-string.cc +++ b/gcc/config/riscv/riscv-string.cc @@ -866,6 +866,7 @@ expand_block_move (rtx dst_in, rtx src_in, rtx length_in) if (TARGET_MIN_VLEN * lmul <= nunits * BITS_PER_UNIT /* Avoid loosing the option of using vsetivli . */ && (nunits <= 31 * lmul || nunits > 31 * 8) + && multiple_p (BYTES_PER_RISCV_VECTOR * lmul, potential_ew) && (riscv_vector::get_vector_mode (elem_mode, exact_div (BYTES_PER_RISCV_VECTOR * lmul, potential_ew)).exists (&vmode))) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-0.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-0.c new file mode 100644 index 00000000000..2e62e60d89b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-0.c @@ -0,0 +1,16 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvfh_zfh -mabi=lp64 -O2" } */ + +typedef struct test_a { + void *x; + char a[10]; + short b[2]; + int c[1]; +} test_type_t; + +void +test_copy_memory (test_type_t *out, test_type_t *in) +{ + *out = *in; +}