| Message ID | 20231023095457.3675888-1-pan2.li@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v1] RISC-V: Remove unnecessary asm check for vec cvt | expand |
LGTM。 juzhe.zhong@rivai.ai From: pan2.li Date: 2023-10-23 17:54 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Remove unnecessary asm check for vec cvt From: Pan Li <pan2.li@intel.com> The vsetvl asm check is unnecessary for the vector convert. We should be focus for constrait and leave the vsetvl test to the vsetvl pass. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/cvt-0.c: Remove the vsetvl asm check from func body. * gcc.target/riscv/rvv/autovec/unop/cvt-1.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com> --- gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-0.c | 3 +-- gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-1.c | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-0.c index 762b1408994..7d66ed3e943 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-0.c @@ -7,9 +7,8 @@ /* ** test_int65_to_fp16: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma ** vfncvt\.f\.x\.w\s+v[0-9]+,\s*v[0-9]+ -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma +** ... ** vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-1.c index 3180ba3612c..af08c51ef8b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-1.c @@ -7,9 +7,8 @@ /* ** test_uint65_to_fp16: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma ** vfncvt\.f\.xu\.w\s+v[0-9]+,\s*v[0-9]+ -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma +** ... ** vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+ ** ... */
Committed, thanks Juzhe.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Monday, October 23, 2023 5:57 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH v1] RISC-V: Remove unnecessary asm check for vec cvt
LGTM。
On 10/23/23 03:54, pan2.li@intel.com wrote: > From: Pan Li <pan2.li@intel.com> > > The vsetvl asm check is unnecessary for the vector convert. We > should be focus for constrait and leave the vsetvl test to the > vsetvl pass. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/unop/cvt-0.c: Remove the vsetvl > asm check from func body. > * gcc.target/riscv/rvv/autovec/unop/cvt-1.c: Ditto. OK jeff
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-0.c index 762b1408994..7d66ed3e943 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-0.c @@ -7,9 +7,8 @@ /* ** test_int65_to_fp16: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma ** vfncvt\.f\.x\.w\s+v[0-9]+,\s*v[0-9]+ -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma +** ... ** vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-1.c index 3180ba3612c..af08c51ef8b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-1.c @@ -7,9 +7,8 @@ /* ** test_uint65_to_fp16: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma ** vfncvt\.f\.xu\.w\s+v[0-9]+,\s*v[0-9]+ -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma +** ... ** vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+ ** ... */