diff mbox series

[v2] RISC-V/testsuite/pr111466.c: update test and expected output

Message ID 20231017185153.90833-1-vineetg@rivosinc.com
State New
Headers show
Series [v2] RISC-V/testsuite/pr111466.c: update test and expected output | expand

Commit Message

Vineet Gupta Oct. 17, 2023, 6:51 p.m. UTC
Update the test to potentially generate two SEXT.W instructions: one for
incoming function arg, other for function return.

But after commit 8eb9cdd14218
("expr: don't clear SUBREG_PROMOTED_VAR_P flag for a promoted subreg")
the test is not supposed to generate either of them so fix the expected
assembler output which was errorneously introduced by commit above.

gcc/testsuite/ChangeLog:
	* gcc.target/riscv/pr111466.c (foo2): Change return to unsigned
	int as that will potentially generate two SEXT.W instructions.
	dg-final: Change to scan-assembler-not SEXT.W.

Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
---
Changes since v1:
  - Changed function return to be unsigned int
---
 gcc/testsuite/gcc.target/riscv/pr111466.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Jeff Law Oct. 17, 2023, 7:45 p.m. UTC | #1
On 10/17/23 12:51, Vineet Gupta wrote:
> Update the test to potentially generate two SEXT.W instructions: one for
> incoming function arg, other for function return.
> 
> But after commit 8eb9cdd14218
> ("expr: don't clear SUBREG_PROMOTED_VAR_P flag for a promoted subreg")
> the test is not supposed to generate either of them so fix the expected
> assembler output which was errorneously introduced by commit above.
> 
> gcc/testsuite/ChangeLog:
> 	* gcc.target/riscv/pr111466.c (foo2): Change return to unsigned
> 	int as that will potentially generate two SEXT.W instructions.
> 	dg-final: Change to scan-assembler-not SEXT.W.
Oh yes, I should have remembered that update.  Thanks for taking care of it.

jeff
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/pr111466.c b/gcc/testsuite/gcc.target/riscv/pr111466.c
index 007792466a51..3348d593813d 100644
--- a/gcc/testsuite/gcc.target/riscv/pr111466.c
+++ b/gcc/testsuite/gcc.target/riscv/pr111466.c
@@ -4,7 +4,7 @@ 
 /* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64" } */
 /* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
-int foo2(int unused, int n, unsigned y, unsigned delta){
+unsigned int foo2(int unused, int n, unsigned y, unsigned delta){
   int s = 0;
   unsigned int x = 0;
   for (;x<n;x +=delta)
@@ -12,4 +12,4 @@  int foo2(int unused, int n, unsigned y, unsigned delta){
   return s;
 }
 
-/* { dg-final { scan-assembler "\msext\M" } } */
+/* { dg-final { scan-assembler-not "\msext\M" } } */