diff mbox series

RISC-V Regression: Make match patterns more accurate

Message ID 20231010024742.3092307-1-juzhe.zhong@rivai.ai
State New
Headers show
Series RISC-V Regression: Make match patterns more accurate | expand

Commit Message

钟居哲 Oct. 10, 2023, 2:47 a.m. UTC 
This patch fixes following 2 FAILs in RVV regression since the check is not accurate.

It's inspired by Robin's previous patch:
https://patchwork.sourceware.org/project/gcc/patch/dde89b9e-49a0-d70b-0906-fb3022cac11b@gmail.com/

gcc/testsuite/ChangeLog:

	* gcc.dg/vect/no-scevccp-outer-7.c: Adjust regex pattern.
	* gcc.dg/vect/no-scevccp-vect-iv-3.c: Ditto.

---
 gcc/testsuite/gcc.dg/vect/no-scevccp-outer-7.c   | 2 +-
 gcc/testsuite/gcc.dg/vect/no-scevccp-vect-iv-3.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

Comments

Jeff Law Oct. 10, 2023, 1:46 p.m. UTC | #1 
On 10/9/23 20:47, Juzhe-Zhong wrote:
> This patch fixes following 2 FAILs in RVV regression since the check is not accurate.
> 
> It's inspired by Robin's previous patch:
> https://patchwork.sourceware.org/project/gcc/patch/dde89b9e-49a0-d70b-0906-fb3022cac11b@gmail.com/
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.dg/vect/no-scevccp-outer-7.c: Adjust regex pattern.
> 	* gcc.dg/vect/no-scevccp-vect-iv-3.c: Ditto.
OK.   We might see other ports flipping to a pass if they were 
exhibiting the same behavior with failing to vectorize with the first 
selected type, but passing on the second type.

Jeff
Li, Pan2 Oct. 10, 2023, 2:02 p.m. UTC | #2 
Committed, thanks Jeff.

Pan

-----Original Message-----
From: Jeff Law <jeffreyalaw@gmail.com> 
Sent: Tuesday, October 10, 2023 9:47 PM
To: Juzhe-Zhong <juzhe.zhong@rivai.ai>; gcc-patches@gcc.gnu.org
Cc: rguenther@suse.de; rdapp.gcc@gmail.com
Subject: Re: [PATCH] RISC-V Regression: Make match patterns more accurate



On 10/9/23 20:47, Juzhe-Zhong wrote:
> This patch fixes following 2 FAILs in RVV regression since the check is not accurate.
> 
> It's inspired by Robin's previous patch:
> https://patchwork.sourceware.org/project/gcc/patch/dde89b9e-49a0-d70b-0906-fb3022cac11b@gmail.com/
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.dg/vect/no-scevccp-outer-7.c: Adjust regex pattern.
> 	* gcc.dg/vect/no-scevccp-vect-iv-3.c: Ditto.
OK.   We might see other ports flipping to a pass if they were 
exhibiting the same behavior with failing to vectorize with the first 
selected type, but passing on the second type.

Jeff
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-7.c b/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-7.c
index 543ee98b5a4..058d1d2db2d 100644
--- a/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-7.c
+++ b/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-7.c
@@ -77,4 +77,4 @@  int main (void)
 }
 
 /* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target vect_widen_mult_hi_to_si } } } */
-/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 1 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected(?:(?!failed)(?!Re-trying).)*succeeded" 1 "vect" } } */
diff --git a/gcc/testsuite/gcc.dg/vect/no-scevccp-vect-iv-3.c b/gcc/testsuite/gcc.dg/vect/no-scevccp-vect-iv-3.c
index 7049e4936b9..6f2b2210b11 100644
--- a/gcc/testsuite/gcc.dg/vect/no-scevccp-vect-iv-3.c
+++ b/gcc/testsuite/gcc.dg/vect/no-scevccp-vect-iv-3.c
@@ -30,4 +30,4 @@  unsigned int main1 ()
 }
 
 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_widen_sum_hi_to_si } } } */
-/* { dg-final { scan-tree-dump-times "vect_recog_widen_sum_pattern: detected" 1 "vect" { target vect_widen_sum_hi_to_si } } } */
+/* { dg-final { scan-tree-dump-times "vect_recog_widen_sum_pattern: detected(?:(?!failed)(?!Re-trying).)*succeeded" 1 "vect" { target vect_widen_sum_hi_to_si } } } */