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[V2] RISC-V: Add Types to Un-Typed Sync Instructions:

Message ID 20230824211957.671151-1-ewlu@rivosinc.com
State New
Headers show
Series [V2] RISC-V: Add Types to Un-Typed Sync Instructions: | expand

Commit Message

Edwin Lu Aug. 24, 2023, 9:19 p.m. UTC 
Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5eb2@gmail.com/

This patch updates the sync instructions to ensure that no insn is left
without a type attribute. Updates a total of 6 insns to have type "atomic"

Tested for regressions using rv32/64 multilib with newlib/linux. 

gcc/Changelog:

	* config/riscv/sync-rvwmo.md: updated types to "multi" or
    "atomic" based on number of assembly lines generated
	* config/riscv/sync-ztso.md: likewise
	* config/riscv/sync.md: likewise

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
---
Changes in V2:
  - Update insns that were typed "atomic" to "multi" if insn
    can generate multiple lines of assembly following
    https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628055.html
---
 gcc/config/riscv/sync-rvwmo.md |  7 ++++---
 gcc/config/riscv/sync-ztso.md  |  7 ++++---
 gcc/config/riscv/sync.md       | 14 +++++++++-----
 3 files changed, 17 insertions(+), 11 deletions(-)

Comments

Jeff Law Aug. 25, 2023, 6:53 p.m. UTC | #1 
On 8/24/23 15:19, Edwin Lu wrote:
> Related Discussion:
> https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5eb2@gmail.com/
> 
> This patch updates the sync instructions to ensure that no insn is left
> without a type attribute. Updates a total of 6 insns to have type "atomic"
> 
> Tested for regressions using rv32/64 multilib with newlib/linux.
> 
> gcc/Changelog:
> 
> 	* config/riscv/sync-rvwmo.md: updated types to "multi" or
>      "atomic" based on number of assembly lines generated
> 	* config/riscv/sync-ztso.md: likewise
> 	* config/riscv/sync.md: likewise
OK.

You should have your write access set up already.  So go ahead and 
follow the directions in the email you received to get yourself into the 
MAINTAINERS file.  Then you can go ahead and push this change.

THanks,
Jeff
Edwin Lu Aug. 25, 2023, 11:44 p.m. UTC | #2 
On 8/25/2023 11:53 AM, Jeff Law via Gcc-patches wrote:
> 
> 
> On 8/24/23 15:19, Edwin Lu wrote:
>> Related Discussion:
>> https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5eb2@gmail.com/
>>
>> This patch updates the sync instructions to ensure that no insn is left
>> without a type attribute. Updates a total of 6 insns to have type 
>> "atomic"
>>
>> Tested for regressions using rv32/64 multilib with newlib/linux.
>>
>> gcc/Changelog:
>>
>>     * config/riscv/sync-rvwmo.md: updated types to "multi" or
>>      "atomic" based on number of assembly lines generated
>>     * config/riscv/sync-ztso.md: likewise
>>     * config/riscv/sync.md: likewise
> OK.
> 
> You should have your write access set up already.  So go ahead and 
> follow the directions in the email you received to get yourself into the 
> MAINTAINERS file.  Then you can go ahead and push this change.
> 
> THanks,
> Jeff
> 
Committed!

Edwin
diff mbox series

Patch

diff --git a/gcc/config/riscv/sync-rvwmo.md b/gcc/config/riscv/sync-rvwmo.md
index 1fc7cf16b5b..cb641ea9ec3 100644
--- a/gcc/config/riscv/sync-rvwmo.md
+++ b/gcc/config/riscv/sync-rvwmo.md
@@ -41,7 +41,8 @@  (define_insn "mem_thread_fence_rvwmo"
     else
 	gcc_unreachable ();
   }
-  [(set (attr "length") (const_int 4))])
+  [(set_attr "type" "atomic")
+   (set (attr "length") (const_int 4))])
 
 ;; Atomic memory operations.
 
@@ -66,7 +67,7 @@  (define_insn "atomic_load_rvwmo<mode>"
     else
       return "l<amo>\t%0,%1";
   }
-  [(set_attr "type" "atomic")
+  [(set_attr "type" "multi")
    (set (attr "length") (const_int 12))])
 
 ;; Implement atomic stores with conservative fences.
@@ -92,5 +93,5 @@  (define_insn "atomic_store_rvwmo<mode>"
     else
       return "s<amo>\t%z1,%0";
   }
-  [(set_attr "type" "atomic")
+  [(set_attr "type" "multi")
    (set (attr "length") (const_int 12))])
diff --git a/gcc/config/riscv/sync-ztso.md b/gcc/config/riscv/sync-ztso.md
index ed94471b96b..7bb15b7ab8c 100644
--- a/gcc/config/riscv/sync-ztso.md
+++ b/gcc/config/riscv/sync-ztso.md
@@ -35,7 +35,8 @@  (define_insn "mem_thread_fence_ztso"
     else
 	gcc_unreachable ();
   }
-  [(set (attr "length") (const_int 4))])
+  [(set_attr "type" "atomic")
+   (set (attr "length") (const_int 4))])
 
 ;; Atomic memory operations.
 
@@ -56,7 +57,7 @@  (define_insn "atomic_load_ztso<mode>"
     else
       return "l<amo>\t%0,%1";
   }
-  [(set_attr "type" "atomic")
+  [(set_attr "type" "multi")
    (set (attr "length") (const_int 12))])
 
 (define_insn "atomic_store_ztso<mode>"
@@ -76,5 +77,5 @@  (define_insn "atomic_store_ztso<mode>"
     else
       return "s<amo>\t%z1,%0";
   }
-  [(set_attr "type" "atomic")
+  [(set_attr "type" "multi")
    (set (attr "length") (const_int 8))])
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 2f85951508f..6ff3493b5ce 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -136,7 +136,8 @@  (define_insn "subword_atomic_fetch_strong_<atomic_optab>"
 	   "sc.w%J3\t%6, %7, %1\;"
 	   "bnez\t%6, 1b";
   }
-  [(set (attr "length") (const_int 28))])
+  [(set_attr "type" "multi")
+   (set (attr "length") (const_int 28))])
 
 (define_expand "atomic_fetch_nand<mode>"
   [(match_operand:SHORT 0 "register_operand")			      ;; old value at mem
@@ -203,7 +204,8 @@  (define_insn "subword_atomic_fetch_strong_nand"
 	   "sc.w%J3\t%6, %7, %1\;"
 	   "bnez\t%6, 1b";
   }
-  [(set (attr "length") (const_int 32))])
+  [(set_attr "type" "multi")
+   (set (attr "length") (const_int 32))])
 
 (define_expand "atomic_fetch_<atomic_optab><mode>"
   [(match_operand:SHORT 0 "register_operand")			 ;; old value at mem
@@ -310,7 +312,8 @@  (define_insn "subword_atomic_exchange_strong"
 	   "sc.w%J3\t%5, %5, %1\;"
 	   "bnez\t%5, 1b";
   }
-  [(set (attr "length") (const_int 20))])
+  [(set_attr "type" "multi")
+   (set (attr "length") (const_int 20))])
 
 (define_insn "atomic_cas_value_strong<mode>"
   [(set (match_operand:GPR 0 "register_operand" "=&r")
@@ -336,7 +339,7 @@  (define_insn "atomic_cas_value_strong<mode>"
 	   "bnez\t%6,1b\;"
 	   "1:";
   }
-  [(set_attr "type" "atomic")
+  [(set_attr "type" "multi")
    (set (attr "length") (const_int 16))])
 
 (define_expand "atomic_compare_and_swap<mode>"
@@ -497,7 +500,8 @@  (define_insn "subword_atomic_cas_strong"
 	   "bnez\t%7, 1b\;"
 	   "1:";
   }
-  [(set (attr "length") (const_int 28))])
+  [(set_attr "type" "multi")
+   (set (attr "length") (const_int 28))])
 
 (define_expand "atomic_test_and_set"
   [(match_operand:QI 0 "register_operand" "")     ;; bool output