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: Submitter =
Li, Pan2
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Apply
«
1
2
3
4
»
Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
[v1,2/2] RISC-V: Add testcases for form 2 of signed vector SAT_ADD
[v1,1/2] Match: Support form 2 for vector signed integer .SAT_ADD
- - - -
-
-
-
2024-09-20
Li, Pan2
New
[v1,1/2] Match: Support form 2 for vector signed integer .SAT_ADD
[v1,1/2] Match: Support form 2 for vector signed integer .SAT_ADD
- - - -
-
-
-
2024-09-20
Li, Pan2
New
[v1,2/2] RISC-V: Add testcases for form 4 of signed scalar SAT_ADD
[v1,1/2] RISC-V: Add testcases for form 3 of signed scalar SAT_ADD
- - - -
-
-
-
2024-09-20
Li, Pan2
New
[v1,1/2] RISC-V: Add testcases for form 3 of signed scalar SAT_ADD
[v1,1/2] RISC-V: Add testcases for form 3 of signed scalar SAT_ADD
- - - -
-
-
-
2024-09-20
Li, Pan2
New
[v5,4/4] RISC-V: Fix vector SAT_ADD dump check due to middle-end change
[v5,1/4] Match: Add interface match_cond_with_binary_phi for true/false arg
- - - -
-
-
-
2024-09-19
Li, Pan2
New
[v5,3/4] Match: Support form 3 for scalar signed integer .SAT_ADD
[v5,1/4] Match: Add interface match_cond_with_binary_phi for true/false arg
- - - -
-
-
-
2024-09-19
Li, Pan2
New
[v5,2/4] Genmatch: Refine the gen_phi_on_cond by match_cond_with_binary_phi
[v5,1/4] Match: Add interface match_cond_with_binary_phi for true/false arg
- - - -
-
-
-
2024-09-19
Li, Pan2
New
[v5,1/4] Match: Add interface match_cond_with_binary_phi for true/false arg
[v5,1/4] Match: Add interface match_cond_with_binary_phi for true/false arg
- - - -
-
-
-
2024-09-19
Li, Pan2
New
[v1] Match: Remove unnecessary types_match for case 1 of signed SAT_ADD
[v1] Match: Remove unnecessary types_match for case 1 of signed SAT_ADD
- - - -
-
-
-
2024-09-13
Li, Pan2
New
[v1] RISC-V: Add testcases for form 2 of signed scalar SAT_ADD
[v1] RISC-V: Add testcases for form 2 of signed scalar SAT_ADD
- - - -
-
-
-
2024-09-13
Li, Pan2
New
[v1] RISC-V: Fix signed SAT_ADD test case for int64_t
[v1] RISC-V: Fix signed SAT_ADD test case for int64_t
- - - -
-
-
-
2024-09-13
Li, Pan2
New
[v4,4/4] RISC-V: Fix vector SAT_ADD dump check due to middle-end change
[v4,1/4] Match: Add interface match_cond_with_binary_phi for true/false arg
- - - -
-
-
-
2024-09-12
Li, Pan2
New
[v4,3/4] Match: Support form 3 for scalar signed integer .SAT_ADD
[v4,1/4] Match: Add interface match_cond_with_binary_phi for true/false arg
- - - -
-
-
-
2024-09-12
Li, Pan2
New
[v4,2/4] Genmatch: Refine the gen_phi_on_cond by match_cond_with_binary_phi
[v4,1/4] Match: Add interface match_cond_with_binary_phi for true/false arg
- - - -
-
-
-
2024-09-12
Li, Pan2
New
[v4,1/4] Match: Add interface match_cond_with_binary_phi for true/false arg
[v4,1/4] Match: Add interface match_cond_with_binary_phi for true/false arg
- - - -
-
-
-
2024-09-12
Li, Pan2
New
[v1] RISC-V: Implement SAT_ADD for signed integer vector
[v1] RISC-V: Implement SAT_ADD for signed integer vector
- - - -
-
-
-
2024-09-12
Li, Pan2
New
[v3,5/5] RISC-V: Fix vector SAT_ADD dump check due to middle-end change
[v3,1/5] Genmatch: Add control flow graph match for case 0 and case 1
- - - -
-
-
-
2024-09-11
Li, Pan2
New
[v3,4/5] Match: Support form 3 for scalar signed integer .SAT_ADD
[v3,1/5] Genmatch: Add control flow graph match for case 0 and case 1
- - - -
-
-
-
2024-09-11
Li, Pan2
New
[v3,3/5] Genmatch: Refine the gen_phi_on_cond by match_cond_with_binary_phi
[v3,1/5] Genmatch: Add control flow graph match for case 0 and case 1
- - - -
-
-
-
2024-09-11
Li, Pan2
New
[v3,2/5] Match: Add interface match_cond_with_binary_phi for true/false arg
[v3,1/5] Genmatch: Add control flow graph match for case 0 and case 1
- - - -
-
-
-
2024-09-11
Li, Pan2
New
[v3,1/5] Genmatch: Add control flow graph match for case 0 and case 1
[v3,1/5] Genmatch: Add control flow graph match for case 0 and case 1
- - - -
-
-
-
2024-09-11
Li, Pan2
New
[v1] RISC-V: Fix asm check for Vector SAT_* due to middle-end change
[v1] RISC-V: Fix asm check for Vector SAT_* due to middle-end change
- - - -
-
-
-
2024-09-10
Li, Pan2
New
[v2,2/2] Match: Support form 3 for scalar signed integer .SAT_ADD
[v2,1/2] Genmatch: Support control flow graph case 1 for phi on condition
- - - -
-
-
-
2024-09-05
Li, Pan2
New
[v2,1/2] Genmatch: Support control flow graph case 1 for phi on condition
[v2,1/2] Genmatch: Support control flow graph case 1 for phi on condition
- - - -
-
-
-
2024-09-05
Li, Pan2
New
[v1] RISC-V: Fix SAT_* dump check failure due to middle-end change.
[v1] RISC-V: Fix SAT_* dump check failure due to middle-end change.
- - - -
-
-
-
2024-09-05
Li, Pan2
New
[v1,2/2] Match: Support form 3 for scalar signed integer .SAT_ADD
[v1,1/2] Genmatch: Support new flow for phi on condition
- - - -
-
-
-
2024-09-04
Li, Pan2
New
[v1,1/2] Genmatch: Support new flow for phi on condition
[v1,1/2] Genmatch: Support new flow for phi on condition
- - - -
-
-
-
2024-09-04
Li, Pan2
New
[v1] Match: Support form 2 for scalar signed integer .SAT_ADD
[v1] Match: Support form 2 for scalar signed integer .SAT_ADD
- - - -
-
-
-
2024-09-03
Li, Pan2
New
[v1] RISC-V: Allow IMM operand for unsigned scalar .SAT_ADD
[v1] RISC-V: Allow IMM operand for unsigned scalar .SAT_ADD
- - - -
-
-
-
2024-09-02
Li, Pan2
New
[v1,2/2] Match: Add int type fits check for form 2 of .SAT_SUB imm operand
[v1,1/2] Match: Add int type fits check for form 1 of .SAT_SUB imm operand
- - - -
-
-
-
2024-09-02
Li, Pan2
New
[v1,1/2] Match: Add int type fits check for form 1 of .SAT_SUB imm operand
[v1,1/2] Match: Add int type fits check for form 1 of .SAT_SUB imm operand
- - - -
-
-
-
2024-09-02
Li, Pan2
New
[v1] Vect: Support form 1 of vector signed integer .SAT_ADD
[v1] Vect: Support form 1 of vector signed integer .SAT_ADD
- - - -
-
-
-
2024-08-30
Li, Pan2
New
[v1] RISC-V: Refactor gen zero_extend rtx for SAT_* when expand SImode in RV64
[v1] RISC-V: Refactor gen zero_extend rtx for SAT_* when expand SImode in RV64
- - - -
-
-
-
2024-08-30
Li, Pan2
New
[v1,2/2] RISC-V: Add testcases for form 4 of unsigned vector .SAT_ADD IMM
[v1,1/2] RISC-V: Add testcases for form 3 of unsigned vector .SAT_ADD IMM
- - - -
-
-
-
2024-08-30
Li, Pan2
New
[v1,1/2] RISC-V: Add testcases for form 3 of unsigned vector .SAT_ADD IMM
[v1,1/2] RISC-V: Add testcases for form 3 of unsigned vector .SAT_ADD IMM
- - - -
-
-
-
2024-08-30
Li, Pan2
New
[v2,2/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 3
[v2,1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
- - - -
-
-
-
2024-08-29
Li, Pan2
New
[v2,1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
[v2,1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
- - - -
-
-
-
2024-08-29
Li, Pan2
New
[v1] RISC-V: Support form 1 of integer scalar .SAT_ADD
[v1] RISC-V: Support form 1 of integer scalar .SAT_ADD
- - - -
-
-
-
2024-08-29
Li, Pan2
New
[v3] Vect: Reconcile the const_int operand type of unsigned .SAT_ADD
[v3] Vect: Reconcile the const_int operand type of unsigned .SAT_ADD
- - - -
-
-
-
2024-08-28
Li, Pan2
New
[v4] Match: Support form 1 for scalar signed integer .SAT_ADD
[v4] Match: Support form 1 for scalar signed integer .SAT_ADD
- - - -
-
-
-
2024-08-27
Li, Pan2
New
[v1,2/2] RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 4
[v1,1/2] RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 3
- - - -
-
-
-
2024-08-27
Li, Pan2
New
[v1,1/2] RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 3
[v1,1/2] RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 3
- - - -
-
-
-
2024-08-27
Li, Pan2
New
[v2] Vect: Reconcile the const_int operand type of unsigned .SAT_ADD
[v2] Vect: Reconcile the const_int operand type of unsigned .SAT_ADD
- - - -
-
-
-
2024-08-27
Li, Pan2
New
[v1] RISC-V: Support IMM for operand 1 of ussub pattern
[v1] RISC-V: Support IMM for operand 1 of ussub pattern
- - - -
-
-
-
2024-08-26
Li, Pan2
New
[v2] Match: Add int type fits check for .SAT_ADD imm operand
[v2] Match: Add int type fits check for .SAT_ADD imm operand
- - - -
-
-
-
2024-08-26
Li, Pan2
New
[v3] Match: Support form 1 for scalar signed integer .SAT_ADD
[v3] Match: Support form 1 for scalar signed integer .SAT_ADD
- - - -
-
-
-
2024-08-26
Li, Pan2
New
[v1,2/2] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 4
[v1,1/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 4
- - - -
-
-
-
2024-08-25
Li, Pan2
New
[v1,1/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 4
[v1,1/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 4
- - - -
-
-
-
2024-08-25
Li, Pan2
New
[v1] Match: Add type check for .SAT_ADD imm operand
[v1] Match: Add type check for .SAT_ADD imm operand
- - - -
-
-
-
2024-08-24
Li, Pan2
New
[v1,2/2] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 3
[v1,1/2] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 2
- - - -
-
-
-
2024-08-21
Li, Pan2
New
[v1,1/2] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 2
[v1,1/2] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 2
- - - -
-
-
-
2024-08-21
Li, Pan2
New
[v1] RISC-V: Fix one typo in .SAT_TRUNC test func name [NFC]
[v1] RISC-V: Fix one typo in .SAT_TRUNC test func name [NFC]
- - - -
-
-
-
2024-08-20
Li, Pan2
New
[v1] Match: Support form 4 for unsigned integer .SAT_TRUNC
[v1] Match: Support form 4 for unsigned integer .SAT_TRUNC
- - - -
-
-
-
2024-08-20
Li, Pan2
New
[v3] RISC-V: Support IMM for operand 0 of ussub pattern
[v3] RISC-V: Support IMM for operand 0 of ussub pattern
- - - -
-
-
-
2024-08-19
Li, Pan2
New
[v2] Test: Move pr116278 run test to dg/torture [NFC]
[v2] Test: Move pr116278 run test to dg/torture [NFC]
- - - -
-
-
-
2024-08-19
Li, Pan2
New
[v1,1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
[v1,1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
- - - -
-
-
-
2024-08-19
Li, Pan2
New
[v1] Test: Move pr116278 run test to c-torture [NFC]
[v1] Test: Move pr116278 run test to c-torture [NFC]
- - - -
-
-
-
2024-08-18
Li, Pan2
New
[v1,2/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 3
[v1,1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
- - - -
-
-
-
2024-08-18
Li, Pan2
New
[v1,1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
[v1,1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
- - - -
-
-
-
2024-08-18
Li, Pan2
New
[v1,2/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 3
[v1,1/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2
- - - -
-
-
-
2024-08-17
Li, Pan2
New
[v1,1/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2
[v1,1/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2
- - - -
-
-
-
2024-08-17
Li, Pan2
New
[v4] RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278]
[v4] RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278]
- - - -
-
-
-
2024-08-17
Li, Pan2
New
[v3] RISC-V: Make sure high bits of usadd operands is clean for HI/QI [PR116278]
[v3] RISC-V: Make sure high bits of usadd operands is clean for HI/QI [PR116278]
- - - -
-
-
-
2024-08-13
Li, Pan2
New
[v2] RISC-V: Make sure high bits of usadd operands is clean for HI/QI [PR116278]
[v2] RISC-V: Make sure high bits of usadd operands is clean for HI/QI [PR116278]
- - - -
-
-
-
2024-08-11
Li, Pan2
New
[v1] RISC-V: Bugfix incorrect operand for vwsll auto-vect
[v1] RISC-V: Bugfix incorrect operand for vwsll auto-vect
- - - -
-
-
-
2024-08-10
Li, Pan2
New
[v1] RISC-V: Make sure high bits of usadd operands is clean for HI/QI [PR116278]
[v1] RISC-V: Make sure high bits of usadd operands is clean for HI/QI [PR116278]
- - - -
-
-
-
2024-08-09
Li, Pan2
New
[v2] Match: Support form 1 for scalar signed integer .SAT_ADD
[v2] Match: Support form 1 for scalar signed integer .SAT_ADD
- - - -
-
-
-
2024-08-07
Li, Pan2
New
[v2] Vect: Make sure the lhs type of .SAT_TRUNC has its mode precision [PR116202]
[v2] Vect: Make sure the lhs type of .SAT_TRUNC has its mode precision [PR116202]
- - - -
-
-
-
2024-08-06
Li, Pan2
New
[v1] RISC-V: Update .SAT_TRUNC dump check due to middle-end change
[v1] RISC-V: Update .SAT_TRUNC dump check due to middle-end change
- - - -
-
-
-
2024-08-05
Li, Pan2
New
[v1] Match: Support form 1 for scalar signed integer .SAT_ADD
[v1] Match: Support form 1 for scalar signed integer .SAT_ADD
- - - -
-
-
-
2024-08-05
Li, Pan2
New
[v2] RISC-V: Support IMM for operand 0 of ussub pattern
[v2] RISC-V: Support IMM for operand 0 of ussub pattern
- - - -
-
-
-
2024-08-04
Li, Pan2
New
[v1] Match: Add type_has_mode_precision_p check for SAT_TRUNC [PR116202]
[v1] Match: Add type_has_mode_precision_p check for SAT_TRUNC [PR116202]
- - - -
-
-
-
2024-08-04
Li, Pan2
New
[v1] RISC-V: Support IMM for operand 0 of ussub pattern
[v1] RISC-V: Support IMM for operand 0 of ussub pattern
- - - -
-
-
-
2024-08-03
Li, Pan2
New
[v1] RISC-V: Take Xmode instead of Pmode for ussub expanding
[v1] RISC-V: Take Xmode instead of Pmode for ussub expanding
- - - -
-
-
-
2024-07-30
Li, Pan2
New
[v2] Internal-fn: Handle vector bool type for type strict match mode [PR116103]
[v2] Internal-fn: Handle vector bool type for type strict match mode [PR116103]
- - - -
-
-
-
2024-07-30
Li, Pan2
New
[v1] Internal-fn: Handle vector bool type for type strict match mode [PR116103]
[v1] Internal-fn: Handle vector bool type for type strict match mode [PR116103]
- - - -
-
-
-
2024-07-29
Li, Pan2
New
[v1] Widening-Mul: Try .SAT_SUB for PLUS_EXPR when one op is IMM
[v1] Widening-Mul: Try .SAT_SUB for PLUS_EXPR when one op is IMM
- - - -
-
-
-
2024-07-28
Li, Pan2
New
[v1] Match: Support .SAT_SUB with IMM op for form 1-4
[v1] Match: Support .SAT_SUB with IMM op for form 1-4
- - - -
-
-
-
2024-07-26
Li, Pan2
New
[v1] RISC-V: Implement the quad and oct .SAT_TRUNC for scalar
[v1] RISC-V: Implement the quad and oct .SAT_TRUNC for scalar
- - - -
-
-
-
2024-07-23
Li, Pan2
New
[v1] RISC-V: Rearrange the test helper files for vector .SAT_*
[v1] RISC-V: Rearrange the test helper files for vector .SAT_*
- - - -
-
-
-
2024-07-21
Li, Pan2
New
[v2] Internal-fn: Only allow type matches mode for internal fn[PR115961]
[v2] Internal-fn: Only allow type matches mode for internal fn[PR115961]
- - - -
-
-
-
2024-07-19
Li, Pan2
New
[v1] Internal-fn: Only allow modes describe types for internal fn[PR115961]
[v1] Internal-fn: Only allow modes describe types for internal fn[PR115961]
- - - -
-
-
-
2024-07-19
Li, Pan2
New
[v1] Match: Only allow single use of MIN_EXPR for SAT_TRUNC form 2 [PR115863]
[v1] Match: Only allow single use of MIN_EXPR for SAT_TRUNC form 2 [PR115863]
- - - -
-
-
-
2024-07-18
Li, Pan2
New
[v2] Doc: Add Standard-Names ustrunc and sstrunc for integer modes
[v2] Doc: Add Standard-Names ustrunc and sstrunc for integer modes
- - - -
-
-
-
2024-07-18
Li, Pan2
New
[v1] Doc: Add Standard-Names ustrunc and sstrunc for integer modes
[v1] Doc: Add Standard-Names ustrunc and sstrunc for integer modes
- - - -
-
-
-
2024-07-18
Li, Pan2
New
[v1] Match: Bugfix .SAT_TRUNC honor types has no mode precision [PR115961]
[v1] Match: Bugfix .SAT_TRUNC honor types has no mode precision [PR115961]
- - - -
-
-
-
2024-07-17
Li, Pan2
New
[v3] RISC-V: Implement the .SAT_TRUNC for scalar
[v3] RISC-V: Implement the .SAT_TRUNC for scalar
- - - -
-
-
-
2024-07-15
Li, Pan2
New
[v1] RISC-V: Add testcases for vector .SAT_SUB in zip benchmark
[v1] RISC-V: Add testcases for vector .SAT_SUB in zip benchmark
- - - -
-
-
-
2024-07-11
Li, Pan2
New
[v1] Vect: Promote unsigned .SAT_ADD constant operand for vectorizable_call
[v1] Vect: Promote unsigned .SAT_ADD constant operand for vectorizable_call
- - - -
-
-
-
2024-07-10
Li, Pan2
New
[v3] Vect: Optimize truncation for .SAT_SUB operands
[v3] Vect: Optimize truncation for .SAT_SUB operands
- - - -
-
-
-
2024-07-09
Li, Pan2
New
[v1,2/2] RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 2
[v1,1/2] RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 1
- - - -
-
-
-
2024-07-08
Li, Pan2
New
[v1,1/2] RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 1
[v1,1/2] RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 1
- - - -
-
-
-
2024-07-08
Li, Pan2
New
[v3] RISC-V: Implement .SAT_TRUNC for vector unsigned int
[v3] RISC-V: Implement .SAT_TRUNC for vector unsigned int
- - - -
-
-
-
2024-07-08
Li, Pan2
New
[v2] RISC-V: Implement .SAT_TRUNC for vector unsigned int
[v2] RISC-V: Implement .SAT_TRUNC for vector unsigned int
- - - -
-
-
-
2024-07-08
Li, Pan2
New
[v2] Vect: Distribute truncation into .SAT_SUB operands
[v2] Vect: Distribute truncation into .SAT_SUB operands
- - - -
-
-
-
2024-07-05
Li, Pan2
New
[v1] Match: Support form 2 for the .SAT_TRUNC
[v1] Match: Support form 2 for the .SAT_TRUNC
- - - -
-
-
-
2024-07-05
Li, Pan2
New
[v1] RISC-V: Implement .SAT_TRUNC for vector unsigned int
[v1] RISC-V: Implement .SAT_TRUNC for vector unsigned int
- - - -
-
-
-
2024-07-05
Li, Pan2
New
[v1] RISC-V: Bugfix vfmv insn honor zvfhmin for FP16 SEW [PR115763]
[v1] RISC-V: Bugfix vfmv insn honor zvfhmin for FP16 SEW [PR115763]
- - - -
-
-
-
2024-07-03
Li, Pan2
New
[v1] RISC-V: Fix asm check failure for truncated after SAT_SUB
[v1] RISC-V: Fix asm check failure for truncated after SAT_SUB
- - - -
-
-
-
2024-07-03
Li, Pan2
New
[v2] RISC-V: Implement the .SAT_TRUNC for scalar
[v2] RISC-V: Implement the .SAT_TRUNC for scalar
- - - -
-
-
-
2024-07-03
Li, Pan2
New
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