Show patches with: Submitter = Li, Pan2       |    State = Action Required       |    Archived = No       |   459 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v2] Internal-fn: Support new IFN SAT_TRUNC for unsigned scalar int [v2] Internal-fn: Support new IFN SAT_TRUNC for unsigned scalar int - - - - --- 2024-06-27 Li, Pan2 New
[v3] Vect: Support truncate after .SAT_SUB pattern in zip [v3] Vect: Support truncate after .SAT_SUB pattern in zip - - - - --- 2024-06-27 Li, Pan2 New
[v1] Internal-fn: Support new IFN SAT_TRUNC for unsigned scalar int [v1] Internal-fn: Support new IFN SAT_TRUNC for unsigned scalar int - - - - --- 2024-06-26 Li, Pan2 New
[v1] RISC-V: Add testcases for vector truncate after .SAT_SUB [v1] RISC-V: Add testcases for vector truncate after .SAT_SUB - - - - --- 2024-06-25 Li, Pan2 New
[v2] Vect: Support truncate after .SAT_SUB pattern in zip [v2] Vect: Support truncate after .SAT_SUB pattern in zip - - - - --- 2024-06-24 Li, Pan2 New
[v1] Ifcvt: Add cond tree reconcile for truncated .SAT_SUB [v1] Ifcvt: Add cond tree reconcile for truncated .SAT_SUB - - - - --- 2024-06-21 Li, Pan2 New
[v1,8/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 10 [v1,1/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 3 - - - - --- 2024-06-19 Li, Pan2 New
[v1,7/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 9 [v1,1/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 3 - - - - --- 2024-06-19 Li, Pan2 New
[v1,6/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 8 [v1,1/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 3 - - - - --- 2024-06-19 Li, Pan2 New
[v1,5/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 7 [v1,1/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 3 - - - - --- 2024-06-19 Li, Pan2 New
[v1,4/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 6 [v1,1/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 3 - - - - --- 2024-06-19 Li, Pan2 New
[v1,3/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 5 [v1,1/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 3 - - - - --- 2024-06-19 Li, Pan2 New
[v1,2/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 4 [v1,1/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 3 - - - - --- 2024-06-19 Li, Pan2 New
[v1,1/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 3 [v1,1/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 3 - - - - --- 2024-06-19 Li, Pan2 New
[v1,2/2] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12 [v1,1/2] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11 - - - - --- 2024-06-18 Li, Pan2 New
[v1,1/2] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11 [v1,1/2] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11 - - - - --- 2024-06-18 Li, Pan2 New
[v1,7/7] RISC-V: Add testcases for unsigned .SAT_ADD vector form 8 [v1,1/7] RISC-V: Add testcases for unsigned .SAT_ADD vector form 2 - - - - --- 2024-06-17 Li, Pan2 New
[v1,6/7] RISC-V: Add testcases for unsigned .SAT_ADD vector form 7 [v1,1/7] RISC-V: Add testcases for unsigned .SAT_ADD vector form 2 - - - - --- 2024-06-17 Li, Pan2 New
[v1,5/7] RISC-V: Add testcases for unsigned .SAT_ADD vector form 6 [v1,1/7] RISC-V: Add testcases for unsigned .SAT_ADD vector form 2 - - - - --- 2024-06-17 Li, Pan2 New
[v1,4/7] RISC-V: Add testcases for unsigned .SAT_ADD vector form 5 [v1,1/7] RISC-V: Add testcases for unsigned .SAT_ADD vector form 2 - - - - --- 2024-06-17 Li, Pan2 New
[v1,3/7] RISC-V: Add testcases for unsigned .SAT_ADD vector form 4 [v1,1/7] RISC-V: Add testcases for unsigned .SAT_ADD vector form 2 - - - - --- 2024-06-17 Li, Pan2 New
[v1,2/7] RISC-V: Add testcases for unsigned .SAT_ADD vector form 3 [v1,1/7] RISC-V: Add testcases for unsigned .SAT_ADD vector form 2 - - - - --- 2024-06-17 Li, Pan2 New
[v1,1/7] RISC-V: Add testcases for unsigned .SAT_ADD vector form 2 [v1,1/7] RISC-V: Add testcases for unsigned .SAT_ADD vector form 2 - - - - --- 2024-06-17 Li, Pan2 New
[v1] Match: Support form 11 for the unsigned scalar .SAT_SUB [v1] Match: Support form 11 for the unsigned scalar .SAT_SUB - - - - --- 2024-06-17 Li, Pan2 New
[v1] Match: Support forms 7 and 8 for the unsigned .SAT_ADD [v1] Match: Support forms 7 and 8 for the unsigned .SAT_ADD - - - - --- 2024-06-17 Li, Pan2 New
[v1] RISC-V: Add testcases for vector unsigned SAT_SUB form 2 [v1] RISC-V: Add testcases for vector unsigned SAT_SUB form 2 - - - - --- 2024-06-15 Li, Pan2 New
[v1] RISC-V: Refine the SAT_ARITH test help header files [NFC] [v1] RISC-V: Refine the SAT_ARITH test help header files [NFC] - - - - --- 2024-06-15 Li, Pan2 New
[v1] RISC-V: Bugfix vec_extract v mode iterator restriction mismatch [v1] RISC-V: Bugfix vec_extract v mode iterator restriction mismatch - - - - --- 2024-06-14 Li, Pan2 New
[v1,8/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 10 [v1,1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 - - - - --- 2024-06-14 Li, Pan2 New
[v1,7/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 9 [v1,1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 - - - - --- 2024-06-14 Li, Pan2 New
[v1,6/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 8 [v1,1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 - - - - --- 2024-06-14 Li, Pan2 New
[v1,5/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 7 [v1,1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 - - - - --- 2024-06-14 Li, Pan2 New
[v1,4/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 6 [v1,1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 - - - - --- 2024-06-14 Li, Pan2 New
[v1,3/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 5 [v1,1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 - - - - --- 2024-06-14 Li, Pan2 New
[v1,2/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 4 [v1,1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 - - - - --- 2024-06-14 Li, Pan2 New
[v1,1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 [v1,1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 - - - - --- 2024-06-14 Li, Pan2 New
[v1] RISC-V: Bugfix vec_extract vls mode iterator restriction mismatch [v1] RISC-V: Bugfix vec_extract vls mode iterator restriction mismatch - - - - --- 2024-06-13 Li, Pan2 New
[v1] Match: Support more forms for the scalar unsigned .SAT_SUB [v1] Match: Support more forms for the scalar unsigned .SAT_SUB - - - - --- 2024-06-12 Li, Pan2 New
[v2] Test: Move target independent test cases to gcc.dg/torture [v2] Test: Move target independent test cases to gcc.dg/torture - - - - --- 2024-06-11 Li, Pan2 New
[v1] Widening-Mul: Take gsi after_labels instead of start_bb for gcall insertion [v1] Widening-Mul: Take gsi after_labels instead of start_bb for gcall insertion - - - - --- 2024-06-11 Li, Pan2 New
[v1] RISC-V: Implement .SAT_SUB for unsigned vector int [v1] RISC-V: Implement .SAT_SUB for unsigned vector int - - - - --- 2024-06-11 Li, Pan2 New
[v1] Test: Move target independent test cases to gcc.dg/torture [v1] Test: Move target independent test cases to gcc.dg/torture - - - - --- 2024-06-11 Li, Pan2 New
[v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match [v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match - - - - --- 2024-06-10 Li, Pan2 New
[v3] RISC-V: Implement .SAT_SUB for unsigned scalar int [v3] RISC-V: Implement .SAT_SUB for unsigned scalar int - - - - --- 2024-06-07 Li, Pan2 New
[v2] RISC-V: Implement .SAT_SUB for unsigned scalar int [v2] RISC-V: Implement .SAT_SUB for unsigned scalar int - - - - --- 2024-06-07 Li, Pan2 New
[v7] Match: Support more form for scalar unsigned SAT_ADD [v7] Match: Support more form for scalar unsigned SAT_ADD - - - - --- 2024-06-06 Li, Pan2 New
[v2] Vect: Support IFN SAT_SUB for unsigned vector int [v2] Vect: Support IFN SAT_SUB for unsigned vector int - - - - --- 2024-06-06 Li, Pan2 New
[v1] RISC-V: Implement .SAT_SUB for unsigned scalar int [v1] RISC-V: Implement .SAT_SUB for unsigned scalar int - - - - --- 2024-06-05 Li, Pan2 New
[v1,5/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 5 [v1,1/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 1 - - - - --- 2024-06-03 Li, Pan2 New
[v1,4/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 4 [v1,1/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 1 - - - - --- 2024-06-03 Li, Pan2 New
[v1,3/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 3 [v1,1/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 1 - - - - --- 2024-06-03 Li, Pan2 New
[v1,2/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 2 [v1,1/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 1 - - - - --- 2024-06-03 Li, Pan2 New
[v1,1/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 1 [v1,1/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 1 - - - - --- 2024-06-03 Li, Pan2 New
[v6] Match: Support more form for scalar unsigned SAT_ADD [v6] Match: Support more form for scalar unsigned SAT_ADD - - - - --- 2024-05-31 Li, Pan2 New
[v5] Match: Support more form for scalar unsigned SAT_ADD [v5] Match: Support more form for scalar unsigned SAT_ADD - - - - --- 2024-05-31 Li, Pan2 New
[v4] Match: Support more form for scalar unsigned SAT_ADD [v4] Match: Support more form for scalar unsigned SAT_ADD - - - - --- 2024-05-30 Li, Pan2 New
[v1] Vect: Support IFN SAT_SUB for unsigned vector int [v1] Vect: Support IFN SAT_SUB for unsigned vector int - - - - --- 2024-05-29 Li, Pan2 New
[v1] Internal-fn: Support new IFN SAT_SUB for unsigned scalar int [v1] Internal-fn: Support new IFN SAT_SUB for unsigned scalar int - - - - --- 2024-05-28 Li, Pan2 New
[v1] Internal-fn: Add new IFN mask_len_strided_load/store [v1] Internal-fn: Add new IFN mask_len_strided_load/store - - - - --- 2024-05-28 Li, Pan2 New
[v3] Match: Support more form for scalar unsigned SAT_ADD [v3] Match: Support more form for scalar unsigned SAT_ADD - - - - --- 2024-05-27 Li, Pan2 New
[v1] Gen-Match: Fix gen_kids_1 right hand braces mis-alignment [v1] Gen-Match: Fix gen_kids_1 right hand braces mis-alignment - - - - --- 2024-05-26 Li, Pan2 New
[v4] Match: Add overloaded types_match to avoid code dup [NFC] [v4] Match: Add overloaded types_match to avoid code dup [NFC] - - - - --- 2024-05-23 Li, Pan2 New
[v2] Match: Support branch form for unsigned SAT_ADD [v2] Match: Support branch form for unsigned SAT_ADD - - - - --- 2024-05-22 Li, Pan2 New
[v2] Match: Support __builtin_add_overflow branch form for unsigned SAT_ADD [v2] Match: Support __builtin_add_overflow branch form for unsigned SAT_ADD - - - - --- 2024-05-22 Li, Pan2 New
[v1,2/2] RISC-V: Add test cases for __builtin_add_overflow branch form unsigned SAT_ADD [v1,1/2] Match: Support __builtin_add_overflow branch form for unsigned SAT_ADD - - - - --- 2024-05-21 Li, Pan2 New
[v1,1/2] Match: Support __builtin_add_overflow branch form for unsigned SAT_ADD [v1,1/2] Match: Support __builtin_add_overflow branch form for unsigned SAT_ADD - - - - --- 2024-05-21 Li, Pan2 New
[v3] Match: Extract ternary_integer_types_match_p helper func [NFC] [v3] Match: Extract ternary_integer_types_match_p helper func [NFC] - - - - --- 2024-05-21 Li, Pan2 New
[v1,2/2] RISC-V: Add test cases for branch form unsigned SAT_ADD [v1,1/2] Match: Support branch form for unsigned SAT_ADD - - - - --- 2024-05-20 Li, Pan2 New
[v1,1/2] Match: Support branch form for unsigned SAT_ADD [v1,1/2] Match: Support branch form for unsigned SAT_ADD - - - - --- 2024-05-20 Li, Pan2 New
[v2] Match: Extract integer_types_ternary_match helper to avoid code dup [NFC] [v2] Match: Extract integer_types_ternary_match helper to avoid code dup [NFC] - - - - --- 2024-05-20 Li, Pan2 New
[v1,2/2] RISC-V: Add test cases for __builtin_add_overflow branchless unsigned SAT_ADD [v1,1/2] Match: Support __builtin_add_overflow for branchless unsigned SAT_ADD - - - - --- 2024-05-19 Li, Pan2 New
[v1,1/2] Match: Support __builtin_add_overflow for branchless unsigned SAT_ADD [v1,1/2] Match: Support __builtin_add_overflow for branchless unsigned SAT_ADD - - - - --- 2024-05-19 Li, Pan2 New
[v1] Match: Extract integer_types_ternary_match helper to avoid code dup [NFC] [v1] Match: Extract integer_types_ternary_match helper to avoid code dup [NFC] - - - - --- 2024-05-19 Li, Pan2 New
[v6] RISC-V: Implement IFN SAT_ADD for both the scalar and vector [v6] RISC-V: Implement IFN SAT_ADD for both the scalar and vector - - - - --- 2024-05-17 Li, Pan2 New
[v1] RISC-V: Cleanup some temporally files [NFC] [v1] RISC-V: Cleanup some temporally files [NFC] - - - - --- 2024-05-16 Li, Pan2 New
[v2,3/3] RISC-V: Enable vectorizable early exit testsuite [v2,1/3] Vect: Support loop len in vectorizable early exit - - - - --- 2024-05-16 Li, Pan2 New
[v2,2/3] RISC-V: Implement vectorizable early exit with vcond_mask_len [v2,1/3] Vect: Support loop len in vectorizable early exit - - - - --- 2024-05-16 Li, Pan2 New
[v2,1/3] Vect: Support loop len in vectorizable early exit [v2,1/3] Vect: Support loop len in vectorizable early exit - - - - --- 2024-05-16 Li, Pan2 New
[v5,3/3] RISC-V: Implement IFN SAT_ADD for both the scalar and vector [v5,1/3] Internal-fn: Support new IFN SAT_ADD for unsigned scalar int - - - - --- 2024-05-15 Li, Pan2 New
[v5,2/3] Vect: Support new IFN SAT_ADD for unsigned vector int [v5,1/3] Internal-fn: Support new IFN SAT_ADD for unsigned scalar int - - - - --- 2024-05-15 Li, Pan2 New
[v5,1/3] Internal-fn: Support new IFN SAT_ADD for unsigned scalar int [v5,1/3] Internal-fn: Support new IFN SAT_ADD for unsigned scalar int - - - - --- 2024-05-15 Li, Pan2 New
[committed] RISC-V: Fix format issue for trailing operator [NFC] [committed] RISC-V: Fix format issue for trailing operator [NFC] - - - - --- 2024-05-14 Li, Pan2 New
[v1,3/3] RISC-V: Enable vectorizable early exit test [v1,1/3] Vect: Support loop len in vectorizable early exit - - - - --- 2024-05-13 Li, Pan2 New
[v1,2/3] RISC-V: Implement vectorizable early exit with vcond_mask_len [v1,1/3] Vect: Support loop len in vectorizable early exit - - - - --- 2024-05-13 Li, Pan2 New
[v1,1/3] Vect: Support loop len in vectorizable early exit [v1,1/3] Vect: Support loop len in vectorizable early exit - - - - --- 2024-05-13 Li, Pan2 New
[v1] RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar [v1] RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar - - - - --- 2024-05-11 Li, Pan2 New
[v1] RISC-V: Make full-vec-move1.c test robust for optimization [v1] RISC-V: Make full-vec-move1.c test robust for optimization - - - - --- 2024-05-09 Li, Pan2 New
[v4,3/3] RISC-V: Implement IFN SAT_ADD for both the scalar and vector [v1] Internal-fn: Introduce new internal function SAT_ADD - - - - --- 2024-05-06 Li, Pan2 New
[v4,2/3] VECT: Support new IFN SAT_ADD for unsigned vector int [v1] Internal-fn: Introduce new internal function SAT_ADD - - - - --- 2024-05-06 Li, Pan2 New
[v4,1/3] Internal-fn: Support new IFN SAT_ADD for unsigned scalar int [v4,1/3] Internal-fn: Support new IFN SAT_ADD for unsigned scalar int - - - - --- 2024-05-06 Li, Pan2 New
[v4] DSE: Fix ICE after allow vector type in get_stored_val [v4] DSE: Fix ICE after allow vector type in get_stored_val - - - - --- 2024-05-03 Li, Pan2 New
[v3] DSE: Fix ICE after allow vector type in get_stored_val [v3] DSE: Fix ICE after allow vector type in get_stored_val - - - - --- 2024-04-30 Li, Pan2 New
[v3] Internal-fn: Introduce new internal function SAT_ADD [v3] Internal-fn: Introduce new internal function SAT_ADD - - - - --- 2024-04-29 Li, Pan2 New
[v2] RISC-V: Fix ICE for legitimize move on subreg const_poly_int [PR114885] [v2] RISC-V: Fix ICE for legitimize move on subreg const_poly_int [PR114885] - - - - --- 2024-04-29 Li, Pan2 New
[v1] RISC-V: Fix ICE for legitimize move on subreg const_poly_move [v1] RISC-V: Fix ICE for legitimize move on subreg const_poly_move - - - - --- 2024-04-28 Li, Pan2 New
[v1] RISC-V: Add test cases for insn does not satisfy its constraints [PR114714] [v1] RISC-V: Add test cases for insn does not satisfy its constraints [PR114714] - - - - --- 2024-04-25 Li, Pan2 New
[v1] RISC-V: Add xfail test case for highpart register overlap of vwcvt [v1] RISC-V: Add xfail test case for highpart register overlap of vwcvt - - - - --- 2024-04-25 Li, Pan2 New
[v1] RISC-V: Add early clobber to the dest of vwsll [v1] RISC-V: Add early clobber to the dest of vwsll - - - - --- 2024-04-25 Li, Pan2 New
[v1] Revert "RISC-V: Support highpart register overlap for vwcvt" [v1] Revert "RISC-V: Support highpart register overlap for vwcvt" - - - - --- 2024-04-24 Li, Pan2 New
[v1] RISC-V: Add xfail test case for highpart overlap of vext.vf [v1] RISC-V: Add xfail test case for highpart overlap of vext.vf - - - - --- 2024-04-24 Li, Pan2 New
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