diff mbox series

[v1] RISC-V: Fix signed SAT_ADD test case for int64_t

Message ID 20240913012141.1032016-1-pan2.li@intel.com
State New
Headers show
Series [v1] RISC-V: Fix signed SAT_ADD test case for int64_t | expand

Commit Message

Li, Pan2 Sept. 13, 2024, 1:21 a.m. UTC 
From: Pan Li <pan2.li@intel.com>

The int8_t test for signed SAT_ADD is sat_s_add-1.c, the sat_s_add-4.c
should be for int64_t.  Thus, update sat_s_add-4.c for int64_t type.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_s_add-4.c: Update test for int64_t
	instead of int8_t.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/testsuite/gcc.target/riscv/sat_s_add-4.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

Comments

Jeff Law Sept. 18, 2024, 3:11 p.m. UTC | #1 
On 9/12/24 7:21 PM, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
> 
> The int8_t test for signed SAT_ADD is sat_s_add-1.c, the sat_s_add-4.c
> should be for int64_t.  Thus, update sat_s_add-4.c for int64_t type.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/sat_s_add-4.c: Update test for int64_t
> 	instead of int8_t.
OK
jeff
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-4.c b/gcc/testsuite/gcc.target/riscv/sat_s_add-4.c
index f85675c1a05..12c9540eaec 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_s_add-4.c
+++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-4.c
@@ -5,26 +5,25 @@ 
 #include "sat_arith.h"
 
 /*
-** sat_s_add_int8_t_fmt_1:
+** sat_s_add_int64_t_fmt_1:
 ** add\s+[atx][0-9]+,\s*a0,\s*a1
 ** xor\s+[atx][0-9]+,\s*a0,\s*a1
 ** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
-** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7
-** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63
 ** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
-** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
 ** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63
-** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127
+** li\s+[atx][0-9]+,\s*-1
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
+** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
 ** neg\s+[atx][0-9]+,\s*[atx][0-9]+
 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
 ** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
 ** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
-** slliw\s+a0,\s*a0,\s*24
-** sraiw\s+a0,\s*a0,\s*24
 ** ret
 */
-DEF_SAT_S_ADD_FMT_1(int8_t, uint8_t, INT8_MIN, INT8_MAX)
+DEF_SAT_S_ADD_FMT_1(int64_t, uint64_t, INT64_MIN, INT64_MAX)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */