| Message ID | 20240420010454.2019265-1-pan2.li@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v1] RISC-V: Add xfail test case for wv insn register overlap | expand |
LGTM. juzhe.zhong@rivai.ai From: pan2.li Date: 2024-04-20 09:04 To: gcc-patches CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li Subject: [PATCH v1] RISC-V: Add xfail test case for wv insn register overlap From: Pan Li <pan2.li@intel.com> gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-42.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com> --- .../gcc.target/riscv/rvv/base/pr112431-42.c | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c new file mode 100644 index 00000000000..fa5dac58a20 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ffast-math" } */ + +#include <stdint-gcc.h> + +int64_t +reduc_plus_int (int *__restrict a, int n) +{ + int64_t r = 0; + for (int i = 0; i < n; ++i) + r += a[i]; + return r; +} + +double +reduc_plus_float (float *__restrict a, int n) +{ + double r = 0; + for (int i = 0; i < n; ++i) + r += a[i]; + return r; +} + +/* { dg-final { scan-assembler-not {vmv1r} { xfail riscv*-*-* } } } */ +/* { dg-final { scan-assembler-not {vmv2r} } } */ +/* { dg-final { scan-assembler-not {vmv4r} } } */ +/* { dg-final { scan-assembler-not {vmv8r} } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vwadd\.wv} 1 } } */ +/* { dg-final { scan-assembler-times {vfwadd\.wv} 1 } } */
Committed, thanks Juzhe.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Saturday, April 20, 2024 9:20 AM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@gmail.com>; Robin Dapp <rdapp.gcc@gmail.com>; Li, Pan2 <pan2.li@intel.com>
Subject: Re: [PATCH v1] RISC-V: Add xfail test case for wv insn register overlap
LGTM.
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c new file mode 100644 index 00000000000..fa5dac58a20 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ffast-math" } */ + +#include <stdint-gcc.h> + +int64_t +reduc_plus_int (int *__restrict a, int n) +{ + int64_t r = 0; + for (int i = 0; i < n; ++i) + r += a[i]; + return r; +} + +double +reduc_plus_float (float *__restrict a, int n) +{ + double r = 0; + for (int i = 0; i < n; ++i) + r += a[i]; + return r; +} + +/* { dg-final { scan-assembler-not {vmv1r} { xfail riscv*-*-* } } } */ +/* { dg-final { scan-assembler-not {vmv2r} } } */ +/* { dg-final { scan-assembler-not {vmv4r} } } */ +/* { dg-final { scan-assembler-not {vmv8r} } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vwadd\.wv} 1 } } */ +/* { dg-final { scan-assembler-times {vfwadd\.wv} 1 } } */