| Message ID | 20240412060856.1331060-1-pan2.li@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v1] RISC-V: Bugfix ICE non-vector in TARGET_FUNCTION_VALUE_REGNO_P | expand |
LGTM。 juzhe.zhong@rivai.ai From: pan2.li Date: 2024-04-12 14:08 To: gcc-patches CC: juzhe.zhong; kito.cheng; Pan Li Subject: [PATCH v1] RISC-V: Bugfix ICE non-vector in TARGET_FUNCTION_VALUE_REGNO_P From: Pan Li <pan2.li@intel.com> This patch would like to fix one ICE when vector is not enabled in hook TARGET_FUNCTION_VALUE_REGNO_P implementation. The vector regno is available if and only if the TARGET_VECTOR is true. The previous implement missed this condition and then result in ICE when rv64gc build option without vector. PR target/114639 The below test suite is passed for this patch. * The rv64gcv fully regression tests. * The rv64gc fully regression tests. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_function_value_regno_p): Add TARGET_VECTOR predicate for V_RETURN regno. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr114639-1.c: New test. * gcc.target/riscv/pr114639-2.c: New test. * gcc.target/riscv/pr114639-3.c: New test. * gcc.target/riscv/pr114639-4.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com> --- gcc/config/riscv/riscv.cc | 2 +- gcc/testsuite/gcc.target/riscv/pr114639-1.c | 11 +++++++++++ gcc/testsuite/gcc.target/riscv/pr114639-2.c | 11 +++++++++++ gcc/testsuite/gcc.target/riscv/pr114639-3.c | 11 +++++++++++ gcc/testsuite/gcc.target/riscv/pr114639-4.c | 11 +++++++++++ 5 files changed, 45 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-4.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 91f017dd52a..e5f00806bb9 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -11008,7 +11008,7 @@ riscv_function_value_regno_p (const unsigned regno) if (FP_RETURN_FIRST <= regno && regno <= FP_RETURN_LAST) return true; - if (regno == V_RETURN) + if (TARGET_VECTOR && regno == V_RETURN) return true; return false; diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-1.c b/gcc/testsuite/gcc.target/riscv/pr114639-1.c new file mode 100644 index 00000000000..f41723193a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr114639-1.c @@ -0,0 +1,11 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -std=gnu89 -O3" } */ + +g (a, b) {} + +f (xx) + void* xx; +{ + __builtin_apply ((void*)g, xx, 200); +} diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-2.c b/gcc/testsuite/gcc.target/riscv/pr114639-2.c new file mode 100644 index 00000000000..0c402c4b254 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr114639-2.c @@ -0,0 +1,11 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64imac -mabi=lp64 -std=gnu89 -O3" } */ + +g (a, b) {} + +f (xx) + void* xx; +{ + __builtin_apply ((void*)g, xx, 200); +} diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-3.c b/gcc/testsuite/gcc.target/riscv/pr114639-3.c new file mode 100644 index 00000000000..ffb0d6d162d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr114639-3.c @@ -0,0 +1,11 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -std=gnu89 -O3" } */ + +g (a, b) {} + +f (xx) + void* xx; +{ + __builtin_apply ((void*)g, xx, 200); +} diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-4.c b/gcc/testsuite/gcc.target/riscv/pr114639-4.c new file mode 100644 index 00000000000..a6e229101ef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr114639-4.c @@ -0,0 +1,11 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv32imac -mabi=ilp32 -std=gnu89 -O3" } */ + +g (a, b) {} + +f (xx) + void* xx; +{ + __builtin_apply ((void*)g, xx, 200); +}
Committed, thanks Juzhe.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Friday, April 12, 2024 2:11 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@gmail.com>; Li, Pan2 <pan2.li@intel.com>
Subject: Re: [PATCH v1] RISC-V: Bugfix ICE non-vector in TARGET_FUNCTION_VALUE_REGNO_P
LGTM。
Does FP reg also need gurared with TARGET_HARD_FLOAT? could you try to compile that case without F? On Fri, Apr 12, 2024 at 2:19 PM Li, Pan2 <pan2.li@intel.com> wrote: > > Committed, thanks Juzhe. > > > > Pan > > > > From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai> > Sent: Friday, April 12, 2024 2:11 PM > To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org> > Cc: kito.cheng <kito.cheng@gmail.com>; Li, Pan2 <pan2.li@intel.com> > Subject: Re: [PATCH v1] RISC-V: Bugfix ICE non-vector in TARGET_FUNCTION_VALUE_REGNO_P > > > > LGTM。 > > > > ________________________________ > > juzhe.zhong@rivai.ai > > > > From: pan2.li > > Date: 2024-04-12 14:08 > > To: gcc-patches > > CC: juzhe.zhong; kito.cheng; Pan Li > > Subject: [PATCH v1] RISC-V: Bugfix ICE non-vector in TARGET_FUNCTION_VALUE_REGNO_P > > From: Pan Li <pan2.li@intel.com> > > > > This patch would like to fix one ICE when vector is not enabled > > in hook TARGET_FUNCTION_VALUE_REGNO_P implementation. The vector > > regno is available if and only if the TARGET_VECTOR is true. The > > previous implement missed this condition and then result in ICE > > when rv64gc build option without vector. > > > > PR target/114639 > > > > The below test suite is passed for this patch. > > > > * The rv64gcv fully regression tests. > > * The rv64gc fully regression tests. > > > > gcc/ChangeLog: > > > > * config/riscv/riscv.cc (riscv_function_value_regno_p): Add > > TARGET_VECTOR predicate for V_RETURN regno. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/pr114639-1.c: New test. > > * gcc.target/riscv/pr114639-2.c: New test. > > * gcc.target/riscv/pr114639-3.c: New test. > > * gcc.target/riscv/pr114639-4.c: New test. > > > > Signed-off-by: Pan Li <pan2.li@intel.com> > > --- > > gcc/config/riscv/riscv.cc | 2 +- > > gcc/testsuite/gcc.target/riscv/pr114639-1.c | 11 +++++++++++ > > gcc/testsuite/gcc.target/riscv/pr114639-2.c | 11 +++++++++++ > > gcc/testsuite/gcc.target/riscv/pr114639-3.c | 11 +++++++++++ > > gcc/testsuite/gcc.target/riscv/pr114639-4.c | 11 +++++++++++ > > 5 files changed, 45 insertions(+), 1 deletion(-) > > create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-1.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-2.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-3.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-4.c > > > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > > index 91f017dd52a..e5f00806bb9 100644 > > --- a/gcc/config/riscv/riscv.cc > > +++ b/gcc/config/riscv/riscv.cc > > @@ -11008,7 +11008,7 @@ riscv_function_value_regno_p (const unsigned regno) > > if (FP_RETURN_FIRST <= regno && regno <= FP_RETURN_LAST) > > return true; > > - if (regno == V_RETURN) > > + if (TARGET_VECTOR && regno == V_RETURN) > > return true; > > return false; > > diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-1.c b/gcc/testsuite/gcc.target/riscv/pr114639-1.c > > new file mode 100644 > > index 00000000000..f41723193a4 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/pr114639-1.c > > @@ -0,0 +1,11 @@ > > +/* Test that we do not have ice when compile */ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=rv64gc -mabi=lp64d -std=gnu89 -O3" } */ > > + > > +g (a, b) {} > > + > > +f (xx) > > + void* xx; > > +{ > > + __builtin_apply ((void*)g, xx, 200); > > +} > > diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-2.c b/gcc/testsuite/gcc.target/riscv/pr114639-2.c > > new file mode 100644 > > index 00000000000..0c402c4b254 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/pr114639-2.c > > @@ -0,0 +1,11 @@ > > +/* Test that we do not have ice when compile */ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=rv64imac -mabi=lp64 -std=gnu89 -O3" } */ > > + > > +g (a, b) {} > > + > > +f (xx) > > + void* xx; > > +{ > > + __builtin_apply ((void*)g, xx, 200); > > +} > > diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-3.c b/gcc/testsuite/gcc.target/riscv/pr114639-3.c > > new file mode 100644 > > index 00000000000..ffb0d6d162d > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/pr114639-3.c > > @@ -0,0 +1,11 @@ > > +/* Test that we do not have ice when compile */ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=rv32gc -mabi=ilp32d -std=gnu89 -O3" } */ > > + > > +g (a, b) {} > > + > > +f (xx) > > + void* xx; > > +{ > > + __builtin_apply ((void*)g, xx, 200); > > +} > > diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-4.c b/gcc/testsuite/gcc.target/riscv/pr114639-4.c > > new file mode 100644 > > index 00000000000..a6e229101ef > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/pr114639-4.c > > @@ -0,0 +1,11 @@ > > +/* Test that we do not have ice when compile */ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=rv32imac -mabi=ilp32 -std=gnu89 -O3" } */ > > + > > +g (a, b) {} > > + > > +f (xx) > > + void* xx; > > +{ > > + __builtin_apply ((void*)g, xx, 200); > > +} > > -- > > 2.34.1 > > > >
Sure thing, the FP_RETURN only acts on ABI_xxx similar to below: #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST) I add some test for rv32/64imac option but don't cover all test cases without f/d extension, will have a try and keep you posted. Pan -----Original Message----- From: Kito Cheng <kito.cheng@gmail.com> Sent: Friday, April 12, 2024 4:56 PM To: Li, Pan2 <pan2.li@intel.com> Cc: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org> Subject: Re: [PATCH v1] RISC-V: Bugfix ICE non-vector in TARGET_FUNCTION_VALUE_REGNO_P Does FP reg also need gurared with TARGET_HARD_FLOAT? could you try to compile that case without F? On Fri, Apr 12, 2024 at 2:19 PM Li, Pan2 <pan2.li@intel.com> wrote: > > Committed, thanks Juzhe. > > > > Pan > > > > From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai> > Sent: Friday, April 12, 2024 2:11 PM > To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org> > Cc: kito.cheng <kito.cheng@gmail.com>; Li, Pan2 <pan2.li@intel.com> > Subject: Re: [PATCH v1] RISC-V: Bugfix ICE non-vector in TARGET_FUNCTION_VALUE_REGNO_P > > > > LGTM。 > > > > ________________________________ > > juzhe.zhong@rivai.ai > > > > From: pan2.li > > Date: 2024-04-12 14:08 > > To: gcc-patches > > CC: juzhe.zhong; kito.cheng; Pan Li > > Subject: [PATCH v1] RISC-V: Bugfix ICE non-vector in TARGET_FUNCTION_VALUE_REGNO_P > > From: Pan Li <pan2.li@intel.com> > > > > This patch would like to fix one ICE when vector is not enabled > > in hook TARGET_FUNCTION_VALUE_REGNO_P implementation. The vector > > regno is available if and only if the TARGET_VECTOR is true. The > > previous implement missed this condition and then result in ICE > > when rv64gc build option without vector. > > > > PR target/114639 > > > > The below test suite is passed for this patch. > > > > * The rv64gcv fully regression tests. > > * The rv64gc fully regression tests. > > > > gcc/ChangeLog: > > > > * config/riscv/riscv.cc (riscv_function_value_regno_p): Add > > TARGET_VECTOR predicate for V_RETURN regno. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/pr114639-1.c: New test. > > * gcc.target/riscv/pr114639-2.c: New test. > > * gcc.target/riscv/pr114639-3.c: New test. > > * gcc.target/riscv/pr114639-4.c: New test. > > > > Signed-off-by: Pan Li <pan2.li@intel.com> > > --- > > gcc/config/riscv/riscv.cc | 2 +- > > gcc/testsuite/gcc.target/riscv/pr114639-1.c | 11 +++++++++++ > > gcc/testsuite/gcc.target/riscv/pr114639-2.c | 11 +++++++++++ > > gcc/testsuite/gcc.target/riscv/pr114639-3.c | 11 +++++++++++ > > gcc/testsuite/gcc.target/riscv/pr114639-4.c | 11 +++++++++++ > > 5 files changed, 45 insertions(+), 1 deletion(-) > > create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-1.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-2.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-3.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-4.c > > > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > > index 91f017dd52a..e5f00806bb9 100644 > > --- a/gcc/config/riscv/riscv.cc > > +++ b/gcc/config/riscv/riscv.cc > > @@ -11008,7 +11008,7 @@ riscv_function_value_regno_p (const unsigned regno) > > if (FP_RETURN_FIRST <= regno && regno <= FP_RETURN_LAST) > > return true; > > - if (regno == V_RETURN) > > + if (TARGET_VECTOR && regno == V_RETURN) > > return true; > > return false; > > diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-1.c b/gcc/testsuite/gcc.target/riscv/pr114639-1.c > > new file mode 100644 > > index 00000000000..f41723193a4 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/pr114639-1.c > > @@ -0,0 +1,11 @@ > > +/* Test that we do not have ice when compile */ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=rv64gc -mabi=lp64d -std=gnu89 -O3" } */ > > + > > +g (a, b) {} > > + > > +f (xx) > > + void* xx; > > +{ > > + __builtin_apply ((void*)g, xx, 200); > > +} > > diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-2.c b/gcc/testsuite/gcc.target/riscv/pr114639-2.c > > new file mode 100644 > > index 00000000000..0c402c4b254 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/pr114639-2.c > > @@ -0,0 +1,11 @@ > > +/* Test that we do not have ice when compile */ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=rv64imac -mabi=lp64 -std=gnu89 -O3" } */ > > + > > +g (a, b) {} > > + > > +f (xx) > > + void* xx; > > +{ > > + __builtin_apply ((void*)g, xx, 200); > > +} > > diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-3.c b/gcc/testsuite/gcc.target/riscv/pr114639-3.c > > new file mode 100644 > > index 00000000000..ffb0d6d162d > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/pr114639-3.c > > @@ -0,0 +1,11 @@ > > +/* Test that we do not have ice when compile */ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=rv32gc -mabi=ilp32d -std=gnu89 -O3" } */ > > + > > +g (a, b) {} > > + > > +f (xx) > > + void* xx; > > +{ > > + __builtin_apply ((void*)g, xx, 200); > > +} > > diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-4.c b/gcc/testsuite/gcc.target/riscv/pr114639-4.c > > new file mode 100644 > > index 00000000000..a6e229101ef > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/pr114639-4.c > > @@ -0,0 +1,11 @@ > > +/* Test that we do not have ice when compile */ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=rv32imac -mabi=ilp32 -std=gnu89 -O3" } */ > > + > > +g (a, b) {} > > + > > +f (xx) > > + void* xx; > > +{ > > + __builtin_apply ((void*)g, xx, 200); > > +} > > -- > > 2.34.1 > > > >
Just completed the rv64imac test for fully regression test, there is NO increased failures. For FP_RETURN, I think the ABI side somehow has some restrictions similar to TARGET_HARD_FLOAT (of course as is). For example, the rv64imac cannot work with lp64f/d, thus the FP_RETURN will be right REG because it is GP_RETURN if the lp64 abi is given. Unfortunately this is not working for v extension as we have no v in abi option. How about we refine this part to TARGET_HARD_FLOAT after gcc-15 opens as the current implement looks like friable and implicit up to a point? Pan -----Original Message----- From: Li, Pan2 Sent: Friday, April 12, 2024 6:58 PM To: Kito Cheng <kito.cheng@gmail.com> Cc: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org> Subject: RE: [PATCH v1] RISC-V: Bugfix ICE non-vector in TARGET_FUNCTION_VALUE_REGNO_P Sure thing, the FP_RETURN only acts on ABI_xxx similar to below: #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST) I add some test for rv32/64imac option but don't cover all test cases without f/d extension, will have a try and keep you posted. Pan -----Original Message----- From: Kito Cheng <kito.cheng@gmail.com> Sent: Friday, April 12, 2024 4:56 PM To: Li, Pan2 <pan2.li@intel.com> Cc: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org> Subject: Re: [PATCH v1] RISC-V: Bugfix ICE non-vector in TARGET_FUNCTION_VALUE_REGNO_P Does FP reg also need gurared with TARGET_HARD_FLOAT? could you try to compile that case without F? On Fri, Apr 12, 2024 at 2:19 PM Li, Pan2 <pan2.li@intel.com> wrote: > > Committed, thanks Juzhe. > > > > Pan > > > > From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai> > Sent: Friday, April 12, 2024 2:11 PM > To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org> > Cc: kito.cheng <kito.cheng@gmail.com>; Li, Pan2 <pan2.li@intel.com> > Subject: Re: [PATCH v1] RISC-V: Bugfix ICE non-vector in TARGET_FUNCTION_VALUE_REGNO_P > > > > LGTM。 > > > > ________________________________ > > juzhe.zhong@rivai.ai > > > > From: pan2.li > > Date: 2024-04-12 14:08 > > To: gcc-patches > > CC: juzhe.zhong; kito.cheng; Pan Li > > Subject: [PATCH v1] RISC-V: Bugfix ICE non-vector in TARGET_FUNCTION_VALUE_REGNO_P > > From: Pan Li <pan2.li@intel.com> > > > > This patch would like to fix one ICE when vector is not enabled > > in hook TARGET_FUNCTION_VALUE_REGNO_P implementation. The vector > > regno is available if and only if the TARGET_VECTOR is true. The > > previous implement missed this condition and then result in ICE > > when rv64gc build option without vector. > > > > PR target/114639 > > > > The below test suite is passed for this patch. > > > > * The rv64gcv fully regression tests. > > * The rv64gc fully regression tests. > > > > gcc/ChangeLog: > > > > * config/riscv/riscv.cc (riscv_function_value_regno_p): Add > > TARGET_VECTOR predicate for V_RETURN regno. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/pr114639-1.c: New test. > > * gcc.target/riscv/pr114639-2.c: New test. > > * gcc.target/riscv/pr114639-3.c: New test. > > * gcc.target/riscv/pr114639-4.c: New test. > > > > Signed-off-by: Pan Li <pan2.li@intel.com> > > --- > > gcc/config/riscv/riscv.cc | 2 +- > > gcc/testsuite/gcc.target/riscv/pr114639-1.c | 11 +++++++++++ > > gcc/testsuite/gcc.target/riscv/pr114639-2.c | 11 +++++++++++ > > gcc/testsuite/gcc.target/riscv/pr114639-3.c | 11 +++++++++++ > > gcc/testsuite/gcc.target/riscv/pr114639-4.c | 11 +++++++++++ > > 5 files changed, 45 insertions(+), 1 deletion(-) > > create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-1.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-2.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-3.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-4.c > > > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > > index 91f017dd52a..e5f00806bb9 100644 > > --- a/gcc/config/riscv/riscv.cc > > +++ b/gcc/config/riscv/riscv.cc > > @@ -11008,7 +11008,7 @@ riscv_function_value_regno_p (const unsigned regno) > > if (FP_RETURN_FIRST <= regno && regno <= FP_RETURN_LAST) > > return true; > > - if (regno == V_RETURN) > > + if (TARGET_VECTOR && regno == V_RETURN) > > return true; > > return false; > > diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-1.c b/gcc/testsuite/gcc.target/riscv/pr114639-1.c > > new file mode 100644 > > index 00000000000..f41723193a4 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/pr114639-1.c > > @@ -0,0 +1,11 @@ > > +/* Test that we do not have ice when compile */ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=rv64gc -mabi=lp64d -std=gnu89 -O3" } */ > > + > > +g (a, b) {} > > + > > +f (xx) > > + void* xx; > > +{ > > + __builtin_apply ((void*)g, xx, 200); > > +} > > diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-2.c b/gcc/testsuite/gcc.target/riscv/pr114639-2.c > > new file mode 100644 > > index 00000000000..0c402c4b254 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/pr114639-2.c > > @@ -0,0 +1,11 @@ > > +/* Test that we do not have ice when compile */ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=rv64imac -mabi=lp64 -std=gnu89 -O3" } */ > > + > > +g (a, b) {} > > + > > +f (xx) > > + void* xx; > > +{ > > + __builtin_apply ((void*)g, xx, 200); > > +} > > diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-3.c b/gcc/testsuite/gcc.target/riscv/pr114639-3.c > > new file mode 100644 > > index 00000000000..ffb0d6d162d > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/pr114639-3.c > > @@ -0,0 +1,11 @@ > > +/* Test that we do not have ice when compile */ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=rv32gc -mabi=ilp32d -std=gnu89 -O3" } */ > > + > > +g (a, b) {} > > + > > +f (xx) > > + void* xx; > > +{ > > + __builtin_apply ((void*)g, xx, 200); > > +} > > diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-4.c b/gcc/testsuite/gcc.target/riscv/pr114639-4.c > > new file mode 100644 > > index 00000000000..a6e229101ef > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/pr114639-4.c > > @@ -0,0 +1,11 @@ > > +/* Test that we do not have ice when compile */ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=rv32imac -mabi=ilp32 -std=gnu89 -O3" } */ > > + > > +g (a, b) {} > > + > > +f (xx) > > + void* xx; > > +{ > > + __builtin_apply ((void*)g, xx, 200); > > +} > > -- > > 2.34.1 > > > >
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 91f017dd52a..e5f00806bb9 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -11008,7 +11008,7 @@ riscv_function_value_regno_p (const unsigned regno) if (FP_RETURN_FIRST <= regno && regno <= FP_RETURN_LAST) return true; - if (regno == V_RETURN) + if (TARGET_VECTOR && regno == V_RETURN) return true; return false; diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-1.c b/gcc/testsuite/gcc.target/riscv/pr114639-1.c new file mode 100644 index 00000000000..f41723193a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr114639-1.c @@ -0,0 +1,11 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -std=gnu89 -O3" } */ + +g (a, b) {} + +f (xx) + void* xx; +{ + __builtin_apply ((void*)g, xx, 200); +} diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-2.c b/gcc/testsuite/gcc.target/riscv/pr114639-2.c new file mode 100644 index 00000000000..0c402c4b254 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr114639-2.c @@ -0,0 +1,11 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64imac -mabi=lp64 -std=gnu89 -O3" } */ + +g (a, b) {} + +f (xx) + void* xx; +{ + __builtin_apply ((void*)g, xx, 200); +} diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-3.c b/gcc/testsuite/gcc.target/riscv/pr114639-3.c new file mode 100644 index 00000000000..ffb0d6d162d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr114639-3.c @@ -0,0 +1,11 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -std=gnu89 -O3" } */ + +g (a, b) {} + +f (xx) + void* xx; +{ + __builtin_apply ((void*)g, xx, 200); +} diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-4.c b/gcc/testsuite/gcc.target/riscv/pr114639-4.c new file mode 100644 index 00000000000..a6e229101ef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr114639-4.c @@ -0,0 +1,11 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv32imac -mabi=ilp32 -std=gnu89 -O3" } */ + +g (a, b) {} + +f (xx) + void* xx; +{ + __builtin_apply ((void*)g, xx, 200); +}