| Message ID | 20231113032237.1379330-1-pan2.li@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v4] DSE: Allow vector type for get_stored_val when read < store | expand |
On 11/12/23 20:22, pan2.li@intel.com wrote: > From: Pan Li <pan2.li@intel.com> > > Update in v4: > * Merge upstream and removed some independent changes. > > Update in v3: > * Take known_le instead of known_lt for vector size. > * Return NULL_RTX when gap is not equal 0 and not constant. > > Update in v2: > * Move vector type support to get_stored_val. > > Original log: > > This patch would like to allow the vector mode in the > get_stored_val in the DSE. It is valid for the read > rtx if and only if the read bitsize is less than the > stored bitsize. > > Given below example code with > --param=riscv-autovec-preference=fixed-vlmax. > > vuint8m1_t test () { > uint8_t arr[32] = { > 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, > 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, > }; > > return __riscv_vle8_v_u8m1(arr, 32); > } > > Before this patch: > test: > lui a5,%hi(.LANCHOR0) > addi sp,sp,-32 > addi a5,a5,%lo(.LANCHOR0) > li a3,32 > vl2re64.v v2,0(a5) > vsetvli zero,a3,e8,m1,ta,ma > vs2r.v v2,0(sp) <== Unnecessary store to stack > vle8.v v1,0(sp) <== Ditto > vs1r.v v1,0(a0) > addi sp,sp,32 > jr ra > > After this patch: > test: > lui a5,%hi(.LANCHOR0) > addi a5,a5,%lo(.LANCHOR0) > li a4,32 > addi sp,sp,-32 > vsetvli zero,a4,e8,m1,ta,ma > vle8.v v1,0(a5) > vs1r.v v1,0(a0) > addi sp,sp,32 > jr ra > > Below tests are passed within this patch: > * The risc-v regression test. > * The x86 bootstrap and regression test. > * The aarch64 regression test. > > PR target/111720 > > gcc/ChangeLog: > > * dse.cc (get_stored_val): Allow vector mode if read size is > less than or equal to stored size. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/pr111720-0.c: New test. > * gcc.target/riscv/rvv/base/pr111720-1.c: New test. > * gcc.target/riscv/rvv/base/pr111720-10.c: New test. > * gcc.target/riscv/rvv/base/pr111720-2.c: New test. > * gcc.target/riscv/rvv/base/pr111720-3.c: New test. > * gcc.target/riscv/rvv/base/pr111720-4.c: New test. > * gcc.target/riscv/rvv/base/pr111720-5.c: New test. > * gcc.target/riscv/rvv/base/pr111720-6.c: New test. > * gcc.target/riscv/rvv/base/pr111720-7.c: New test. > * gcc.target/riscv/rvv/base/pr111720-8.c: New test. > * gcc.target/riscv/rvv/base/pr111720-9.c: New test. OK for the trunk. > > + else if (VECTOR_MODE_P (read_mode) && VECTOR_MODE_P (store_mode) > + && known_le (GET_MODE_BITSIZE (read_mode), GET_MODE_BITSIZE (store_mode)) > + && targetm.modes_tieable_p (read_mode, store_mode)) > + read_reg = gen_lowpart (read_mode, copy_rtx (store_info->rhs)); > else > read_reg = extract_low_bits (read_mode, store_mode, > copy_rtx (store_info->rhs)); It may not matter, especially for RV, but we could possibly have a mixture of scalar and vector modes in the RTL. Say a vector store followed by a scalar read or vice-versa. I wouldn't try to handle that case unless we had actual evidence it was useful to do so. Just wanted to point out that unlike pseudos we can have multiple modes referencing the same memory location. Jeff
> I wouldn't try to handle that case unless we had actual evidence it was > useful to do so. Just wanted to point out that unlike pseudos we can > have multiple modes referencing the same memory location. Got the point here, thanks Jeff for emphasizing this, 😉. Pan -----Original Message----- From: Jeff Law <jeffreyalaw@gmail.com> Sent: Tuesday, November 14, 2023 4:12 AM To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; richard.guenther@gmail.com; richard.sandiford@arm.com2 Subject: Re: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store On 11/12/23 20:22, pan2.li@intel.com wrote: > From: Pan Li <pan2.li@intel.com> > > Update in v4: > * Merge upstream and removed some independent changes. > > Update in v3: > * Take known_le instead of known_lt for vector size. > * Return NULL_RTX when gap is not equal 0 and not constant. > > Update in v2: > * Move vector type support to get_stored_val. > > Original log: > > This patch would like to allow the vector mode in the > get_stored_val in the DSE. It is valid for the read > rtx if and only if the read bitsize is less than the > stored bitsize. > > Given below example code with > --param=riscv-autovec-preference=fixed-vlmax. > > vuint8m1_t test () { > uint8_t arr[32] = { > 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, > 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, > }; > > return __riscv_vle8_v_u8m1(arr, 32); > } > > Before this patch: > test: > lui a5,%hi(.LANCHOR0) > addi sp,sp,-32 > addi a5,a5,%lo(.LANCHOR0) > li a3,32 > vl2re64.v v2,0(a5) > vsetvli zero,a3,e8,m1,ta,ma > vs2r.v v2,0(sp) <== Unnecessary store to stack > vle8.v v1,0(sp) <== Ditto > vs1r.v v1,0(a0) > addi sp,sp,32 > jr ra > > After this patch: > test: > lui a5,%hi(.LANCHOR0) > addi a5,a5,%lo(.LANCHOR0) > li a4,32 > addi sp,sp,-32 > vsetvli zero,a4,e8,m1,ta,ma > vle8.v v1,0(a5) > vs1r.v v1,0(a0) > addi sp,sp,32 > jr ra > > Below tests are passed within this patch: > * The risc-v regression test. > * The x86 bootstrap and regression test. > * The aarch64 regression test. > > PR target/111720 > > gcc/ChangeLog: > > * dse.cc (get_stored_val): Allow vector mode if read size is > less than or equal to stored size. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/pr111720-0.c: New test. > * gcc.target/riscv/rvv/base/pr111720-1.c: New test. > * gcc.target/riscv/rvv/base/pr111720-10.c: New test. > * gcc.target/riscv/rvv/base/pr111720-2.c: New test. > * gcc.target/riscv/rvv/base/pr111720-3.c: New test. > * gcc.target/riscv/rvv/base/pr111720-4.c: New test. > * gcc.target/riscv/rvv/base/pr111720-5.c: New test. > * gcc.target/riscv/rvv/base/pr111720-6.c: New test. > * gcc.target/riscv/rvv/base/pr111720-7.c: New test. > * gcc.target/riscv/rvv/base/pr111720-8.c: New test. > * gcc.target/riscv/rvv/base/pr111720-9.c: New test. OK for the trunk. > > + else if (VECTOR_MODE_P (read_mode) && VECTOR_MODE_P (store_mode) > + && known_le (GET_MODE_BITSIZE (read_mode), GET_MODE_BITSIZE (store_mode)) > + && targetm.modes_tieable_p (read_mode, store_mode)) > + read_reg = gen_lowpart (read_mode, copy_rtx (store_info->rhs)); > else > read_reg = extract_low_bits (read_mode, store_mode, > copy_rtx (store_info->rhs)); It may not matter, especially for RV, but we could possibly have a mixture of scalar and vector modes in the RTL. Say a vector store followed by a scalar read or vice-versa. I wouldn't try to handle that case unless we had actual evidence it was useful to do so. Just wanted to point out that unlike pseudos we can have multiple modes referencing the same memory location. Jeff
Sorry for disturbing, looks I have a typo for Richard S's email address, cc the right email address for awareness. Pan -----Original Message----- From: Li, Pan2 Sent: Wednesday, November 15, 2023 8:18 AM To: Jeff Law <jeffreyalaw@gmail.com>; gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; richard.guenther@gmail.com; richard.sandiford@arm.com2 Subject: RE: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store > I wouldn't try to handle that case unless we had actual evidence it was > useful to do so. Just wanted to point out that unlike pseudos we can > have multiple modes referencing the same memory location. Got the point here, thanks Jeff for emphasizing this, 😉. Pan -----Original Message----- From: Jeff Law <jeffreyalaw@gmail.com> Sent: Tuesday, November 14, 2023 4:12 AM To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; richard.guenther@gmail.com; richard.sandiford@arm.com2 Subject: Re: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store On 11/12/23 20:22, pan2.li@intel.com wrote: > From: Pan Li <pan2.li@intel.com> > > Update in v4: > * Merge upstream and removed some independent changes. > > Update in v3: > * Take known_le instead of known_lt for vector size. > * Return NULL_RTX when gap is not equal 0 and not constant. > > Update in v2: > * Move vector type support to get_stored_val. > > Original log: > > This patch would like to allow the vector mode in the > get_stored_val in the DSE. It is valid for the read > rtx if and only if the read bitsize is less than the > stored bitsize. > > Given below example code with > --param=riscv-autovec-preference=fixed-vlmax. > > vuint8m1_t test () { > uint8_t arr[32] = { > 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, > 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, > }; > > return __riscv_vle8_v_u8m1(arr, 32); > } > > Before this patch: > test: > lui a5,%hi(.LANCHOR0) > addi sp,sp,-32 > addi a5,a5,%lo(.LANCHOR0) > li a3,32 > vl2re64.v v2,0(a5) > vsetvli zero,a3,e8,m1,ta,ma > vs2r.v v2,0(sp) <== Unnecessary store to stack > vle8.v v1,0(sp) <== Ditto > vs1r.v v1,0(a0) > addi sp,sp,32 > jr ra > > After this patch: > test: > lui a5,%hi(.LANCHOR0) > addi a5,a5,%lo(.LANCHOR0) > li a4,32 > addi sp,sp,-32 > vsetvli zero,a4,e8,m1,ta,ma > vle8.v v1,0(a5) > vs1r.v v1,0(a0) > addi sp,sp,32 > jr ra > > Below tests are passed within this patch: > * The risc-v regression test. > * The x86 bootstrap and regression test. > * The aarch64 regression test. > > PR target/111720 > > gcc/ChangeLog: > > * dse.cc (get_stored_val): Allow vector mode if read size is > less than or equal to stored size. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/pr111720-0.c: New test. > * gcc.target/riscv/rvv/base/pr111720-1.c: New test. > * gcc.target/riscv/rvv/base/pr111720-10.c: New test. > * gcc.target/riscv/rvv/base/pr111720-2.c: New test. > * gcc.target/riscv/rvv/base/pr111720-3.c: New test. > * gcc.target/riscv/rvv/base/pr111720-4.c: New test. > * gcc.target/riscv/rvv/base/pr111720-5.c: New test. > * gcc.target/riscv/rvv/base/pr111720-6.c: New test. > * gcc.target/riscv/rvv/base/pr111720-7.c: New test. > * gcc.target/riscv/rvv/base/pr111720-8.c: New test. > * gcc.target/riscv/rvv/base/pr111720-9.c: New test. OK for the trunk. > > + else if (VECTOR_MODE_P (read_mode) && VECTOR_MODE_P (store_mode) > + && known_le (GET_MODE_BITSIZE (read_mode), GET_MODE_BITSIZE (store_mode)) > + && targetm.modes_tieable_p (read_mode, store_mode)) > + read_reg = gen_lowpart (read_mode, copy_rtx (store_info->rhs)); > else > read_reg = extract_low_bits (read_mode, store_mode, > copy_rtx (store_info->rhs)); It may not matter, especially for RV, but we could possibly have a mixture of scalar and vector modes in the RTL. Say a vector store followed by a scalar read or vice-versa. I wouldn't try to handle that case unless we had actual evidence it was useful to do so. Just wanted to point out that unlike pseudos we can have multiple modes referencing the same memory location. Jeff
Hi Richard S, Thanks a lot for reviewing and comments. May I know is there any concern or further comments for landing this patch to GCC-14? Pan -----Original Message----- From: Li, Pan2 Sent: Wednesday, November 15, 2023 8:25 AM To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; richard.guenther@gmail.com; richard.sandiford@arm.com; Jeff Law <jeffreyalaw@gmail.com> Subject: RE: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store Sorry for disturbing, looks I have a typo for Richard S's email address, cc the right email address for awareness. Pan -----Original Message----- From: Li, Pan2 Sent: Wednesday, November 15, 2023 8:18 AM To: Jeff Law <jeffreyalaw@gmail.com>; gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; richard.guenther@gmail.com; richard.sandiford@arm.com2 Subject: RE: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store > I wouldn't try to handle that case unless we had actual evidence it was > useful to do so. Just wanted to point out that unlike pseudos we can > have multiple modes referencing the same memory location. Got the point here, thanks Jeff for emphasizing this, 😉. Pan -----Original Message----- From: Jeff Law <jeffreyalaw@gmail.com> Sent: Tuesday, November 14, 2023 4:12 AM To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; richard.guenther@gmail.com; richard.sandiford@arm.com2 Subject: Re: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store On 11/12/23 20:22, pan2.li@intel.com wrote: > From: Pan Li <pan2.li@intel.com> > > Update in v4: > * Merge upstream and removed some independent changes. > > Update in v3: > * Take known_le instead of known_lt for vector size. > * Return NULL_RTX when gap is not equal 0 and not constant. > > Update in v2: > * Move vector type support to get_stored_val. > > Original log: > > This patch would like to allow the vector mode in the > get_stored_val in the DSE. It is valid for the read > rtx if and only if the read bitsize is less than the > stored bitsize. > > Given below example code with > --param=riscv-autovec-preference=fixed-vlmax. > > vuint8m1_t test () { > uint8_t arr[32] = { > 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, > 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, > }; > > return __riscv_vle8_v_u8m1(arr, 32); > } > > Before this patch: > test: > lui a5,%hi(.LANCHOR0) > addi sp,sp,-32 > addi a5,a5,%lo(.LANCHOR0) > li a3,32 > vl2re64.v v2,0(a5) > vsetvli zero,a3,e8,m1,ta,ma > vs2r.v v2,0(sp) <== Unnecessary store to stack > vle8.v v1,0(sp) <== Ditto > vs1r.v v1,0(a0) > addi sp,sp,32 > jr ra > > After this patch: > test: > lui a5,%hi(.LANCHOR0) > addi a5,a5,%lo(.LANCHOR0) > li a4,32 > addi sp,sp,-32 > vsetvli zero,a4,e8,m1,ta,ma > vle8.v v1,0(a5) > vs1r.v v1,0(a0) > addi sp,sp,32 > jr ra > > Below tests are passed within this patch: > * The risc-v regression test. > * The x86 bootstrap and regression test. > * The aarch64 regression test. > > PR target/111720 > > gcc/ChangeLog: > > * dse.cc (get_stored_val): Allow vector mode if read size is > less than or equal to stored size. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/pr111720-0.c: New test. > * gcc.target/riscv/rvv/base/pr111720-1.c: New test. > * gcc.target/riscv/rvv/base/pr111720-10.c: New test. > * gcc.target/riscv/rvv/base/pr111720-2.c: New test. > * gcc.target/riscv/rvv/base/pr111720-3.c: New test. > * gcc.target/riscv/rvv/base/pr111720-4.c: New test. > * gcc.target/riscv/rvv/base/pr111720-5.c: New test. > * gcc.target/riscv/rvv/base/pr111720-6.c: New test. > * gcc.target/riscv/rvv/base/pr111720-7.c: New test. > * gcc.target/riscv/rvv/base/pr111720-8.c: New test. > * gcc.target/riscv/rvv/base/pr111720-9.c: New test. OK for the trunk. > > + else if (VECTOR_MODE_P (read_mode) && VECTOR_MODE_P (store_mode) > + && known_le (GET_MODE_BITSIZE (read_mode), GET_MODE_BITSIZE (store_mode)) > + && targetm.modes_tieable_p (read_mode, store_mode)) > + read_reg = gen_lowpart (read_mode, copy_rtx (store_info->rhs)); > else > read_reg = extract_low_bits (read_mode, store_mode, > copy_rtx (store_info->rhs)); It may not matter, especially for RV, but we could possibly have a mixture of scalar and vector modes in the RTL. Say a vector store followed by a scalar read or vice-versa. I wouldn't try to handle that case unless we had actual evidence it was useful to do so. Just wanted to point out that unlike pseudos we can have multiple modes referencing the same memory location. Jeff
On Wed, Nov 22, 2023 at 3:30 AM Li, Pan2 <pan2.li@intel.com> wrote: > > Hi Richard S, > > Thanks a lot for reviewing and comments. May I know is there any concern or further comments for landing this patch to GCC-14? It looks like Jeff approved the patch? Richard. > Pan > > -----Original Message----- > From: Li, Pan2 > Sent: Wednesday, November 15, 2023 8:25 AM > To: gcc-patches@gcc.gnu.org > Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; richard.guenther@gmail.com; richard.sandiford@arm.com; Jeff Law <jeffreyalaw@gmail.com> > Subject: RE: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store > > Sorry for disturbing, looks I have a typo for Richard S's email address, cc the right email address for awareness. > > Pan > > -----Original Message----- > From: Li, Pan2 > Sent: Wednesday, November 15, 2023 8:18 AM > To: Jeff Law <jeffreyalaw@gmail.com>; gcc-patches@gcc.gnu.org > Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; richard.guenther@gmail.com; richard.sandiford@arm.com2 > Subject: RE: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store > > > I wouldn't try to handle that case unless we had actual evidence it was > > useful to do so. Just wanted to point out that unlike pseudos we can > > have multiple modes referencing the same memory location. > > Got the point here, thanks Jeff for emphasizing this, 😉. > > Pan > > -----Original Message----- > From: Jeff Law <jeffreyalaw@gmail.com> > Sent: Tuesday, November 14, 2023 4:12 AM > To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org > Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; richard.guenther@gmail.com; richard.sandiford@arm.com2 > Subject: Re: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store > > > > On 11/12/23 20:22, pan2.li@intel.com wrote: > > From: Pan Li <pan2.li@intel.com> > > > > Update in v4: > > * Merge upstream and removed some independent changes. > > > > Update in v3: > > * Take known_le instead of known_lt for vector size. > > * Return NULL_RTX when gap is not equal 0 and not constant. > > > > Update in v2: > > * Move vector type support to get_stored_val. > > > > Original log: > > > > This patch would like to allow the vector mode in the > > get_stored_val in the DSE. It is valid for the read > > rtx if and only if the read bitsize is less than the > > stored bitsize. > > > > Given below example code with > > --param=riscv-autovec-preference=fixed-vlmax. > > > > vuint8m1_t test () { > > uint8_t arr[32] = { > > 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, > > 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, > > }; > > > > return __riscv_vle8_v_u8m1(arr, 32); > > } > > > > Before this patch: > > test: > > lui a5,%hi(.LANCHOR0) > > addi sp,sp,-32 > > addi a5,a5,%lo(.LANCHOR0) > > li a3,32 > > vl2re64.v v2,0(a5) > > vsetvli zero,a3,e8,m1,ta,ma > > vs2r.v v2,0(sp) <== Unnecessary store to stack > > vle8.v v1,0(sp) <== Ditto > > vs1r.v v1,0(a0) > > addi sp,sp,32 > > jr ra > > > > After this patch: > > test: > > lui a5,%hi(.LANCHOR0) > > addi a5,a5,%lo(.LANCHOR0) > > li a4,32 > > addi sp,sp,-32 > > vsetvli zero,a4,e8,m1,ta,ma > > vle8.v v1,0(a5) > > vs1r.v v1,0(a0) > > addi sp,sp,32 > > jr ra > > > > Below tests are passed within this patch: > > * The risc-v regression test. > > * The x86 bootstrap and regression test. > > * The aarch64 regression test. > > > > PR target/111720 > > > > gcc/ChangeLog: > > > > * dse.cc (get_stored_val): Allow vector mode if read size is > > less than or equal to stored size. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/rvv/base/pr111720-0.c: New test. > > * gcc.target/riscv/rvv/base/pr111720-1.c: New test. > > * gcc.target/riscv/rvv/base/pr111720-10.c: New test. > > * gcc.target/riscv/rvv/base/pr111720-2.c: New test. > > * gcc.target/riscv/rvv/base/pr111720-3.c: New test. > > * gcc.target/riscv/rvv/base/pr111720-4.c: New test. > > * gcc.target/riscv/rvv/base/pr111720-5.c: New test. > > * gcc.target/riscv/rvv/base/pr111720-6.c: New test. > > * gcc.target/riscv/rvv/base/pr111720-7.c: New test. > > * gcc.target/riscv/rvv/base/pr111720-8.c: New test. > > * gcc.target/riscv/rvv/base/pr111720-9.c: New test. > OK for the trunk. > > > > > > > + else if (VECTOR_MODE_P (read_mode) && VECTOR_MODE_P (store_mode) > > + && known_le (GET_MODE_BITSIZE (read_mode), GET_MODE_BITSIZE (store_mode)) > > + && targetm.modes_tieable_p (read_mode, store_mode)) > > + read_reg = gen_lowpart (read_mode, copy_rtx (store_info->rhs)); > > else > > read_reg = extract_low_bits (read_mode, store_mode, > > copy_rtx (store_info->rhs)); > It may not matter, especially for RV, but we could possibly have a > mixture of scalar and vector modes in the RTL. Say a vector store > followed by a scalar read or vice-versa. > > I wouldn't try to handle that case unless we had actual evidence it was > useful to do so. Just wanted to point out that unlike pseudos we can > have multiple modes referencing the same memory location. > > Jeff
> It looks like Jeff approved the patch? Yes, just would like to double check the way of this patch is expected as following the suggestion of Richard S. Pan -----Original Message----- From: Richard Biener <richard.guenther@gmail.com> Sent: Wednesday, November 22, 2023 4:02 PM To: Li, Pan2 <pan2.li@intel.com> Cc: richard.sandiford@arm.com; juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; Jeff Law <jeffreyalaw@gmail.com>; gcc-patches@gcc.gnu.org Subject: Re: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store On Wed, Nov 22, 2023 at 3:30 AM Li, Pan2 <pan2.li@intel.com> wrote: > > Hi Richard S, > > Thanks a lot for reviewing and comments. May I know is there any concern or further comments for landing this patch to GCC-14? It looks like Jeff approved the patch? Richard. > Pan > > -----Original Message----- > From: Li, Pan2 > Sent: Wednesday, November 15, 2023 8:25 AM > To: gcc-patches@gcc.gnu.org > Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; richard.guenther@gmail.com; richard.sandiford@arm.com; Jeff Law <jeffreyalaw@gmail.com> > Subject: RE: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store > > Sorry for disturbing, looks I have a typo for Richard S's email address, cc the right email address for awareness. > > Pan > > -----Original Message----- > From: Li, Pan2 > Sent: Wednesday, November 15, 2023 8:18 AM > To: Jeff Law <jeffreyalaw@gmail.com>; gcc-patches@gcc.gnu.org > Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; richard.guenther@gmail.com; richard.sandiford@arm.com2 > Subject: RE: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store > > > I wouldn't try to handle that case unless we had actual evidence it was > > useful to do so. Just wanted to point out that unlike pseudos we can > > have multiple modes referencing the same memory location. > > Got the point here, thanks Jeff for emphasizing this, 😉. > > Pan > > -----Original Message----- > From: Jeff Law <jeffreyalaw@gmail.com> > Sent: Tuesday, November 14, 2023 4:12 AM > To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org > Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; richard.guenther@gmail.com; richard.sandiford@arm.com2 > Subject: Re: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store > > > > On 11/12/23 20:22, pan2.li@intel.com wrote: > > From: Pan Li <pan2.li@intel.com> > > > > Update in v4: > > * Merge upstream and removed some independent changes. > > > > Update in v3: > > * Take known_le instead of known_lt for vector size. > > * Return NULL_RTX when gap is not equal 0 and not constant. > > > > Update in v2: > > * Move vector type support to get_stored_val. > > > > Original log: > > > > This patch would like to allow the vector mode in the > > get_stored_val in the DSE. It is valid for the read > > rtx if and only if the read bitsize is less than the > > stored bitsize. > > > > Given below example code with > > --param=riscv-autovec-preference=fixed-vlmax. > > > > vuint8m1_t test () { > > uint8_t arr[32] = { > > 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, > > 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, > > }; > > > > return __riscv_vle8_v_u8m1(arr, 32); > > } > > > > Before this patch: > > test: > > lui a5,%hi(.LANCHOR0) > > addi sp,sp,-32 > > addi a5,a5,%lo(.LANCHOR0) > > li a3,32 > > vl2re64.v v2,0(a5) > > vsetvli zero,a3,e8,m1,ta,ma > > vs2r.v v2,0(sp) <== Unnecessary store to stack > > vle8.v v1,0(sp) <== Ditto > > vs1r.v v1,0(a0) > > addi sp,sp,32 > > jr ra > > > > After this patch: > > test: > > lui a5,%hi(.LANCHOR0) > > addi a5,a5,%lo(.LANCHOR0) > > li a4,32 > > addi sp,sp,-32 > > vsetvli zero,a4,e8,m1,ta,ma > > vle8.v v1,0(a5) > > vs1r.v v1,0(a0) > > addi sp,sp,32 > > jr ra > > > > Below tests are passed within this patch: > > * The risc-v regression test. > > * The x86 bootstrap and regression test. > > * The aarch64 regression test. > > > > PR target/111720 > > > > gcc/ChangeLog: > > > > * dse.cc (get_stored_val): Allow vector mode if read size is > > less than or equal to stored size. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/rvv/base/pr111720-0.c: New test. > > * gcc.target/riscv/rvv/base/pr111720-1.c: New test. > > * gcc.target/riscv/rvv/base/pr111720-10.c: New test. > > * gcc.target/riscv/rvv/base/pr111720-2.c: New test. > > * gcc.target/riscv/rvv/base/pr111720-3.c: New test. > > * gcc.target/riscv/rvv/base/pr111720-4.c: New test. > > * gcc.target/riscv/rvv/base/pr111720-5.c: New test. > > * gcc.target/riscv/rvv/base/pr111720-6.c: New test. > > * gcc.target/riscv/rvv/base/pr111720-7.c: New test. > > * gcc.target/riscv/rvv/base/pr111720-8.c: New test. > > * gcc.target/riscv/rvv/base/pr111720-9.c: New test. > OK for the trunk. > > > > > > > + else if (VECTOR_MODE_P (read_mode) && VECTOR_MODE_P (store_mode) > > + && known_le (GET_MODE_BITSIZE (read_mode), GET_MODE_BITSIZE (store_mode)) > > + && targetm.modes_tieable_p (read_mode, store_mode)) > > + read_reg = gen_lowpart (read_mode, copy_rtx (store_info->rhs)); > > else > > read_reg = extract_low_bits (read_mode, store_mode, > > copy_rtx (store_info->rhs)); > It may not matter, especially for RV, but we could possibly have a > mixture of scalar and vector modes in the RTL. Say a vector store > followed by a scalar read or vice-versa. > > I wouldn't try to handle that case unless we had actual evidence it was > useful to do so. Just wanted to point out that unlike pseudos we can > have multiple modes referencing the same memory location. > > Jeff
"Li, Pan2" <pan2.li@intel.com> writes: >> It looks like Jeff approved the patch? > > Yes, just would like to double check the way of this patch is expected as following the suggestion of Richard S. Yeah, it looks good to me, thanks. Richard > Pan > > -----Original Message----- > From: Richard Biener <richard.guenther@gmail.com> > Sent: Wednesday, November 22, 2023 4:02 PM > To: Li, Pan2 <pan2.li@intel.com> > Cc: richard.sandiford@arm.com; juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; Jeff Law <jeffreyalaw@gmail.com>; gcc-patches@gcc.gnu.org > Subject: Re: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store > > On Wed, Nov 22, 2023 at 3:30 AM Li, Pan2 <pan2.li@intel.com> wrote: >> >> Hi Richard S, >> >> Thanks a lot for reviewing and comments. May I know is there any concern or further comments for landing this patch to GCC-14? > > It looks like Jeff approved the patch? > > Richard. > >> Pan >> >> -----Original Message----- >> From: Li, Pan2 >> Sent: Wednesday, November 15, 2023 8:25 AM >> To: gcc-patches@gcc.gnu.org >> Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; richard.guenther@gmail.com; richard.sandiford@arm.com; Jeff Law <jeffreyalaw@gmail.com> >> Subject: RE: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store >> >> Sorry for disturbing, looks I have a typo for Richard S's email address, cc the right email address for awareness. >> >> Pan >> >> -----Original Message----- >> From: Li, Pan2 >> Sent: Wednesday, November 15, 2023 8:18 AM >> To: Jeff Law <jeffreyalaw@gmail.com>; gcc-patches@gcc.gnu.org >> Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; richard.guenther@gmail.com; richard.sandiford@arm.com2 >> Subject: RE: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store >> >> > I wouldn't try to handle that case unless we had actual evidence it was >> > useful to do so. Just wanted to point out that unlike pseudos we can >> > have multiple modes referencing the same memory location. >> >> Got the point here, thanks Jeff for emphasizing this, 😉. >> >> Pan >> >> -----Original Message----- >> From: Jeff Law <jeffreyalaw@gmail.com> >> Sent: Tuesday, November 14, 2023 4:12 AM >> To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org >> Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; richard.guenther@gmail.com; richard.sandiford@arm.com2 >> Subject: Re: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store >> >> >> >> On 11/12/23 20:22, pan2.li@intel.com wrote: >> > From: Pan Li <pan2.li@intel.com> >> > >> > Update in v4: >> > * Merge upstream and removed some independent changes. >> > >> > Update in v3: >> > * Take known_le instead of known_lt for vector size. >> > * Return NULL_RTX when gap is not equal 0 and not constant. >> > >> > Update in v2: >> > * Move vector type support to get_stored_val. >> > >> > Original log: >> > >> > This patch would like to allow the vector mode in the >> > get_stored_val in the DSE. It is valid for the read >> > rtx if and only if the read bitsize is less than the >> > stored bitsize. >> > >> > Given below example code with >> > --param=riscv-autovec-preference=fixed-vlmax. >> > >> > vuint8m1_t test () { >> > uint8_t arr[32] = { >> > 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, >> > 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, >> > }; >> > >> > return __riscv_vle8_v_u8m1(arr, 32); >> > } >> > >> > Before this patch: >> > test: >> > lui a5,%hi(.LANCHOR0) >> > addi sp,sp,-32 >> > addi a5,a5,%lo(.LANCHOR0) >> > li a3,32 >> > vl2re64.v v2,0(a5) >> > vsetvli zero,a3,e8,m1,ta,ma >> > vs2r.v v2,0(sp) <== Unnecessary store to stack >> > vle8.v v1,0(sp) <== Ditto >> > vs1r.v v1,0(a0) >> > addi sp,sp,32 >> > jr ra >> > >> > After this patch: >> > test: >> > lui a5,%hi(.LANCHOR0) >> > addi a5,a5,%lo(.LANCHOR0) >> > li a4,32 >> > addi sp,sp,-32 >> > vsetvli zero,a4,e8,m1,ta,ma >> > vle8.v v1,0(a5) >> > vs1r.v v1,0(a0) >> > addi sp,sp,32 >> > jr ra >> > >> > Below tests are passed within this patch: >> > * The risc-v regression test. >> > * The x86 bootstrap and regression test. >> > * The aarch64 regression test. >> > >> > PR target/111720 >> > >> > gcc/ChangeLog: >> > >> > * dse.cc (get_stored_val): Allow vector mode if read size is >> > less than or equal to stored size. >> > >> > gcc/testsuite/ChangeLog: >> > >> > * gcc.target/riscv/rvv/base/pr111720-0.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-1.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-10.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-2.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-3.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-4.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-5.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-6.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-7.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-8.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-9.c: New test. >> OK for the trunk. >> >> >> > >> >> > + else if (VECTOR_MODE_P (read_mode) && VECTOR_MODE_P (store_mode) >> > + && known_le (GET_MODE_BITSIZE (read_mode), GET_MODE_BITSIZE (store_mode)) >> > + && targetm.modes_tieable_p (read_mode, store_mode)) >> > + read_reg = gen_lowpart (read_mode, copy_rtx (store_info->rhs)); >> > else >> > read_reg = extract_low_bits (read_mode, store_mode, >> > copy_rtx (store_info->rhs)); >> It may not matter, especially for RV, but we could possibly have a >> mixture of scalar and vector modes in the RTL. Say a vector store >> followed by a scalar read or vice-versa. >> >> I wouldn't try to handle that case unless we had actual evidence it was >> useful to do so. Just wanted to point out that unlike pseudos we can >> have multiple modes referencing the same memory location. >> >> Jeff
Committed, thanks all. Pan -----Original Message----- From: Richard Sandiford <richard.sandiford@arm.com> Sent: Thursday, November 23, 2023 2:39 AM To: Li, Pan2 <pan2.li@intel.com> Cc: Richard Biener <richard.guenther@gmail.com>; juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; Jeff Law <jeffreyalaw@gmail.com>; gcc-patches@gcc.gnu.org Subject: Re: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store "Li, Pan2" <pan2.li@intel.com> writes: >> It looks like Jeff approved the patch? > > Yes, just would like to double check the way of this patch is expected as following the suggestion of Richard S. Yeah, it looks good to me, thanks. Richard > Pan > > -----Original Message----- > From: Richard Biener <richard.guenther@gmail.com> > Sent: Wednesday, November 22, 2023 4:02 PM > To: Li, Pan2 <pan2.li@intel.com> > Cc: richard.sandiford@arm.com; juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; Jeff Law <jeffreyalaw@gmail.com>; gcc-patches@gcc.gnu.org > Subject: Re: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store > > On Wed, Nov 22, 2023 at 3:30 AM Li, Pan2 <pan2.li@intel.com> wrote: >> >> Hi Richard S, >> >> Thanks a lot for reviewing and comments. May I know is there any concern or further comments for landing this patch to GCC-14? > > It looks like Jeff approved the patch? > > Richard. > >> Pan >> >> -----Original Message----- >> From: Li, Pan2 >> Sent: Wednesday, November 15, 2023 8:25 AM >> To: gcc-patches@gcc.gnu.org >> Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; richard.guenther@gmail.com; richard.sandiford@arm.com; Jeff Law <jeffreyalaw@gmail.com> >> Subject: RE: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store >> >> Sorry for disturbing, looks I have a typo for Richard S's email address, cc the right email address for awareness. >> >> Pan >> >> -----Original Message----- >> From: Li, Pan2 >> Sent: Wednesday, November 15, 2023 8:18 AM >> To: Jeff Law <jeffreyalaw@gmail.com>; gcc-patches@gcc.gnu.org >> Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; richard.guenther@gmail.com; richard.sandiford@arm.com2 >> Subject: RE: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store >> >> > I wouldn't try to handle that case unless we had actual evidence it was >> > useful to do so. Just wanted to point out that unlike pseudos we can >> > have multiple modes referencing the same memory location. >> >> Got the point here, thanks Jeff for emphasizing this, 😉. >> >> Pan >> >> -----Original Message----- >> From: Jeff Law <jeffreyalaw@gmail.com> >> Sent: Tuesday, November 14, 2023 4:12 AM >> To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org >> Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; richard.guenther@gmail.com; richard.sandiford@arm.com2 >> Subject: Re: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store >> >> >> >> On 11/12/23 20:22, pan2.li@intel.com wrote: >> > From: Pan Li <pan2.li@intel.com> >> > >> > Update in v4: >> > * Merge upstream and removed some independent changes. >> > >> > Update in v3: >> > * Take known_le instead of known_lt for vector size. >> > * Return NULL_RTX when gap is not equal 0 and not constant. >> > >> > Update in v2: >> > * Move vector type support to get_stored_val. >> > >> > Original log: >> > >> > This patch would like to allow the vector mode in the >> > get_stored_val in the DSE. It is valid for the read >> > rtx if and only if the read bitsize is less than the >> > stored bitsize. >> > >> > Given below example code with >> > --param=riscv-autovec-preference=fixed-vlmax. >> > >> > vuint8m1_t test () { >> > uint8_t arr[32] = { >> > 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, >> > 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, >> > }; >> > >> > return __riscv_vle8_v_u8m1(arr, 32); >> > } >> > >> > Before this patch: >> > test: >> > lui a5,%hi(.LANCHOR0) >> > addi sp,sp,-32 >> > addi a5,a5,%lo(.LANCHOR0) >> > li a3,32 >> > vl2re64.v v2,0(a5) >> > vsetvli zero,a3,e8,m1,ta,ma >> > vs2r.v v2,0(sp) <== Unnecessary store to stack >> > vle8.v v1,0(sp) <== Ditto >> > vs1r.v v1,0(a0) >> > addi sp,sp,32 >> > jr ra >> > >> > After this patch: >> > test: >> > lui a5,%hi(.LANCHOR0) >> > addi a5,a5,%lo(.LANCHOR0) >> > li a4,32 >> > addi sp,sp,-32 >> > vsetvli zero,a4,e8,m1,ta,ma >> > vle8.v v1,0(a5) >> > vs1r.v v1,0(a0) >> > addi sp,sp,32 >> > jr ra >> > >> > Below tests are passed within this patch: >> > * The risc-v regression test. >> > * The x86 bootstrap and regression test. >> > * The aarch64 regression test. >> > >> > PR target/111720 >> > >> > gcc/ChangeLog: >> > >> > * dse.cc (get_stored_val): Allow vector mode if read size is >> > less than or equal to stored size. >> > >> > gcc/testsuite/ChangeLog: >> > >> > * gcc.target/riscv/rvv/base/pr111720-0.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-1.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-10.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-2.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-3.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-4.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-5.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-6.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-7.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-8.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-9.c: New test. >> OK for the trunk. >> >> >> > >> >> > + else if (VECTOR_MODE_P (read_mode) && VECTOR_MODE_P (store_mode) >> > + && known_le (GET_MODE_BITSIZE (read_mode), GET_MODE_BITSIZE (store_mode)) >> > + && targetm.modes_tieable_p (read_mode, store_mode)) >> > + read_reg = gen_lowpart (read_mode, copy_rtx (store_info->rhs)); >> > else >> > read_reg = extract_low_bits (read_mode, store_mode, >> > copy_rtx (store_info->rhs)); >> It may not matter, especially for RV, but we could possibly have a >> mixture of scalar and vector modes in the RTL. Say a vector store >> followed by a scalar read or vice-versa. >> >> I wouldn't try to handle that case unless we had actual evidence it was >> useful to do so. Just wanted to point out that unlike pseudos we can >> have multiple modes referencing the same memory location. >> >> Jeff
diff --git a/gcc/dse.cc b/gcc/dse.cc index 1a85dae1f8c..40c4c29d07e 100644 --- a/gcc/dse.cc +++ b/gcc/dse.cc @@ -1900,8 +1900,11 @@ get_stored_val (store_info *store_info, machine_mode read_mode, else gap = read_offset - store_info->offset; - if (gap.is_constant () && maybe_ne (gap, 0)) + if (maybe_ne (gap, 0)) { + if (!gap.is_constant ()) + return NULL_RTX; + poly_int64 shift = gap * BITS_PER_UNIT; poly_int64 access_size = GET_MODE_SIZE (read_mode) + gap; read_reg = find_shift_sequence (access_size, store_info, read_mode, @@ -1940,6 +1943,10 @@ get_stored_val (store_info *store_info, machine_mode read_mode, || GET_MODE_CLASS (read_mode) != GET_MODE_CLASS (store_mode))) read_reg = extract_low_bits (read_mode, store_mode, copy_rtx (store_info->const_rhs)); + else if (VECTOR_MODE_P (read_mode) && VECTOR_MODE_P (store_mode) + && known_le (GET_MODE_BITSIZE (read_mode), GET_MODE_BITSIZE (store_mode)) + && targetm.modes_tieable_p (read_mode, store_mode)) + read_reg = gen_lowpart (read_mode, copy_rtx (store_info->rhs)); else read_reg = extract_low_bits (read_mode, store_mode, copy_rtx (store_info->rhs)); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c new file mode 100644 index 00000000000..a61e94a6d98 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint8m1_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vle8_v_u8m1(arr, 32); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c new file mode 100644 index 00000000000..46efd7379ac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint8m2_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vle8_v_u8m2(arr, 32); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[09]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c new file mode 100644 index 00000000000..8bebac219a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vbool4_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vlm_v_b4(arr, 32); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c new file mode 100644 index 00000000000..47e4243e02e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint8m1_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vle8_v_u8m1(arr, 16); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c new file mode 100644 index 00000000000..5331e547ed3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint8m2_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vle8_v_u8m2(arr, 8); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[09]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c new file mode 100644 index 00000000000..0c728f93514 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint8mf2_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vle8_v_u8mf2(arr, 32); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c new file mode 100644 index 00000000000..ccfc40cd382 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint8m2_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vle8_v_u8m2(arr, 4); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[09]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c new file mode 100644 index 00000000000..ce7ddbb99b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint8m8_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vle8_v_u8m8(arr, 32); +} + +/* { dg-final { scan-assembler-times {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} 1 } } */ +/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c new file mode 100644 index 00000000000..ac0100a1211 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vbool8_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + vuint8m1_t varr = __riscv_vle8_v_u8m1(arr, 32); + vuint8m1_t vand_m = __riscv_vand_vx_u8m1(varr, 1, 32); + + return __riscv_vreinterpret_v_u8m1_b8(vand_m); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c new file mode 100644 index 00000000000..b7ebef80954 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vfloat32m1_t test () { + float arr[32] = { + 1.0, 2.2, 7.8, 1.2, 3.3, 4.7, 5.5, 3.3, + 1.0, 0.2, 1.8, 2.2, 4.3, 4.7, 9.5, 9.3, + 1.0, 2.2, 7.8, 1.2, 3.3, 4.7, 5.5, 3.3, + 1.0, 0.2, 1.8, 2.2, 4.3, 4.7, 9.5, 9.3, + }; + + return __riscv_vle32_v_f32m1(arr, 32); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c new file mode 100644 index 00000000000..21fed06d201 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vfloat64m8_t test () { + double arr[8] = { + 1.0, 2.2, 7.8, 1.2, 3.3, 4.7, 5.5, 3.3, + }; + + return __riscv_vle64_v_f64m8(arr, 4); +} + +/* { dg-final { scan-assembler-times {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} 1 } } */ +/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} 1 } } */