diff mbox series

RISC-V: Add Types to Un-Typed Vector Instructions:

Message ID 20230828190432.2530773-1-ewlu@rivosinc.com
State New
Headers show
Series RISC-V: Add Types to Un-Typed Vector Instructions: | expand

Commit Message

Edwin Lu Aug. 28, 2023, 7:03 p.m. UTC 
Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5eb2@gmail.com/

This patch updates vector instructions to ensure that no insn is left
without a type attribute. Creates a placeholder type "vector" for insns
where a type isn't clear

Tested for regressions using rv32/rv64 gc/gcv multilib with newlib/linux. 

gcc/Changelog:

	* config/riscv/autovec-vls.md: Update types
	* config/riscv/riscv.md: Add vector placeholder type
	* config/riscv/vector.md: Update types

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
---
 gcc/config/riscv/autovec-vls.md | 15 ++++++++++++---
 gcc/config/riscv/riscv.md       |  3 ++-
 gcc/config/riscv/vector.md      | 17 ++++++++++++-----
 3 files changed, 26 insertions(+), 9 deletions(-)

Comments

Jeff Law Aug. 28, 2023, 9:45 p.m. UTC | #1 
On 8/28/23 13:03, Edwin Lu wrote:
> Related Discussion:
> https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5eb2@gmail.com/
> 
> This patch updates vector instructions to ensure that no insn is left
> without a type attribute. Creates a placeholder type "vector" for insns
> where a type isn't clear
> 
> Tested for regressions using rv32/rv64 gc/gcv multilib with newlib/linux.
> 
> gcc/Changelog:
> 
> 	* config/riscv/autovec-vls.md: Update types
> 	* config/riscv/riscv.md: Add vector placeholder type
> 	* config/riscv/vector.md: Update types
OK
jeff
>
Edwin Lu Aug. 29, 2023, 3:31 p.m. UTC | #2 
On 8/28/2023 2:45 PM, Jeff Law via Gcc-patches wrote:
> 
> 
> On 8/28/23 13:03, Edwin Lu wrote:
>> Related Discussion:
>> https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5eb2@gmail.com/
>>
>> This patch updates vector instructions to ensure that no insn is left
>> without a type attribute. Creates a placeholder type "vector" for insns
>> where a type isn't clear
>>
>> Tested for regressions using rv32/rv64 gc/gcv multilib with newlib/linux.
>>
>> gcc/Changelog:
>>
>>     * config/riscv/autovec-vls.md: Update types
>>     * config/riscv/riscv.md: Add vector placeholder type
>>     * config/riscv/vector.md: Update types
> OK
> jeff
>>
> 
Committed!

Edwin
diff mbox series

Patch

diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md
index 1b1d940d779..35b86de25c7 100644
--- a/gcc/config/riscv/autovec-vls.md
+++ b/gcc/config/riscv/autovec-vls.md
@@ -68,6 +68,7 @@  (define_insn_and_split "*mov<mode>_mem_to_mem"
       }
     DONE;
   }
+  [(set_attr "type" "vmov")]
 )
 
 (define_insn_and_split "*mov<mode>"
@@ -89,6 +90,7 @@  (define_insn_and_split "*mov<mode>"
     gcc_assert (ok_p);
     DONE;
   }
+  [(set_attr "type" "vmov")]
 )
 
 (define_expand "mov<mode>"
@@ -130,7 +132,9 @@  (define_insn_and_split "*mov<VLS_AVL_REG:mode><P:mode>_lra"
 					riscv_vector::RVV_UNOP, operands, operands[2]);
     }
   DONE;
-})
+}
+  [(set_attr "type" "vmov")]
+)
 
 (define_insn "*mov<mode>_vls"
   [(set (match_operand:VLS 0 "register_operand" "=vr")
@@ -157,6 +161,7 @@  (define_insn_and_split "@vec_duplicate<mode>"
                                    riscv_vector::RVV_UNOP, operands);
     DONE;
   }
+  [(set_attr "type" "vector")]
 )
 
 ;; -------------------------------------------------------------------------
@@ -180,7 +185,9 @@  (define_insn_and_split "<optab><mode>3"
   riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
 				 riscv_vector::RVV_BINOP, operands);
   DONE;
-})
+}
+[(set_attr "type" "vector")]
+)
 
 ;; -------------------------------------------------------------------------------
 ;; ---- [INT] Unary operations
@@ -201,4 +208,6 @@  (define_insn_and_split "<optab><mode>2"
   insn_code icode = code_for_pred (<CODE>, <MODE>mode);
   riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands);
   DONE;
-})
+}
+[(set_attr "type" "vector")]
+)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 47d14d99903..4d062307ad9 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -410,6 +410,7 @@  (define_attr "ext_enabled" "no,yes"
 ;; vgather      vector register gather instructions
 ;; vcompress    vector compress instruction
 ;; vmov         whole vector register move
+;; vector       unknown vector instruction
 (define_attr "type"
   "unknown,branch,jump,call,load,fpload,store,fpstore,
    mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
@@ -429,7 +430,7 @@  (define_attr "type"
    vired,viwred,vfredu,vfredo,vfwredu,vfwredo,
    vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv,
    vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,
-   vgather,vcompress,vmov"
+   vgather,vcompress,vmov,vector"
   (cond [(eq_attr "got" "load") (const_string "load")
 
 	 ;; If a doubleword move uses these expensive instructions,
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index a442e0fdd3c..ea836968878 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -878,13 +878,15 @@  (define_insn "@vundefined<mode>"
   [(set (match_operand:V 0 "register_operand" "=vr")
 	(unspec:V [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
   "TARGET_VECTOR"
-  "")
+  ""
+  [(set_attr "type" "vector")])
 
 (define_insn "@vundefined<mode>"
   [(set (match_operand:VB 0 "register_operand" "=vr")
 	(unspec:VB [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
   "TARGET_VECTOR"
-  "")
+  ""
+  [(set_attr "type" "vector")])
 
 (define_expand "@vreinterpret<mode>"
   [(set (match_operand:V 0 "register_operand")
@@ -935,7 +937,8 @@  (define_insn "@vlmax_avl<mode>"
   [(set (match_operand:P 0 "register_operand" "=r")
 	(unspec:P [(match_operand:P 1 "const_int_operand" "i")] UNSPEC_VLMAX))]
   "TARGET_VECTOR"
-  "")
+  ""
+  [(set_attr "type" "vector")])
 
 ;; Set VXRM
 (define_insn "vxrmsi"
@@ -1135,7 +1138,9 @@  (define_insn_and_split "*mov<V_FRACT:mode><P:mode>_lra"
 				     riscv_vector::RVV_UNOP, operands, operands[2]);
     }
   DONE;
-})
+}
+[(set_attr "type" "vector")]
+)
 
 (define_insn_and_split "*mov<VB:mode><P:mode>_lra"
   [(set (match_operand:VB 0 "reg_or_mem_operand" "=vr, m,vr")
@@ -1155,7 +1160,9 @@  (define_insn_and_split "*mov<VB:mode><P:mode>_lra"
 				     riscv_vector::RVV_UNOP, operands, operands[2]);
     }
   DONE;
-})
+}
+[(set_attr "type" "vector")]
+)
 
 ;; Define tuple modes data movement.
 ;; operands[2] is used to save the offset of each subpart.