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(jcmvbkbc-1-pt.tunnel.tserv24.sto1.ipv6.he.net. [2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id l14-v6sm460143ljh.91.2018.08.28.18.17.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 Aug 2018 18:17:07 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Tue, 28 Aug 2018 18:16:51 -0700 Message-Id: <20180829011652.4466-2-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180829011652.4466-1-jcmvbkbc@gmail.com> References: <20180829011652.4466-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::131 Subject: [Qemu-devel] [PATCH v2 1/2] target/xtensa: convert to do_transaction_failed X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Max Filippov Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Max Filippov Reviewed-by: Peter Maydell --- Changes v1->v2: - change ldl_phys to address_space_ldl in get_pte and check transaction for success; target/xtensa/cpu.c | 2 +- target/xtensa/cpu.h | 7 ++++--- target/xtensa/helper.c | 22 +++++++++++++++++++--- target/xtensa/op_helper.c | 12 +++++++----- 4 files changed, 31 insertions(+), 12 deletions(-) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 590813d4f7b9..a54dbe42602d 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -186,7 +186,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data) #else cc->do_unaligned_access = xtensa_cpu_do_unaligned_access; cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug; - cc->do_unassigned_access = xtensa_cpu_do_unassigned_access; + cc->do_transaction_failed = xtensa_cpu_do_transaction_failed; #endif cc->debug_excp_handler = xtensa_breakpoint_handler; cc->disas_set_info = xtensa_cpu_disas_set_info; diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 7472cf3ca32a..1362772617ea 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -497,9 +497,10 @@ int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int size, int mmu_idx); void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); -void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr, - bool is_write, bool is_exec, int opaque, - unsigned size); +void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, + unsigned size, MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr); void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index f74636f67854..0484f5fab808 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -642,11 +642,27 @@ static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0, &paddr, &page_size, &access, false); - qemu_log_mask(CPU_LOG_MMU, "%s: trying autorefill(%08x) -> %08x\n", - __func__, vaddr, ret ? ~0 : paddr); + if (ret == 0) { + qemu_log_mask(CPU_LOG_MMU, + "%s: autorefill(%08x): PTE va = %08x, pa = %08x\n", + __func__, vaddr, pt_vaddr, paddr); + } else { + qemu_log_mask(CPU_LOG_MMU, + "%s: autorefill(%08x): PTE va = %08x, failed (%d)\n", + __func__, vaddr, pt_vaddr, ret); + } if (ret == 0) { - *pte = ldl_phys(cs->as, paddr); + MemTxResult result; + + *pte = address_space_ldl(cs->as, paddr, MEMTXATTRS_UNSPECIFIED, + &result); + if (result != MEMTX_OK) { + qemu_log_mask(CPU_LOG_MMU, + "%s: couldn't load PTE: transaction failed (%u)\n", + __func__, (unsigned)result); + ret = 1; + } } return ret; } diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index d4c942d87980..06fe346f02ff 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -78,18 +78,20 @@ void tlb_fill(CPUState *cs, target_ulong vaddr, int size, } } -void xtensa_cpu_do_unassigned_access(CPUState *cs, hwaddr addr, - bool is_write, bool is_exec, int opaque, - unsigned size) +void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, + unsigned size, MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr) { XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = &cpu->env; + cpu_restore_state(cs, retaddr, true); HELPER(exception_cause_vaddr)(env, env->pc, - is_exec ? + access_type == MMU_INST_FETCH ? INSTR_PIF_ADDR_ERROR_CAUSE : LOAD_STORE_PIF_ADDR_ERROR_CAUSE, - is_exec ? addr : cs->mem_io_vaddr); + addr); } static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) From patchwork Wed Aug 29 01:16:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 963186 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="WkCPOuQz"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 420SRD31Xsz9rvt for ; Wed, 29 Aug 2018 11:17:44 +1000 (AEST) Received: from localhost ([::1]:40756 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fup78-0000em-1C for incoming@patchwork.ozlabs.org; Tue, 28 Aug 2018 21:17:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51918) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fup6f-0000UM-A9 for qemu-devel@nongnu.org; Tue, 28 Aug 2018 21:17:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fup6e-0003tX-CZ for qemu-devel@nongnu.org; Tue, 28 Aug 2018 21:17:13 -0400 Received: from mail-lj1-x244.google.com ([2a00:1450:4864:20::244]:41831) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fup6e-0003sL-3t for qemu-devel@nongnu.org; Tue, 28 Aug 2018 21:17:12 -0400 Received: by mail-lj1-x244.google.com with SMTP id y17-v6so2965283ljy.8 for ; Tue, 28 Aug 2018 18:17:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DD+dzR6E8p9qXvFxIFL8B9Yypfkn8SKEL+smPuakJSU=; b=WkCPOuQzH5pyFg3XbkHy4xa+ZThr3SDcdWx0eUVCpFcWNqJ0bJQIl38RZYgnFydhBI W7cX5ZzgJPrT4UgHHe4/xg8Dq2verORzfI/p0RksZWKgs/7gh6mxdTha1+jUQY3yXFvD Flp9lEalWumC+VU3etgLo4a6ajru9j5y5nnm/RxpQq39WYWZHcrzzoyoUSyQdXhjjKcz FhLhyhoQyrsLGvI5z22hJtCo3WdxDeiBopIFD1ABjTYXREZvs4inO+Q0ZQhn3IwI8dRl ZvN2JoFrlCiQVLoyztbKM7CURLZPN1sehpEQ38dqAcXEvogNFKRNuFamF1jrJ2r5BTdg G9FQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DD+dzR6E8p9qXvFxIFL8B9Yypfkn8SKEL+smPuakJSU=; b=nz/c/yI6K4E5fB7m1RbStTkSuGSWE8clkRopiqYw+PwppCGZBsnSnhuhWfEUEQXT7X 69IVNfymbpITUdNXhrNmFmVc9gjFeFgUtNSn0y1jEH/W1HwFIpxRVGTUTJTK1gmKc49K FSoniOZRwRTP62h/J/KbFL8E4vBjaylwKgx53PBEhxX3+bjxmRARBvXNUEV4RBLGT0Hj 5Nyhelr38hHcs3X0wPeNbv2GGLXq9dC2ZyZZZOqvaKHuch/NSwLhBwJIYwqkOJvImfFI QVErnPwKarFU4zy6TKdpW0FQH3rhIt9c0Ok1esVvaMWIm0s+hgeEAMlcLkcyB+oxWMU2 5gvA== X-Gm-Message-State: APzg51A8kEVfZtUz3cYH7jj4pNmVFqfksB+PZVFaVvYCln/5HV8nPLte M5LdmUPM+XgVtwOrDwKZej3fFg0I X-Google-Smtp-Source: ANB0Vda0AU+cbpR4Zmfirf0TXw5W1g5WX1pokW11Jmq/1VZtBJfvUCO1jmSVqyf170ZT4Ckc9qfeDw== X-Received: by 2002:a2e:9d45:: with SMTP id y5-v6mr1118968ljj.136.1535505430709; Tue, 28 Aug 2018 18:17:10 -0700 (PDT) Received: from octofox.hsd1.ca.comcast.net. (jcmvbkbc-1-pt.tunnel.tserv24.sto1.ipv6.he.net. [2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id l14-v6sm460143ljh.91.2018.08.28.18.17.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 Aug 2018 18:17:10 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Tue, 28 Aug 2018 18:16:52 -0700 Message-Id: <20180829011652.4466-3-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180829011652.4466-1-jcmvbkbc@gmail.com> References: <20180829011652.4466-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::244 Subject: [Qemu-devel] [PATCH v2 2/2] tests/tcg/xtensa: add test for failed memory transactions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Max Filippov Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Failed memory transactions should raise exceptions 14 (for fetch) or 15 (for load/store) with XEA2. Memory accesses that result in TLB miss followed by an attempt to load PTE from physical memory which fails should raise InstTLBMiss or LoadStoreTLBMiss with XEA2. Signed-off-by: Max Filippov --- Changes v1->v2: - add tests that attempt TLB autorefill from the physically unmapped addresses. tests/tcg/xtensa/Makefile | 1 + tests/tcg/xtensa/test_phys_mem.S | 124 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 125 insertions(+) create mode 100644 tests/tcg/xtensa/test_phys_mem.S diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa/Makefile index 091518c05583..2f5691f75b09 100644 --- a/tests/tcg/xtensa/Makefile +++ b/tests/tcg/xtensa/Makefile @@ -44,6 +44,7 @@ TESTCASES += test_mmu.tst TESTCASES += test_mul16.tst TESTCASES += test_mul32.tst TESTCASES += test_nsa.tst +TESTCASES += test_phys_mem.tst ifdef XT TESTCASES += test_pipeline.tst endif diff --git a/tests/tcg/xtensa/test_phys_mem.S b/tests/tcg/xtensa/test_phys_mem.S new file mode 100644 index 000000000000..aae0a793a718 --- /dev/null +++ b/tests/tcg/xtensa/test_phys_mem.S @@ -0,0 +1,124 @@ +#include "macros.inc" + +test_suite phys_mem + +.purgem test_init + +.macro test_init + movi a2, 0xc0000003 /* PPN */ + movi a3, 0xc0000004 /* VPN */ + wdtlb a2, a3 + witlb a2, a3 + movi a2, 0xc0000000 + wsr a2, ptevaddr +.endm + +test inst_fetch_get_pte_no_phys + set_vector kernel, 2f + + movi a2, 0x20000000 + jx a2 +2: + movi a2, 0x20000000 + rsr a3, excvaddr + assert eq, a2, a3 + rsr a3, epc1 + assert eq, a2, a3 + rsr a3, exccause + movi a2, 16 + assert eq, a2, a3 +test_end + +test read_get_pte_no_phys + set_vector kernel, 2f + + movi a2, 0x20000000 +1: + l32i a3, a2, 0 + test_fail +2: + movi a2, 0x20000000 + rsr a3, excvaddr + assert eq, a2, a3 + movi a2, 1b + rsr a3, epc1 + assert eq, a2, a3 + rsr a3, exccause + movi a2, 24 + assert eq, a2, a3 +test_end + +test write_get_pte_no_phys + set_vector kernel, 2f + + movi a2, 0x20000000 +1: + s32i a3, a2, 0 + test_fail +2: + movi a2, 0x20000000 + rsr a3, excvaddr + assert eq, a2, a3 + movi a2, 1b + rsr a3, epc1 + assert eq, a2, a3 + rsr a3, exccause + movi a2, 24 + assert eq, a2, a3 +test_end + +test inst_fetch_no_phys + set_vector kernel, 2f + + movi a2, 0xc0000000 + jx a2 +2: + movi a2, 0xc0000000 + rsr a3, excvaddr + assert eq, a2, a3 + rsr a3, epc1 + assert eq, a2, a3 + rsr a3, exccause + movi a2, 14 + assert eq, a2, a3 +test_end + +test read_no_phys + set_vector kernel, 2f + + movi a2, 0xc0000000 +1: + l32i a3, a2, 0 + test_fail +2: + movi a2, 0xc0000000 + rsr a3, excvaddr + assert eq, a2, a3 + movi a2, 1b + rsr a3, epc1 + assert eq, a2, a3 + rsr a3, exccause + movi a2, 15 + assert eq, a2, a3 +test_end + +test write_no_phys + set_vector kernel, 2f + + movi a2, 0xc0000000 +1: + s32i a3, a2, 0 + test_fail +2: + movi a2, 0xc0000000 + rsr a3, excvaddr + assert eq, a2, a3 + movi a2, 1b + rsr a3, epc1 + assert eq, a2, a3 + rsr a3, exccause + movi a2, 15 + assert eq, a2, a3 +test_end + +test_suite_end