From patchwork Tue Jul 10 08:57:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Jingqi" X-Patchwork-Id: 941867 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Px1x5KFkz9s19 for ; Tue, 10 Jul 2018 18:58:29 +1000 (AEST) Received: from localhost ([::1]:46562 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fcoTb-00032x-BU for incoming@patchwork.ozlabs.org; Tue, 10 Jul 2018 04:58:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50372) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fcoTB-00032h-VR for qemu-devel@nongnu.org; Tue, 10 Jul 2018 04:58:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fcoT9-0003uD-Ds for qemu-devel@nongnu.org; Tue, 10 Jul 2018 04:58:02 -0400 Received: from mga09.intel.com ([134.134.136.24]:44704) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fcoT9-0003tC-5d for qemu-devel@nongnu.org; Tue, 10 Jul 2018 04:57:59 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jul 2018 01:57:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,333,1526367600"; d="scan'208";a="71049807" Received: from dst.sh.intel.com ([10.239.48.156]) by fmsmga001.fm.intel.com with ESMTP; 10 Jul 2018 01:57:57 -0700 From: Jingqi Liu To: pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com Date: Tue, 10 Jul 2018 16:57:32 +0800 Message-Id: <1531213054-63327-2-git-send-email-jingqi.liu@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1531213054-63327-1-git-send-email-jingqi.liu@intel.com> References: <1531213054-63327-1-git-send-email-jingqi.liu@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.24 Subject: [Qemu-devel] [PATCH 1/3] x86/cpu: Enable UMONITOR/UMWAIT/TPAUSE cpu features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jingqi Liu , wei.w.wang@intel.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" UMONITOR, UMWAIT, and TPAUSE are a set of user wait instructions. UMONITOR arms address monitoring hardware using an address. A store to an address within the specified address range triggers the monitoring hardware to wake up the processor waiting in umwait. UMWAIT instructs the processor to enter an implementation-dependent optimized state while monitoring a range of addresses. The optimized state may be either a light-weight power/performance optimized state or an improved power/performance optimized state. TPAUSE instructs the processor to enter an implementation-dependent optimized state c0.1 or c0.2 state and wake up when time-stamp counter reaches specified timeout. The bit definition: CPUID.(EAX=7,ECX=0):ECX[bit 05] WAITPKG The release document ref below link: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Signed-off-by: Jingqi Liu --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e0e2f2e..e0d151f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -978,7 +978,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { [FEAT_7_0_ECX] = { .feat_names = { NULL, "avx512vbmi", "umip", "pku", - NULL /* ospke */, NULL, "avx512vbmi2", NULL, + NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, "gfni", "vaes", "vpclmulqdq", "avx512vnni", "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, "la57", NULL, NULL, NULL, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 2c5a0d9..f651105 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -674,6 +674,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_ECX_UMIP (1U << 2) #define CPUID_7_0_ECX_PKU (1U << 3) #define CPUID_7_0_ECX_OSPKE (1U << 4) +#define CPUID_7_0_ECX_WAITPKG (1U << 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */ #define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */ #define CPUID_7_0_ECX_GFNI (1U << 8) #define CPUID_7_0_ECX_VAES (1U << 9) From patchwork Tue Jul 10 08:57:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Jingqi" X-Patchwork-Id: 941870 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Px2R4b3Jz9s19 for ; Tue, 10 Jul 2018 18:58:55 +1000 (AEST) Received: from localhost ([::1]:46566 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fcoU1-0003EH-5u for incoming@patchwork.ozlabs.org; Tue, 10 Jul 2018 04:58:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50480) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fcoTR-0003Cc-3n for qemu-devel@nongnu.org; Tue, 10 Jul 2018 04:58:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fcoTN-0003yn-W9 for qemu-devel@nongnu.org; Tue, 10 Jul 2018 04:58:17 -0400 Received: from mga03.intel.com ([134.134.136.65]:51105) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fcoTN-0003yN-Lp for qemu-devel@nongnu.org; Tue, 10 Jul 2018 04:58:13 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jul 2018 01:58:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,333,1526367600"; d="scan'208";a="71049820" Received: from dst.sh.intel.com ([10.239.48.156]) by fmsmga001.fm.intel.com with ESMTP; 10 Jul 2018 01:58:00 -0700 From: Jingqi Liu To: pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com Date: Tue, 10 Jul 2018 16:57:33 +0800 Message-Id: <1531213054-63327-3-git-send-email-jingqi.liu@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1531213054-63327-1-git-send-email-jingqi.liu@intel.com> References: <1531213054-63327-1-git-send-email-jingqi.liu@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.65 Subject: [Qemu-devel] [PATCH 2/3] x86/cpu: Enable MOVDIRI cpu feature X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jingqi Liu , wei.w.wang@intel.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" MOVDIRI moves doubleword or quadword from register to memory through direct store which is implemented by using write combining (WC) for writing data directly into memory without caching the data. The bit definition: CPUID.(EAX=7,ECX=0):ECX[bit 27] MOVDIRI The release document ref below link: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Signed-off-by: Jingqi Liu --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e0d151f..775cfcb 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -983,7 +983,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, "la57", NULL, NULL, NULL, NULL, NULL, "rdpid", NULL, - NULL, "cldemote", NULL, NULL, + NULL, "cldemote", NULL, "movdiri", NULL, NULL, NULL, NULL, }, .cpuid_eax = 7, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index f651105..d94bf2d 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -685,6 +685,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_ECX_LA57 (1U << 16) #define CPUID_7_0_ECX_RDPID (1U << 22) #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) /* CLDEMOTE Instruction */ +#define CPUID_7_0_ECX_MOVDIRI (1U << 27) /* MOVDIRI Instruction */ #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ From patchwork Tue Jul 10 08:57:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Jingqi" X-Patchwork-Id: 941869 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Px2R2yv3z9s0W for ; Tue, 10 Jul 2018 18:58:55 +1000 (AEST) Received: from localhost ([::1]:46565 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fcoU0-0003Du-Uq for incoming@patchwork.ozlabs.org; Tue, 10 Jul 2018 04:58:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50483) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fcoTR-0003Ce-4i for qemu-devel@nongnu.org; Tue, 10 Jul 2018 04:58:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fcoTO-0003z8-GB for qemu-devel@nongnu.org; Tue, 10 Jul 2018 04:58:17 -0400 Received: from mga03.intel.com ([134.134.136.65]:51105) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fcoTO-0003yN-5z for qemu-devel@nongnu.org; Tue, 10 Jul 2018 04:58:14 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jul 2018 01:58:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,333,1526367600"; d="scan'208";a="71049830" Received: from dst.sh.intel.com ([10.239.48.156]) by fmsmga001.fm.intel.com with ESMTP; 10 Jul 2018 01:58:01 -0700 From: Jingqi Liu To: pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com Date: Tue, 10 Jul 2018 16:57:34 +0800 Message-Id: <1531213054-63327-4-git-send-email-jingqi.liu@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1531213054-63327-1-git-send-email-jingqi.liu@intel.com> References: <1531213054-63327-1-git-send-email-jingqi.liu@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.65 Subject: [Qemu-devel] [PATCH 3/3] x86/cpu: Enable MOVDIR64B cpu feature X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jingqi Liu , wei.w.wang@intel.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" MOVDIR64B moves 64-bytes as direct-store with 64-bytes write atomicity. Direct store is implemented by using write combining (WC) for writing data directly into memory without caching the data. The bit definition: CPUID.(EAX=7,ECX=0):ECX[bit 28] MOVDIR64B The release document ref below link: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Signed-off-by: Jingqi Liu --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 775cfcb..fc0b678 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -984,7 +984,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "la57", NULL, NULL, NULL, NULL, NULL, "rdpid", NULL, NULL, "cldemote", NULL, "movdiri", - NULL, NULL, NULL, NULL, + "movdir64b", NULL, NULL, NULL, }, .cpuid_eax = 7, .cpuid_needs_ecx = true, .cpuid_ecx = 0, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d94bf2d..8014c1c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -686,6 +686,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_ECX_RDPID (1U << 22) #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) /* CLDEMOTE Instruction */ #define CPUID_7_0_ECX_MOVDIRI (1U << 27) /* MOVDIRI Instruction */ +#define CPUID_7_0_ECX_MOVDIR64B (1U << 28) /* MOVDIR64B Instruction */ #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */