From patchwork Mon Jun 25 03:39:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 934066 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.intel.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Dcmg6trgz9ryk for ; Mon, 25 Jun 2018 15:14:43 +1000 (AEST) Received: from localhost ([::1]:44265 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXJpm-00066e-Gb for incoming@patchwork.ozlabs.org; Mon, 25 Jun 2018 01:14:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36624) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXIMJ-0001mF-Dp for qemu-devel@nongnu.org; Sun, 24 Jun 2018 23:40:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXIME-0007sQ-Ik for qemu-devel@nongnu.org; Sun, 24 Jun 2018 23:40:07 -0400 Received: from mga17.intel.com ([192.55.52.151]:25151) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXIME-0007qo-9x for qemu-devel@nongnu.org; Sun, 24 Jun 2018 23:40:02 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Jun 2018 20:39:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,268,1526367600"; d="scan'208";a="235277831" Received: from sqa-gate.sh.intel.com (HELO robert-ivt.tsp.org) ([10.239.48.212]) by orsmga005.jf.intel.com with ESMTP; 24 Jun 2018 20:39:47 -0700 From: Robert Hoo To: qemu-devel@nongnu.org, pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com Date: Mon, 25 Jun 2018 11:39:17 +0800 Message-Id: <1529897961-134132-2-git-send-email-robert.hu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1529897961-134132-1-git-send-email-robert.hu@linux.intel.com> References: <1529897961-134132-1-git-send-email-robert.hu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.151 X-Mailman-Approved-At: Mon, 25 Jun 2018 01:13:50 -0400 Subject: [Qemu-devel] [PATCH 1/5] i386: Add support for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robert.hu@intel.com, Robert Hoo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" IA32_PRED_CMD MSR gives software a way to issue commands that affect the state of indirect branch predictors. Enumerated by CPUID.(EAX=7H,ECX=0):EDX[26]. IA32_ARCH_CAPABILITIES MSR enumerates architectural features of RDCL_NO and IBRS_ALL. Enumerated by CPUID.(EAX=07H, ECX=0):EDX[29]. https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf Signed-off-by: Robert Hoo --- target/i386/cpu.h | 4 ++++ target/i386/kvm.c | 27 ++++++++++++++++++++++++++- target/i386/machine.c | 40 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 70 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 89c82be..734a73e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -352,6 +352,8 @@ typedef enum X86Seg { #define MSR_TSC_ADJUST 0x0000003b #define MSR_IA32_SPEC_CTRL 0x48 #define MSR_VIRT_SSBD 0xc001011f +#define MSR_IA32_PRED_CMD 0x49 +#define MSR_IA32_ARCH_CAPABILITIES 0x10a #define MSR_IA32_TSCDEADLINE 0x6e0 #define FEATURE_CONTROL_LOCKED (1<<0) @@ -1210,6 +1212,8 @@ typedef struct CPUX86State { uint64_t spec_ctrl; uint64_t virt_ssbd; + uint64_t pred_cmd; + uint64_t arch_capabilities; /* End of state preserved by INIT (dummy marker). */ struct {} end_init_save; diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 445e0e0..5232446 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -93,6 +93,8 @@ static bool has_msr_hv_reenlightenment; static bool has_msr_xss; static bool has_msr_spec_ctrl; static bool has_msr_virt_ssbd; +static bool has_msr_pred_cmd; +static bool has_msr_arch_capabilities; static bool has_msr_smi_count; static uint32_t has_architectural_pmu_version; @@ -1258,6 +1260,11 @@ static int kvm_get_supported_msrs(KVMState *s) break; case MSR_VIRT_SSBD: has_msr_virt_ssbd = true; + case MSR_IA32_PRED_CMD: + has_msr_pred_cmd = true; + break; + case MSR_IA32_ARCH_CAPABILITIES: + has_msr_arch_capabilities = true; break; } } @@ -1750,7 +1757,13 @@ static int kvm_put_msrs(X86CPU *cpu, int level) if (has_msr_virt_ssbd) { kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd); } - + if (has_msr_pred_cmd) { + kvm_msr_entry_add(cpu, MSR_IA32_PRED_CMD, env->pred_cmd); + } + if (has_msr_arch_capabilities) { + kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES, + env->arch_capabilities); + } #ifdef TARGET_X86_64 if (lm_capable_kernel) { kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar); @@ -2133,6 +2146,13 @@ static int kvm_get_msrs(X86CPU *cpu) if (has_msr_virt_ssbd) { kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0); } + if (has_msr_pred_cmd) { + kvm_msr_entry_add(cpu, MSR_IA32_PRED_CMD, 0); + } + if (has_msr_arch_capabilities) { + kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES, 0); + } + if (!env->tsc_valid) { kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0); env->tsc_valid = !runstate_is_running(); @@ -2514,6 +2534,11 @@ static int kvm_get_msrs(X86CPU *cpu) break; case MSR_VIRT_SSBD: env->virt_ssbd = msrs[i].data; + case MSR_IA32_PRED_CMD: + env->pred_cmd = msrs[i].data; + break; + case MSR_IA32_ARCH_CAPABILITIES: + env->arch_capabilities = msrs[i].data; break; case MSR_IA32_RTIT_CTL: env->msr_rtit_ctrl = msrs[i].data; diff --git a/target/i386/machine.c b/target/i386/machine.c index 4d98d36..089aba0 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -879,6 +879,44 @@ static const VMStateDescription vmstate_spec_ctrl = { } }; +static bool pred_cmd_needed(void *opaque) +{ + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; + + return env->pred_cmd != 0; +} + +static const VMStateDescription vmstate_pred_cmd = { + .name = "cpu/pred_cmd", + .version_id = 1, + .minimum_version_id = 1, + .needed = pred_cmd_needed, + .fields = (VMStateField[]){ + VMSTATE_UINT64(env.arch_capabilities, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool arch_capabilities_needed(void *opaque) +{ + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; + + return env->arch_capabilities != 0; +} + +static const VMStateDescription vmstate_arch_capabilities = { + .name = "cpu/arch_capabilities", + .version_id = 1, + .minimum_version_id = 1, + .needed = arch_capabilities_needed, + .fields = (VMStateField[]){ + VMSTATE_UINT64(env.arch_capabilities, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + static bool intel_pt_enable_needed(void *opaque) { X86CPU *cpu = opaque; @@ -1056,6 +1094,8 @@ VMStateDescription vmstate_x86_cpu = { &vmstate_pkru, #endif &vmstate_spec_ctrl, + &vmstate_pred_cmd, + &vmstate_arch_capabilities, &vmstate_mcg_ext_ctl, &vmstate_msr_intel_pt, &vmstate_msr_virt_ssbd, From patchwork Mon Jun 25 03:39:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 934065 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.intel.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41DcmT0JrBz9s2t for ; Mon, 25 Jun 2018 15:14:31 +1000 (AEST) Received: from localhost ([::1]:44264 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXJpc-0005ya-6m for incoming@patchwork.ozlabs.org; Mon, 25 Jun 2018 01:14:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36627) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXIMJ-0001mH-Hd for qemu-devel@nongnu.org; Sun, 24 Jun 2018 23:40:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXIMF-0007sl-KR for qemu-devel@nongnu.org; Sun, 24 Jun 2018 23:40:07 -0400 Received: from mga17.intel.com ([192.55.52.151]:25151) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXIMF-0007qo-5u for qemu-devel@nongnu.org; Sun, 24 Jun 2018 23:40:03 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Jun 2018 20:39:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,268,1526367600"; d="scan'208";a="235277836" Received: from sqa-gate.sh.intel.com (HELO robert-ivt.tsp.org) ([10.239.48.212]) by orsmga005.jf.intel.com with ESMTP; 24 Jun 2018 20:39:49 -0700 From: Robert Hoo To: qemu-devel@nongnu.org, pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com Date: Mon, 25 Jun 2018 11:39:18 +0800 Message-Id: <1529897961-134132-3-git-send-email-robert.hu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1529897961-134132-1-git-send-email-robert.hu@linux.intel.com> References: <1529897961-134132-1-git-send-email-robert.hu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.151 X-Mailman-Approved-At: Mon, 25 Jun 2018 01:13:43 -0400 Subject: [Qemu-devel] [PATCH 2/5] i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robert.hu@intel.com, Robert Hoo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as SPEC_CTRL. Signed-off-by: Robert Hoo --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1e69e68..3134af4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -896,7 +896,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "spec-ctrl", NULL, - NULL, NULL, NULL, "ssbd", + NULL, "arch-capabilities", NULL, "ssbd", }, .cpuid_eax = 7, .cpuid_needs_ecx = true, .cpuid_ecx = 0, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 734a73e..1ef2040 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -688,6 +688,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ +#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities of RDCL_NO and IBRS_ALL*/ #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */ From patchwork Mon Jun 25 03:39:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 934068 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.intel.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Dcpr6YMTz9ryk for ; Mon, 25 Jun 2018 15:16:36 +1000 (AEST) Received: from localhost ([::1]:44278 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXJre-0007fU-D0 for incoming@patchwork.ozlabs.org; Mon, 25 Jun 2018 01:16:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36628) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXIMJ-0001mI-Hp for qemu-devel@nongnu.org; Sun, 24 Jun 2018 23:40:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXIMG-0007t8-5k for qemu-devel@nongnu.org; Sun, 24 Jun 2018 23:40:07 -0400 Received: from mga17.intel.com ([192.55.52.151]:25155) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXIMF-0007sW-TK for qemu-devel@nongnu.org; Sun, 24 Jun 2018 23:40:04 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Jun 2018 20:39:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,268,1526367600"; d="scan'208";a="235277839" Received: from sqa-gate.sh.intel.com (HELO robert-ivt.tsp.org) ([10.239.48.212]) by orsmga005.jf.intel.com with ESMTP; 24 Jun 2018 20:39:50 -0700 From: Robert Hoo To: qemu-devel@nongnu.org, pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com Date: Mon, 25 Jun 2018 11:39:19 +0800 Message-Id: <1529897961-134132-4-git-send-email-robert.hu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1529897961-134132-1-git-send-email-robert.hu@linux.intel.com> References: <1529897961-134132-1-git-send-email-robert.hu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.151 X-Mailman-Approved-At: Mon, 25 Jun 2018 01:13:49 -0400 Subject: [Qemu-devel] [PATCH 3/5] i386: Add CPUID bit for PCONFIG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robert.hu@intel.com, Robert Hoo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" PCONFIG: Platform configuration, enumerated by CPUID.(EAX=07H, ECX=0): EDX[bit18]. Reference: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf Signed-off-by: Robert Hoo --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3134af4..9e038c3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -893,7 +893,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + NULL, NULL, "pconfig", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "spec-ctrl", NULL, NULL, "arch-capabilities", NULL, "ssbd", diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 1ef2040..61d23e5 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -687,6 +687,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ +#define CPUID_7_0_EDX_PCONFIG (1U << 18) /* Platform Configuration */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities of RDCL_NO and IBRS_ALL*/ #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ From patchwork Mon Jun 25 03:39:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 934069 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.intel.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Dcrq5zPPz9ryk for ; Mon, 25 Jun 2018 15:18:19 +1000 (AEST) Received: from localhost ([::1]:44291 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXJtJ-0000X5-EH for incoming@patchwork.ozlabs.org; Mon, 25 Jun 2018 01:18:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36633) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXIMJ-0001mK-J7 for qemu-devel@nongnu.org; Sun, 24 Jun 2018 23:40:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXIMF-0007sr-NR for qemu-devel@nongnu.org; Sun, 24 Jun 2018 23:40:07 -0400 Received: from mga17.intel.com ([192.55.52.151]:25155) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXIMF-0007sW-EU for qemu-devel@nongnu.org; Sun, 24 Jun 2018 23:40:03 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Jun 2018 20:39:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,268,1526367600"; d="scan'208";a="235277840" Received: from sqa-gate.sh.intel.com (HELO robert-ivt.tsp.org) ([10.239.48.212]) by orsmga005.jf.intel.com with ESMTP; 24 Jun 2018 20:39:51 -0700 From: Robert Hoo To: qemu-devel@nongnu.org, pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com Date: Mon, 25 Jun 2018 11:39:20 +0800 Message-Id: <1529897961-134132-5-git-send-email-robert.hu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1529897961-134132-1-git-send-email-robert.hu@linux.intel.com> References: <1529897961-134132-1-git-send-email-robert.hu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.151 X-Mailman-Approved-At: Mon, 25 Jun 2018 01:13:44 -0400 Subject: [Qemu-devel] [PATCH 4/5] i386: Add CPUID bit for WBNOINVD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robert.hu@intel.com, Robert Hoo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" WBNOINVD: Write back and do not invalidate cache, enumerated by CPUID.(EAX=80000008H, ECX=0):EBX[bit 9]. Reference: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf Signed-off-by: Robert Hoo --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 9e038c3..821b7bd 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -923,7 +923,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .feat_names = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + NULL, "wbnoinvd", NULL, NULL, "ibpb", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 61d23e5..c67216d 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -692,6 +692,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities of RDCL_NO and IBRS_ALL*/ #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ +#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and do not invalidate cache */ #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */ #define CPUID_XSAVE_XSAVEOPT (1U << 0) From patchwork Mon Jun 25 03:39:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 934070 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.intel.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41DctZ5yk9z9ryk for ; Mon, 25 Jun 2018 15:19:49 +1000 (AEST) Received: from localhost ([::1]:44295 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXJuk-0001D1-4x for incoming@patchwork.ozlabs.org; Mon, 25 Jun 2018 01:19:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36629) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXIMJ-0001mJ-IP for qemu-devel@nongnu.org; Sun, 24 Jun 2018 23:40:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXIMG-0007t1-2E for qemu-devel@nongnu.org; Sun, 24 Jun 2018 23:40:07 -0400 Received: from mga17.intel.com ([192.55.52.151]:25151) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXIMF-0007qo-Pv for qemu-devel@nongnu.org; Sun, 24 Jun 2018 23:40:03 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Jun 2018 20:39:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,268,1526367600"; d="scan'208";a="235277842" Received: from sqa-gate.sh.intel.com (HELO robert-ivt.tsp.org) ([10.239.48.212]) by orsmga005.jf.intel.com with ESMTP; 24 Jun 2018 20:39:52 -0700 From: Robert Hoo To: qemu-devel@nongnu.org, pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com Date: Mon, 25 Jun 2018 11:39:21 +0800 Message-Id: <1529897961-134132-6-git-send-email-robert.hu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1529897961-134132-1-git-send-email-robert.hu@linux.intel.com> References: <1529897961-134132-1-git-send-email-robert.hu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.151 X-Mailman-Approved-At: Mon, 25 Jun 2018 01:13:45 -0400 Subject: [Qemu-devel] [PATCH 5/5] i386: Add new CPU model Icelake-{Server, Client} X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robert.hu@intel.com, Robert Hoo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" New CPU models mostly inherit features from ancestor Skylake, while addin new features: UMIP, New Instructions ( PCONIFIG (server only), WBNOINVD, AVX512_VBMI2, GFNI, AVX512_VNNI, VPCLMULQDQ, VAES, AVX512_BITALG), Intel PT and 5-level paging (Server only). As well as IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs, SSBD support for speculative execution side channel mitigations. Note: For 5-level paging, Guest physical address width can be configured, with parameter "phys-bits". Unless explicitly specified, we still use its default value, even for Icelake-Server cpu model. Signed-off-by: Robert Hoo --- target/i386/cpu.c | 116 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 821b7bd..2613e1a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2276,6 +2276,122 @@ static X86CPUDefinition builtin_x86_defs[] = { .model_id = "Intel Xeon Processor (Skylake, IBRS)", }, { + .name = "Icelake-Client", + .level = 0xd, + .vendor = CPUID_VENDOR_INTEL, + .family = 6, + .model = 126, + .stepping = 0, + .features[FEAT_1_EDX] = + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .features[FEAT_1_ECX] = + CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | + CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | + CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | + CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, + .features[FEAT_8000_0001_EDX] = + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | + CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0001_ECX] = + CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, + .features[FEAT_8000_0008_EBX] = + CPUID_8000_0008_EBX_WBNOINVD, + .features[FEAT_7_0_EBX] = + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | + CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_INTEL_PT, + .features[FEAT_7_0_ECX] = + CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | + CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI | + CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | + CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | + CPUID_7_0_ECX_AVX512_VPOPCNTDQ, + .features[FEAT_7_0_EDX] = + CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | + CPUID_7_0_EDX_SPEC_CTRL_SSBD, + /* Missing: XSAVES (not supported by some Linux versions, + * including v4.1 to v4.12). + * KVM doesn't yet expose any XSAVES state save component, + * and the only one defined in Skylake (processor tracing) + * probably will block migration anyway. + */ + .features[FEAT_XSAVE] = + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | + CPUID_XSAVE_XGETBV1, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, + .xlevel = 0x80000008, + .model_id = "Intel Core Processor (Icelake)", + }, + { + .name = "Icelake-Server", + .level = 0xd, + .vendor = CPUID_VENDOR_INTEL, + .family = 6, + .model = 134, + .stepping = 0, + .features[FEAT_1_EDX] = + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .features[FEAT_1_ECX] = + CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | + CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | + CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | + CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, + .features[FEAT_8000_0001_EDX] = + CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | + CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0001_ECX] = + CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, + .features[FEAT_8000_0008_EBX] = + CPUID_8000_0008_EBX_WBNOINVD, + .features[FEAT_7_0_EBX] = + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | + CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB | + CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | + CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | + CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT | + CPUID_7_0_EBX_INTEL_PT, + .features[FEAT_7_0_ECX] = + CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | + CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI | + CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | + CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | + CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, + .features[FEAT_7_0_EDX] = + CPUID_7_0_EDX_PCONFIG | CPUID_7_0_EDX_SPEC_CTRL | + CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, + /* Missing: XSAVES (not supported by some Linux versions, + * including v4.1 to v4.12). + * KVM doesn't yet expose any XSAVES state save component, + * and the only one defined in Skylake (processor tracing) + * probably will block migration anyway. + */ + .features[FEAT_XSAVE] = + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | + CPUID_XSAVE_XGETBV1, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, + .xlevel = 0x80000008, + .model_id = "Intel Xeon Processor (Icelake)", + }, + { .name = "KnightsMill", .level = 0xd, .vendor = CPUID_VENDOR_INTEL,