From patchwork Sat Jun 23 23:52:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timothy Pearson X-Patchwork-Id: 933819 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Ctw20ffpz9s2R for ; Sun, 24 Jun 2018 10:48:34 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=raptorengineering.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=raptorengineering.com header.i=@raptorengineering.com header.b="Kcu6bNqU"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 41Ctw1674vzF0wq for ; Sun, 24 Jun 2018 10:48:33 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=raptorengineering.com Authentication-Results: lists.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=raptorengineering.com header.i=@raptorengineering.com header.b="Kcu6bNqU"; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=raptorengineering.com (client-ip=192.119.205.245; helo=mail.rptsys.com; envelope-from=tpearson@raptorengineering.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=raptorengineering.com Authentication-Results: lists.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=raptorengineering.com header.i=@raptorengineering.com header.b="Kcu6bNqU"; dkim-atps=neutral Received: from mail.rptsys.com (mail.rptsys.com [192.119.205.245]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 41Csp94WkLzF14f for ; Sun, 24 Jun 2018 09:58:25 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by mail.rptsys.com (Postfix) with ESMTP id 15B986428A2; Sat, 23 Jun 2018 18:52:33 -0500 (CDT) Received: from mail.rptsys.com ([127.0.0.1]) by localhost (vali.starlink.edu [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id AQ1QZ927D5uc; Sat, 23 Jun 2018 18:52:31 -0500 (CDT) Received: from localhost (localhost [127.0.0.1]) by mail.rptsys.com (Postfix) with ESMTP id 670A66428A9; Sat, 23 Jun 2018 18:52:31 -0500 (CDT) DKIM-Filter: OpenDKIM Filter v2.9.2 mail.rptsys.com 670A66428A9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=raptorengineering.com; s=B8E824E6-0BE2-11E6-931D-288C65937AAD; t=1529797951; bh=4D5wi8kxunDLSxbQJ4fR37/ZSWDQEQkkQhPeivK+BRo=; h=Date:From:To:Message-ID:Subject:MIME-Version:Content-Type: Content-Transfer-Encoding; b=Kcu6bNqUrW3WFMhUqivJY98th43Rs/P05v2fegA7yPyKdCHmUWMEWOK0r0bYTUAbH KoCh/vs6Xf1kLRR4bevzOpVy+KhbM30jJaimsX3khn+YPByRsiqZ4aa0GLLkdMYzMA fCTxU+ZrVj0eCVtz0VRnjuA/c3O1Q/2gxPjWy6fY= X-Virus-Scanned: amavisd-new at rptsys.com Received: from mail.rptsys.com ([127.0.0.1]) by localhost (vali.starlink.edu [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id SAWbxcMH1uJB; Sat, 23 Jun 2018 18:52:31 -0500 (CDT) Received: from vali.starlink.edu (netrouter.starlink.edu [192.168.3.1]) by mail.rptsys.com (Postfix) with ESMTP id 1FF976428A2; Sat, 23 Jun 2018 18:52:31 -0500 (CDT) Date: Sat, 23 Jun 2018 18:52:30 -0500 (CDT) From: Timothy Pearson To: linuxppc-dev@lists.ozlabs.org Message-ID: <77952537.2569246.1529797950974.JavaMail.zimbra@raptorengineeringinc.com> Subject: [PATCH 1/7] powerpc/powernv/pci: Track largest available TCE order MIME-Version: 1.0 X-Mailer: Zimbra 8.5.0_GA_3042 (ZimbraWebClient - FF3.6 (Linux)/8.5.0_GA_3042) Thread-Topic: powerpc/powernv/pci: Track largest available TCE order Thread-Index: w/cN0CTC+T9U81zi83C5HZaodRl3JA== X-Mailman-Approved-At: Sun, 24 Jun 2018 10:42:17 +1000 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Mackerras Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" per PHB Knowing the largest possible TCE size of a PHB is useful, so get it out of the device tree. This relies on the property being added in OPAL. It is assumed that any PHB4 or later machine would be running firmware that implemented this property, and otherwise assumed to be PHB3, which has a maximum TCE order of 28 bits or 256MB TCEs. This is used later in the series. Signed-off-by: Russell Currey --- arch/powerpc/platforms/powernv/pci-ioda.c | 16 ++++++++++++++++ arch/powerpc/platforms/powernv/pci.h | 3 +++ 2 files changed, 19 insertions(+) diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index 5bd0eb6681bc..bcb3bfce072a 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -3873,11 +3873,13 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np, struct resource r; const __be64 *prop64; const __be32 *prop32; + struct property *prop; int len; unsigned int segno; u64 phb_id; void *aux; long rc; + u32 val; if (!of_device_is_available(np)) return; @@ -4016,6 +4018,20 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np, } phb->ioda.pe_array = aux + pemap_off; + phb->ioda.max_tce_order = 0; + // Get TCE order from the DT. If it's not present, assume P8 + if (!of_get_property(np, "ibm,supported-tce-sizes", NULL)) { + phb->ioda.max_tce_order = 28; // assume P8 256mb TCEs + } else { + of_property_for_each_u32(np, "ibm,supported-tce-sizes", prop, + prop32, val) { + if (val > phb->ioda.max_tce_order) + phb->ioda.max_tce_order = val; + } + pr_debug("PHB%llx Found max TCE order of %d bits\n", + phb->opal_id, phb->ioda.max_tce_order); + } + /* * Choose PE number for root bus, which shouldn't have * M64 resources consumed by its child devices. To pick diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h index eada4b6068cb..c9952def5e93 100644 --- a/arch/powerpc/platforms/powernv/pci.h +++ b/arch/powerpc/platforms/powernv/pci.h @@ -173,6 +173,9 @@ struct pnv_phb { struct list_head pe_list; struct mutex pe_list_mutex; + /* Largest supported TCE order bits */ + uint8_t max_tce_order; + /* Reverse map of PEs, indexed by {bus, devfn} */ unsigned int pe_rmap[0x10000]; } ioda; From patchwork Sat Jun 23 23:53:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timothy Pearson X-Patchwork-Id: 933818 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41CtsP0S99z9s2R for ; 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Sat, 23 Jun 2018 18:53:03 -0500 (CDT) DKIM-Filter: OpenDKIM Filter v2.9.2 mail.rptsys.com 2E565641A29 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=raptorengineering.com; s=B8E824E6-0BE2-11E6-931D-288C65937AAD; t=1529797983; bh=qRUdXU6SsH35fq5zypudgEZYk6tERI03pFsev7zjM64=; h=Date:From:To:Message-ID:Subject:MIME-Version:Content-Type: Content-Transfer-Encoding; b=lA3D9474LRMTHMfqpI7TOsclYLwn8sUEnylZRV3MFekaIRUkBN/Lw+D8Qeu9EsYHu FNqbSjQHtUuPpyrwEWyRFaZ8iT+LSkeKjTHgqEcRuO3wWwFJSWPZtuF3qUqYq0UTGQ lk6t0pPJYN1o5PTihkaZ3+wPZpve4X3ZJDD7RoL0= X-Virus-Scanned: amavisd-new at rptsys.com Received: from mail.rptsys.com ([127.0.0.1]) by localhost (vali.starlink.edu [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id UGkN3NBG2hCy; Sat, 23 Jun 2018 18:53:02 -0500 (CDT) Received: from vali.starlink.edu (vali.starlink.edu [192.168.3.21]) by mail.rptsys.com (Postfix) with ESMTP id 828A16420E4; Sat, 23 Jun 2018 18:53:02 -0500 (CDT) Date: Sat, 23 Jun 2018 18:53:02 -0500 (CDT) From: Timothy Pearson To: linuxppc-dev@lists.ozlabs.org Message-ID: <813333447.2569248.1529797982244.JavaMail.zimbra@raptorengineeringinc.com> Subject: [PATCH 2/7] powerpc/powernv: DMA operations for discontiguous MIME-Version: 1.0 X-Mailer: Zimbra 8.5.0_GA_3042 (ZimbraWebClient - FF3.6 (Linux)/8.5.0_GA_3042) Thread-Topic: powerpc/powernv: DMA operations for discontiguous Thread-Index: V923L26qrpxS9NLvkWrGpBvktf//Bg== X-Mailman-Approved-At: Sun, 24 Jun 2018 10:42:17 +1000 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Mackerras Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" allocation Cognitive DMA is a new set of DMA operations that solve some issues for devices that want to address more than 32 bits but can't address the 59 bits required to enable direct DMA. The previous implementation for POWER8/PHB3 worked around this by configuring a bypass from the default 32-bit address space into 64-bit address space. This approach does not work for POWER9/PHB4 because regions of memory are discontiguous and many devices will be unable to address memory beyond the first node. Instead, implement a new set of DMA operations that allocate TCEs as DMA mappings are requested so that all memory is addressable even when a one-to-one mapping between real addresses and DMA addresses isn't possible. These TCEs are the maximum size available on the platform, which is 256M on PHB3 and 1G on PHB4. Devices can now map any region of memory up to the maximum amount they can address according to the DMA mask set, in chunks of the largest available TCE size. This implementation replaces the need for the existing PHB3 solution and should be compatible with future PHB versions. Signed-off-by: Russell Currey --- arch/powerpc/include/asm/dma-mapping.h | 1 + arch/powerpc/platforms/powernv/Makefile | 2 +- arch/powerpc/platforms/powernv/pci-dma.c | 319 ++++++++++++++++++++++ arch/powerpc/platforms/powernv/pci-ioda.c | 102 +++---- arch/powerpc/platforms/powernv/pci.h | 7 + 5 files changed, 381 insertions(+), 50 deletions(-) create mode 100644 arch/powerpc/platforms/powernv/pci-dma.c diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h index 8fa394520af6..354f435160f3 100644 --- a/arch/powerpc/include/asm/dma-mapping.h +++ b/arch/powerpc/include/asm/dma-mapping.h @@ -74,6 +74,7 @@ static inline unsigned long device_to_mask(struct device *dev) extern struct dma_map_ops dma_iommu_ops; #endif extern const struct dma_map_ops dma_nommu_ops; +extern const struct dma_map_ops dma_pseudo_bypass_ops; static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus) { diff --git a/arch/powerpc/platforms/powernv/Makefile b/arch/powerpc/platforms/powernv/Makefile index 703a350a7f4e..2467bdab3c13 100644 --- a/arch/powerpc/platforms/powernv/Makefile +++ b/arch/powerpc/platforms/powernv/Makefile @@ -6,7 +6,7 @@ obj-y += opal-msglog.o opal-hmi.o opal-power.o opal-irqchip.o obj-y += opal-kmsg.o opal-powercap.o opal-psr.o opal-sensor-groups.o obj-$(CONFIG_SMP) += smp.o subcore.o subcore-asm.o -obj-$(CONFIG_PCI) += pci.o pci-ioda.o npu-dma.o +obj-$(CONFIG_PCI) += pci.o pci-ioda.o npu-dma.o pci-dma.o obj-$(CONFIG_CXL_BASE) += pci-cxl.o obj-$(CONFIG_EEH) += eeh-powernv.o obj-$(CONFIG_PPC_SCOM) += opal-xscom.o diff --git a/arch/powerpc/platforms/powernv/pci-dma.c b/arch/powerpc/platforms/powernv/pci-dma.c new file mode 100644 index 000000000000..1d5409be343e --- /dev/null +++ b/arch/powerpc/platforms/powernv/pci-dma.c @@ -0,0 +1,319 @@ +/* + * DMA operations supporting pseudo-bypass for PHB3+ + * + * Author: Russell Currey + * + * Copyright 2018 IBM Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "pci.h" + +/* select and allocate a TCE using the bitmap */ +static int dma_pseudo_bypass_select_tce(struct pnv_ioda_pe *pe, phys_addr_t addr) +{ + int tce; + __be64 old, new; + + spin_lock(&pe->tce_alloc_lock); + tce = bitmap_find_next_zero_area(pe->tce_bitmap, + pe->tce_count, + 0, + 1, + 0); + bitmap_set(pe->tce_bitmap, tce, 1); + old = pe->tces[tce]; + new = cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); + pe->tces[tce] = new; + pe_info(pe, "allocating TCE %i 0x%016llx (old 0x%016llx)\n", + tce, new, old); + spin_unlock(&pe->tce_alloc_lock); + + return tce; +} + +/* + * The tracking table for assigning TCEs has two entries per TCE. + * - @entry1 contains the physical address and the smallest bit indicates + * if it's currently valid. + * - @entry2 contains the DMA address returned in the upper 34 bits, and a + * refcount in the lower 30 bits. + */ +static dma_addr_t dma_pseudo_bypass_get_address(struct device *dev, + phys_addr_t addr) +{ + struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); + struct pci_controller *hose = pci_bus_to_host(pdev->bus); + struct pnv_phb *phb = hose->private_data; + struct pnv_ioda_pe *pe; + u64 i, entry1, entry2, dma_prefix, tce, ret; + u64 offset = addr & ((1 << phb->ioda.max_tce_order) - 1); + + pe = &phb->ioda.pe_array[pci_get_pdn(pdev)->pe_number]; + + /* look through the tracking table for a free entry */ + for (i = 0; i < pe->tce_count; i++) { + entry1 = pe->tce_tracker[i * 2]; + entry2 = pe->tce_tracker[i * 2 + 1]; + dma_prefix = entry2 >> 34; + + /* if the address is the same and the entry is valid */ + if (entry1 == ((addr - offset) | 1)) { + /* all we need to do here is increment the refcount */ + ret = cmpxchg(&pe->tce_tracker[i * 2 + 1], + entry2, entry2 + 1); + if (ret != entry2) { + /* conflict, start looking again just in case */ + i--; + continue; + } + return (dma_prefix << phb->ioda.max_tce_order) | offset; + /* if the entry is invalid then we want to replace it */ + } else if (!(entry1 & 1)) { + /* set the real address, note that it isn't valid yet */ + ret = cmpxchg(&pe->tce_tracker[i * 2], + entry1, (addr - offset)); + if (ret != entry1) { + /* conflict, start looking again */ + i--; + continue; + } + + /* now we can allocate a TCE */ + tce = dma_pseudo_bypass_select_tce(pe, addr - offset); + + /* set new value, including TCE index and new refcount */ + ret = cmpxchg(&pe->tce_tracker[i * 2 + 1], + entry2, tce << 34 | 1); + if (ret != entry2) { + /* + * XXX In this case we need to throw out + * everything, including the TCE we just + * allocated. For now, just leave it. + */ + i--; + continue; + } + + /* now set the valid bit */ + ret = cmpxchg(&pe->tce_tracker[i * 2], + (addr - offset), (addr - offset) | 1); + if (ret != (addr - offset)) { + /* + * XXX Same situation as above. We'd probably + * want to null out entry2 as well. + */ + i--; + continue; + } + return (tce << phb->ioda.max_tce_order) | offset; + /* it's a valid entry but not ours, keep looking */ + } else { + continue; + } + } + /* If we get here, the table must be full, so error out. */ + return -1ULL; +} + +/* + * For the moment, unmapping just decrements the refcount and doesn't actually + * remove the TCE. This is because it's very likely that a previously allocated + * TCE will be used again, and this saves having to invalidate it. + * + * TODO implement some kind of garbage collection that clears unused TCE entries + * once the table reaches a certain size. + */ +static void dma_pseudo_bypass_unmap_address(struct device *dev, dma_addr_t dma_addr) +{ + struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); + struct pci_controller *hose = pci_bus_to_host(pdev->bus); + struct pnv_phb *phb = hose->private_data; + struct pnv_ioda_pe *pe; + u64 i, entry1, entry2, dma_prefix, refcount; + + pe = &phb->ioda.pe_array[pci_get_pdn(pdev)->pe_number]; + + for (i = 0; i < pe->tce_count; i++) { + entry1 = pe->tce_tracker[i * 2]; + entry2 = pe->tce_tracker[i * 2 + 1]; + dma_prefix = entry2 >> 34; + refcount = entry2 & ((1 << 30) - 1); + + /* look through entry2 until we find our address */ + if (dma_prefix == (dma_addr >> phb->ioda.max_tce_order)) { + refcount--; + cmpxchg(&pe->tce_tracker[i * 2 + 1], entry2, (dma_prefix << 34) | refcount); + if (!refcount) { + /* + * Here is where we would remove the valid bit + * from entry1, clear the entry in the TCE table + * and invalidate the TCE - but we want to leave + * them until the table fills up (for now). + */ + } + break; + } + } +} + +static int dma_pseudo_bypass_dma_supported(struct device *dev, u64 mask) +{ + /* + * Normally dma_supported() checks if the mask is capable of addressing + * all of memory. Since we map physical memory in chunks that the + * device can address, the device will be able to address whatever it + * wants - just not all at once. + */ + return 1; +} + +static void *dma_pseudo_bypass_alloc_coherent(struct device *dev, + size_t size, + dma_addr_t *dma_handle, + gfp_t flag, + unsigned long attrs) +{ + void *ret; + struct page *page; + int node = dev_to_node(dev); + + /* ignore region specifiers */ + flag &= ~(__GFP_HIGHMEM); + + page = alloc_pages_node(node, flag, get_order(size)); + if (page == NULL) + return NULL; + ret = page_address(page); + memset(ret, 0, size); + *dma_handle = dma_pseudo_bypass_get_address(dev, __pa(ret)); + + return ret; +} + +static void dma_pseudo_bypass_free_coherent(struct device *dev, + size_t size, + void *vaddr, + dma_addr_t dma_handle, + unsigned long attrs) +{ + free_pages((unsigned long)vaddr, get_order(size)); +} + +static int dma_pseudo_bypass_mmap_coherent(struct device *dev, + struct vm_area_struct *vma, + void *cpu_addr, + dma_addr_t handle, + size_t size, + unsigned long attrs) +{ + unsigned long pfn = page_to_pfn(virt_to_page(cpu_addr)); + + return remap_pfn_range(vma, vma->vm_start, + pfn + vma->vm_pgoff, + vma->vm_end - vma->vm_start, + vma->vm_page_prot); +} + +static inline dma_addr_t dma_pseudo_bypass_map_page(struct device *dev, + struct page *page, + unsigned long offset, + size_t size, + enum dma_data_direction dir, + unsigned long attrs) +{ + BUG_ON(dir == DMA_NONE); + + /* XXX I don't know if this is necessary (or even desired) */ + if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC)) + __dma_sync_page(page, offset, size, dir); + + return dma_pseudo_bypass_get_address(dev, page_to_phys(page) + offset); +} + +static inline void dma_pseudo_bypass_unmap_page(struct device *dev, + dma_addr_t dma_address, + size_t size, + enum dma_data_direction direction, + unsigned long attrs) +{ + dma_pseudo_bypass_unmap_address(dev, dma_address); +} + + +static int dma_pseudo_bypass_map_sg(struct device *dev, struct scatterlist *sgl, + int nents, enum dma_data_direction direction, + unsigned long attrs) +{ + struct scatterlist *sg; + int i; + + + for_each_sg(sgl, sg, nents, i) { + sg->dma_address = dma_pseudo_bypass_get_address(dev, sg_phys(sg)); + sg->dma_length = sg->length; + + if (attrs & DMA_ATTR_SKIP_CPU_SYNC) + continue; + + __dma_sync_page(sg_page(sg), sg->offset, sg->length, direction); + } + + return nents; +} + +static void dma_pseudo_bypass_unmap_sg(struct device *dev, struct scatterlist *sgl, + int nents, enum dma_data_direction direction, + unsigned long attrs) +{ + struct scatterlist *sg; + int i; + + for_each_sg(sgl, sg, nents, i) { + dma_pseudo_bypass_unmap_address(dev, sg->dma_address); + } +} + +static u64 dma_pseudo_bypass_get_required_mask(struct device *dev) +{ + /* + * there's no limitation on our end, the driver should just call + * set_mask() with as many bits as the device can address. + */ + return -1ULL; +} + +static int dma_pseudo_bypass_mapping_error(struct device *dev, dma_addr_t dma_addr) +{ + return dma_addr == -1ULL; +} + + +const struct dma_map_ops dma_pseudo_bypass_ops = { + .alloc = dma_pseudo_bypass_alloc_coherent, + .free = dma_pseudo_bypass_free_coherent, + .mmap = dma_pseudo_bypass_mmap_coherent, + .map_sg = dma_pseudo_bypass_map_sg, + .unmap_sg = dma_pseudo_bypass_unmap_sg, + .dma_supported = dma_pseudo_bypass_dma_supported, + .map_page = dma_pseudo_bypass_map_page, + .unmap_page = dma_pseudo_bypass_unmap_page, + .get_required_mask = dma_pseudo_bypass_get_required_mask, + .mapping_error = dma_pseudo_bypass_mapping_error, +}; +EXPORT_SYMBOL(dma_pseudo_bypass_ops); diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index bcb3bfce072a..7ecc186493ca 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -1088,6 +1089,9 @@ static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) pe->pbus = NULL; pe->mve_number = -1; pe->rid = dev->bus->number << 8 | pdn->devfn; + pe->tces = NULL; + pe->tce_tracker = NULL; + pe->tce_bitmap = NULL; pe_info(pe, "Associated device to PE\n"); @@ -1569,6 +1573,9 @@ static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) pe->mve_number = -1; pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | pci_iov_virtfn_devfn(pdev, vf_index); + pe->tces = NULL; + pe->tce_tracker = NULL; + pe->tce_bitmap = NULL; pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", hose->global_number, pdev->bus->number, @@ -1774,43 +1781,40 @@ static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe) return true; } -/* - * Reconfigure TVE#0 to be usable as 64-bit DMA space. - * - * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. - * Devices can only access more than that if bit 59 of the PCI address is set - * by hardware, which indicates TVE#1 should be used instead of TVE#0. - * Many PCI devices are not capable of addressing that many bits, and as a - * result are limited to the 4GB of virtual memory made available to 32-bit - * devices in TVE#0. - * - * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit - * devices by configuring the virtual memory past the first 4GB inaccessible - * by 64-bit DMAs. This should only be used by devices that want more than - * 4GB, and only on PEs that have no 32-bit devices. - * - * Currently this will only work on PHB3 (POWER8). - */ -static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) +static int pnv_pci_pseudo_bypass_setup(struct pnv_ioda_pe *pe) { - u64 window_size, table_size, tce_count, addr; + u64 tce_count, table_size, window_size; + struct pnv_phb *p = pe->phb; struct page *table_pages; - u64 tce_order = 28; /* 256MB TCEs */ __be64 *tces; - s64 rc; + int rc = -ENOMEM; + int bitmap_size, tracker_entries; + + /* + * XXX These are factors for scaling the size of the TCE table, and + * the table that tracks these allocations. These should eventually + * be kernel command line options with defaults above 1, for situations + * where your memory expands after the machine has booted. + */ + int tce_size_factor = 1; + int tracking_table_factor = 1; /* - * Window size needs to be a power of two, but needs to account for - * shifting memory by the 4GB offset required to skip 32bit space. + * The window size covers all of memory (and optionally more), with + * enough tracker entries to cover them all being allocated. So we + * create enough TCEs to cover all of memory at once. */ - window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); - tce_count = window_size >> tce_order; + window_size = roundup_pow_of_two(tce_size_factor * memory_hotplug_max()); + tracker_entries = (tracking_table_factor * memory_hotplug_max()) >> + p->ioda.max_tce_order; + tce_count = window_size >> p->ioda.max_tce_order; + bitmap_size = BITS_TO_LONGS(tce_count) * sizeof(unsigned long); table_size = tce_count << 3; if (table_size < PAGE_SIZE) table_size = PAGE_SIZE; - table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, + table_pages = alloc_pages_node(p->hose->node, GFP_KERNEL, get_order(table_size)); if (!table_pages) goto err; @@ -1821,26 +1825,33 @@ static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) memset(tces, 0, table_size); - for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { - tces[(addr + (1ULL << 32)) >> tce_order] = - cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); - } + pe->tces = tces; + pe->tce_count = tce_count; + pe->tce_bitmap = kzalloc(bitmap_size, GFP_KERNEL); + /* The tracking table has two u64s per TCE */ + pe->tce_tracker = vzalloc(sizeof(u64) * 2 * tracker_entries); + spin_lock_init(&pe->tce_alloc_lock); + + /* mark the first 4GB as reserved so this can still be used for 32bit */ + bitmap_set(pe->tce_bitmap, 0, 1ULL << (32 - p->ioda.max_tce_order)); + + pe_info(pe, "pseudo-bypass sizes: tracker %d bitmap %d TCEs %lld\n", + tracker_entries, bitmap_size, tce_count); rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, pe->pe_number, - /* reconfigure window 0 */ (pe->pe_number << 1) + 0, 1, __pa(tces), table_size, - 1 << tce_order); + 1 << p->ioda.max_tce_order); if (rc == OPAL_SUCCESS) { - pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); + pe_info(pe, "TCE tables configured for pseudo-bypass\n"); return 0; } err: - pe_err(pe, "Error configuring 64-bit DMA bypass\n"); - return -EIO; + pe_err(pe, "error configuring pseudo-bypass\n"); + return rc; } static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) @@ -1851,7 +1862,6 @@ static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) struct pnv_ioda_pe *pe; uint64_t top; bool bypass = false; - s64 rc; if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) return -ENODEV; @@ -1868,21 +1878,15 @@ static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) } else { /* * If the device can't set the TCE bypass bit but still wants - * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to - * bypass the 32-bit region and be usable for 64-bit DMAs. - * The device needs to be able to address all of this space. + * to access 4GB or more, we need to use a different set of DMA + * operations with an indirect mapping. */ if (dma_mask >> 32 && - dma_mask > (memory_hotplug_max() + (1ULL << 32)) && - pnv_pci_ioda_pe_single_vendor(pe) && - phb->model == PNV_PHB_MODEL_PHB3) { - /* Configure the bypass mode */ - rc = pnv_pci_ioda_dma_64bit_bypass(pe); - if (rc) - return rc; - /* 4GB offset bypasses 32-bit space */ - set_dma_offset(&pdev->dev, (1ULL << 32)); - set_dma_ops(&pdev->dev, &dma_nommu_ops); + phb->model != PNV_PHB_MODEL_P7IOC && + pnv_pci_ioda_pe_single_vendor(pe)) { + if (!pe->tces) + pnv_pci_pseudo_bypass_setup(pe); + set_dma_ops(&pdev->dev, &dma_pseudo_bypass_ops); } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) { /* * Fail the request if a DMA mask between 32 and 64 bits diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h index c9952def5e93..83492aba90f1 100644 --- a/arch/powerpc/platforms/powernv/pci.h +++ b/arch/powerpc/platforms/powernv/pci.h @@ -70,6 +70,13 @@ struct pnv_ioda_pe { bool tce_bypass_enabled; uint64_t tce_bypass_base; + /* TCE tables for DMA pseudo-bypass */ + __be64 *tces; + u64 tce_count; + unsigned long *tce_bitmap; + u64 *tce_tracker; // 2 u64s per TCE + spinlock_t tce_alloc_lock; + /* MSIs. MVE index is identical for for 32 and 64 bit MSI * and -1 if not supported. (It's actually identical to the * PE number) From patchwork Sat Jun 23 23:53:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timothy Pearson X-Patchwork-Id: 933823 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Cv6S2Xc3z9s2R for ; Sun, 24 Jun 2018 10:57:36 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=raptorengineering.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=raptorengineering.com header.i=@raptorengineering.com header.b="pFHCWTws"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 41Cv6S0psgzF164 for ; Sun, 24 Jun 2018 10:57:36 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=raptorengineering.com Authentication-Results: lists.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=raptorengineering.com header.i=@raptorengineering.com header.b="pFHCWTws"; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=raptorengineering.com (client-ip=192.119.205.245; helo=mail.rptsys.com; envelope-from=tpearson@raptorengineering.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=raptorengineering.com Authentication-Results: lists.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=raptorengineering.com header.i=@raptorengineering.com header.b="pFHCWTws"; dkim-atps=neutral Received: from mail.rptsys.com (mail.rptsys.com [192.119.205.245]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 41Csw03nSmzF14f for ; Sun, 24 Jun 2018 10:03:28 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by mail.rptsys.com (Postfix) with ESMTP id 938486428B1; Sat, 23 Jun 2018 18:53:29 -0500 (CDT) Received: from mail.rptsys.com ([127.0.0.1]) by localhost (vali.starlink.edu [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id vveHCvE8w5vr; Sat, 23 Jun 2018 18:53:28 -0500 (CDT) Received: from localhost (localhost [127.0.0.1]) by mail.rptsys.com (Postfix) with ESMTP id C12656428AE; Sat, 23 Jun 2018 18:53:28 -0500 (CDT) DKIM-Filter: OpenDKIM Filter v2.9.2 mail.rptsys.com C12656428AE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=raptorengineering.com; s=B8E824E6-0BE2-11E6-931D-288C65937AAD; t=1529798008; bh=F4yDmmbHH69y3+VTut3UdpNOzoOmUoZtCzaSs61LV2s=; h=Date:From:To:Message-ID:Subject:MIME-Version:Content-Type: Content-Transfer-Encoding; b=pFHCWTwsCoFzPwDoDMMusBYyKObCYtsGlVf5D3UN8jYK6kDXKHIzt/PQ5XnDk1Vwe Zgd7Ncif43MKDTGLOFn8+7XDUOoigJX9mOgdC78VozYbtLg4xEMS8d+eoQ6UQLNdSY X17mK5dB7LgztZXwjM6WsOYlJ++DdfAsAhD76kNg= X-Virus-Scanned: amavisd-new at rptsys.com Received: from mail.rptsys.com ([127.0.0.1]) by localhost (vali.starlink.edu [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id aVxyrZ4_1tye; Sat, 23 Jun 2018 18:53:28 -0500 (CDT) Received: from vali.starlink.edu (vali.starlink.edu [192.168.3.21]) by mail.rptsys.com (Postfix) with ESMTP id 7C9C2642869; Sat, 23 Jun 2018 18:53:28 -0500 (CDT) Date: Sat, 23 Jun 2018 18:53:28 -0500 (CDT) From: Timothy Pearson To: linuxppc-dev@lists.ozlabs.org Message-ID: <1820986268.2569250.1529798008396.JavaMail.zimbra@raptorengineeringinc.com> Subject: [PATCH 3/7] powerpc/powernv/pci: Track DMA and TCE tables in debugfs MIME-Version: 1.0 X-Mailer: Zimbra 8.5.0_GA_3042 (ZimbraWebClient - FF3.6 (Linux)/8.5.0_GA_3042) Thread-Topic: powerpc/powernv/pci: Track DMA and TCE tables in debugfs Thread-Index: oG83j61aOBSIlGh5LUfZgfdaH1NwPw== X-Mailman-Approved-At: Sun, 24 Jun 2018 10:42:17 +1000 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Mackerras Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Add a new debugfs entry to trigger dumping out the tracking table and TCEs for a given PE, for example PE 0x4 of PHB 2: echo 0x4 > /sys/kernel/debug/powerpc/PCI0002/sketchy This will result in the table being dumped out in dmesg. Signed-off-by: Russell Currey --- arch/powerpc/platforms/powernv/pci-ioda.c | 43 +++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index 7ecc186493ca..55f0f7b885bc 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -3342,6 +3342,47 @@ static int pnv_pci_diag_data_set(void *data, u64 val) DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, pnv_pci_diag_data_set, "%llu\n"); +static int pnv_pci_sketchy_set(void *data, u64 val) +{ + struct pci_controller *hose; + struct pnv_ioda_pe *pe; + struct pnv_phb *phb; + u64 entry1, entry2; + int i; + + hose = (struct pci_controller *)data; + if (!hose || !hose->private_data) + return -ENODEV; + + phb = hose->private_data; + pe = &phb->ioda.pe_array[val]; + + if (!pe) + return -EINVAL; + + if (!pe->tces || !pe->tce_tracker) + return -EIO; + + for (i = 0; i < pe->tce_count; i++) { + if (i > 16 && pe->tces[i] == 0) + break; + pr_info("%3d: %016llx\n", i, be64_to_cpu(pe->tces[i])); + } + + for (i = 0; i < pe->tce_count; i++) { + entry1 = pe->tce_tracker[i * 2]; + entry2 = pe->tce_tracker[i * 2 + 1]; + if (!entry1) + break; + pr_info("%3d: %016llx %016llx\n", i, entry1, entry2); + } + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_sketchy_fops, NULL, + pnv_pci_sketchy_set, "%llu\n"); + + #endif /* CONFIG_DEBUG_FS */ static void pnv_pci_ioda_create_dbgfs(void) @@ -3367,6 +3408,8 @@ static void pnv_pci_ioda_create_dbgfs(void) debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose, &pnv_pci_diag_data_fops); + debugfs_create_file("sketchy", 0200, phb->dbgfs, hose, + &pnv_pci_sketchy_fops); } #endif /* CONFIG_DEBUG_FS */ } From patchwork Sat Jun 23 23:53:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timothy Pearson X-Patchwork-Id: 933824 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Cv9663k8z9s2R for ; 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Sat, 23 Jun 2018 18:53:55 -0500 (CDT) DKIM-Filter: OpenDKIM Filter v2.9.2 mail.rptsys.com 27BFD6428B8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=raptorengineering.com; s=B8E824E6-0BE2-11E6-931D-288C65937AAD; t=1529798035; bh=zdLIaptXyGL1SVERJfxZ2iAPm4/Q3RtGVLG7Ic69xNc=; h=Date:From:To:Message-ID:Subject:MIME-Version:Content-Type: Content-Transfer-Encoding; b=BKeIuvxrMAlIHfP2sCwFK2pGgfilhmCUxRTyk+4Uz35wDDciEcTwvBaQZCm33W+j2 M4U9VDrsDv7/974Kp+4wkqrOpiTlDC92YMP9Ca/3VAu7aja8XzrLuBN+gxXGgNrElk 0Zp4eRLpHmjhbmreQSFTJhk/j5yZBUR4NsQZ/sKE= X-Virus-Scanned: amavisd-new at rptsys.com Received: from mail.rptsys.com ([127.0.0.1]) by localhost (vali.starlink.edu [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id 9lFLP1jjpOdk; Sat, 23 Jun 2018 18:53:54 -0500 (CDT) Received: from vali.starlink.edu (netrouter.starlink.edu [192.168.3.1]) by mail.rptsys.com (Postfix) with ESMTP id D6BB96428B4; Sat, 23 Jun 2018 18:53:54 -0500 (CDT) Date: Sat, 23 Jun 2018 18:53:54 -0500 (CDT) From: Timothy Pearson To: linuxppc-dev@lists.ozlabs.org Message-ID: <955790001.2569251.1529798034743.JavaMail.zimbra@raptorengineeringinc.com> Subject: [PATCH 4/7] powerpc/powernv/pci: Safety fixes for pseudobypass TCE MIME-Version: 1.0 X-Mailer: Zimbra 8.5.0_GA_3042 (ZimbraWebClient - FF3.6 (Linux)/8.5.0_GA_3042) Thread-Topic: powerpc/powernv/pci: Safety fixes for pseudobypass TCE Thread-Index: QW8SWb3YXtahyGZt1Y15YFdVjbGYnQ== X-Mailman-Approved-At: Sun, 24 Jun 2018 10:42:17 +1000 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Mackerras Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" allocation Signed-off-by: Russell Currey --- arch/powerpc/platforms/powernv/pci-dma.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/platforms/powernv/pci-dma.c b/arch/powerpc/platforms/powernv/pci-dma.c index 1d5409be343e..237940a2a052 100644 --- a/arch/powerpc/platforms/powernv/pci-dma.c +++ b/arch/powerpc/platforms/powernv/pci-dma.c @@ -29,8 +29,9 @@ static int dma_pseudo_bypass_select_tce(struct pnv_ioda_pe *pe, phys_addr_t addr { int tce; __be64 old, new; + unsigned long flags; - spin_lock(&pe->tce_alloc_lock); + spin_lock_irqsave(&pe->tce_alloc_lock, flags); tce = bitmap_find_next_zero_area(pe->tce_bitmap, pe->tce_count, 0, @@ -40,9 +41,10 @@ static int dma_pseudo_bypass_select_tce(struct pnv_ioda_pe *pe, phys_addr_t addr old = pe->tces[tce]; new = cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); pe->tces[tce] = new; + mb(); pe_info(pe, "allocating TCE %i 0x%016llx (old 0x%016llx)\n", tce, new, old); - spin_unlock(&pe->tce_alloc_lock); + spin_unlock_irqrestore(&pe->tce_alloc_lock, flags); return tce; } From patchwork Sat Jun 23 23:54:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timothy Pearson X-Patchwork-Id: 933821 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Cv176ZPZz9s2R for ; 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Sat, 23 Jun 2018 18:54:16 -0500 (CDT) DKIM-Filter: OpenDKIM Filter v2.9.2 mail.rptsys.com 9FABD6428BF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=raptorengineering.com; s=B8E824E6-0BE2-11E6-931D-288C65937AAD; t=1529798056; bh=PHuFQ1yIgcsK9KzXoq9OqFrrU8fHsX++t1kZgvOdKiI=; h=Date:From:To:Message-ID:Subject:MIME-Version:Content-Type: Content-Transfer-Encoding; b=lRMYI7tUds4zYMjjQrrGipr9g7BxAIlsffJdlBuGaydqaOJVnHfHsDXK/M2gL/u2Y HmPTUzmIUTCRdTImVRdzhUKY5yq7joWEB7tkJtTnyEKt4bvvfUpnTCSmvFJrVe/ypf oDIsIp8gYC4FewP4QsIuHlzLHKfLXjg2macnCc0I= X-Virus-Scanned: amavisd-new at rptsys.com Received: from mail.rptsys.com ([127.0.0.1]) by localhost (vali.starlink.edu [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id 7gZLtg2Uv0Y8; Sat, 23 Jun 2018 18:54:16 -0500 (CDT) Received: from vali.starlink.edu (vali.starlink.edu [192.168.3.21]) by mail.rptsys.com (Postfix) with ESMTP id 695D96428BB; Sat, 23 Jun 2018 18:54:16 -0500 (CDT) Date: Sat, 23 Jun 2018 18:54:16 -0500 (CDT) From: Timothy Pearson To: linuxppc-dev@lists.ozlabs.org Message-ID: <225890156.2569252.1529798056341.JavaMail.zimbra@raptorengineeringinc.com> Subject: [PATCH 5/7] powerpc/powernv/pci: Export MIME-Version: 1.0 X-Mailer: Zimbra 8.5.0_GA_3042 (ZimbraWebClient - FF3.6 (Linux)/8.5.0_GA_3042) Thread-Topic: powerpc/powernv/pci: Export Thread-Index: +FYE2xkjoZhD88r85vpquPeK9G1V+w== X-Mailman-Approved-At: Sun, 24 Jun 2018 10:42:17 +1000 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Mackerras Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" pnv_pci_ioda2_tce_invalidate_pe Pseudo DMA support requires a method to invalidate the TCE cache Export pnv_pci_ioda2_tce_invalidate_pe for use by the pseudo DMA mapper. Signed-off-by: Timothy Pearson --- arch/powerpc/platforms/powernv/pci-ioda.c | 2 +- arch/powerpc/platforms/powernv/pci.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index 55f0f7b885bc..a6097dd323f8 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -2102,7 +2102,7 @@ static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, } } -static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) +void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) { struct pnv_phb *phb = pe->phb; diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h index 83492aba90f1..8d3849e76be3 100644 --- a/arch/powerpc/platforms/powernv/pci.h +++ b/arch/powerpc/platforms/powernv/pci.h @@ -264,6 +264,7 @@ extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, /* Nvlink functions */ extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass); extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm); +extern void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe); extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe); extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num, struct iommu_table *tbl); From patchwork Sat Jun 23 23:54:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timothy Pearson X-Patchwork-Id: 933820 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Ctyc6hFwz9s2R for ; Sun, 24 Jun 2018 10:50:48 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=raptorengineering.com Authentication-Results: ozlabs.org; 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s=B8E824E6-0BE2-11E6-931D-288C65937AAD; t=1529798077; bh=4qAYiDs4bpnZuUO8IxOrl3cHmNY5zrTalu3/TXUCHV4=; h=Date:From:To:Message-ID:Subject:MIME-Version:Content-Type: Content-Transfer-Encoding; b=ve0Iw9/qDsIn2AuGTDKjMSLDxyCEWarw/espOsWWM6Y4xlLKAFvDQJZi8EBDWshOW hOeKReK2v10Df25OvE8Evk0LzXdyZh7U+/BfHafzhm5EFvmzzWSagHi2FLeLS8Mz42 /p1M/CC2nnm2zHc4n9D5UNCk0uydjHgPVc4XQ9+s= X-Virus-Scanned: amavisd-new at rptsys.com Received: from mail.rptsys.com ([127.0.0.1]) by localhost (vali.starlink.edu [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id 2Iksm81gi3kI; Sat, 23 Jun 2018 18:54:37 -0500 (CDT) Received: from vali.starlink.edu (vali.starlink.edu [192.168.3.21]) by mail.rptsys.com (Postfix) with ESMTP id 029466428BE; Sat, 23 Jun 2018 18:54:37 -0500 (CDT) Date: Sat, 23 Jun 2018 18:54:36 -0500 (CDT) From: Timothy Pearson To: linuxppc-dev@lists.ozlabs.org Message-ID: <1298010887.2569253.1529798076885.JavaMail.zimbra@raptorengineeringinc.com> Subject: [PATCH 6/7] powerpc/powernv/pci: Invalidate TCE cache after DMA map MIME-Version: 1.0 X-Mailer: Zimbra 8.5.0_GA_3042 (ZimbraWebClient - FF3.6 (Linux)/8.5.0_GA_3042) Thread-Topic: powerpc/powernv/pci: Invalidate TCE cache after DMA map Thread-Index: XThkSZuk+06+kFPVOVAy0ZXBeX6nDA== X-Mailman-Approved-At: Sun, 24 Jun 2018 10:42:17 +1000 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Mackerras Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" setup Per the IODA2, TCEs must be invalidated after their settings have been changed. Invalidate the cache after the address is changed during TCE allocation when using pseudo DMA. Signed-off-by: Timothy Pearson --- arch/powerpc/platforms/powernv/pci-dma.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/powerpc/platforms/powernv/pci-dma.c b/arch/powerpc/platforms/powernv/pci-dma.c index 237940a2a052..060dbc168401 100644 --- a/arch/powerpc/platforms/powernv/pci-dma.c +++ b/arch/powerpc/platforms/powernv/pci-dma.c @@ -42,8 +42,7 @@ static int dma_pseudo_bypass_select_tce(struct pnv_ioda_pe *pe, phys_addr_t addr new = cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); pe->tces[tce] = new; mb(); - pe_info(pe, "allocating TCE %i 0x%016llx (old 0x%016llx)\n", - tce, new, old); + pnv_pci_ioda2_tce_invalidate_pe(pe); spin_unlock_irqrestore(&pe->tce_alloc_lock, flags); return tce; From patchwork Sat Jun 23 23:54:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timothy Pearson X-Patchwork-Id: 933822 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Cv3d3vFpz9s2R for ; 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Sat, 23 Jun 2018 18:54:58 -0500 (CDT) DKIM-Filter: OpenDKIM Filter v2.9.2 mail.rptsys.com 62F9C6428C4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=raptorengineering.com; s=B8E824E6-0BE2-11E6-931D-288C65937AAD; t=1529798098; bh=W2GR4AZy1EX7HIa6cx+nKiZi6vDav5TPexI5uKu8QYU=; h=Date:From:To:Message-ID:Subject:MIME-Version:Content-Type: Content-Transfer-Encoding; b=kxad+z4YXqcbKXjvHXOGd/QYeBasoZiuPW6OLCZ5wJwAgqWgaIyYzVeKtV79vzzVh gDdfUUOVeGmvlkfOonb4Gt7+KWFq4n237DMAvYJnLLBj3UHD8Rdvl7rHSOhuNQhd76 wjeyqx94wgcUhTILNBHJC5pqKMp4jBjz2beMDo2Q= X-Virus-Scanned: amavisd-new at rptsys.com Received: from mail.rptsys.com ([127.0.0.1]) by localhost (vali.starlink.edu [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id ARMCpSyow8fJ; Sat, 23 Jun 2018 18:54:58 -0500 (CDT) Received: from vali.starlink.edu (localhost [127.0.0.1]) by mail.rptsys.com (Postfix) with ESMTP id 1D34C6428C0; Sat, 23 Jun 2018 18:54:58 -0500 (CDT) Date: Sat, 23 Jun 2018 18:54:58 -0500 (CDT) From: Timothy Pearson To: linuxppc-dev@lists.ozlabs.org Message-ID: <698112983.2569254.1529798098017.JavaMail.zimbra@raptorengineeringinc.com> Subject: [PATCH 7/7] powerpc/powernv/pci: Don't use the lower 4G TCEs in MIME-Version: 1.0 X-Mailer: Zimbra 8.5.0_GA_3042 (ZimbraWebClient - FF3.6 (Linux)/8.5.0_GA_3042) Thread-Topic: powerpc/powernv/pci: Don't use the lower 4G TCEs in Thread-Index: 3j5mPUQAI1/e2mF/RyskYXk6DjVVFA== X-Mailman-Approved-At: Sun, 24 Jun 2018 10:42:17 +1000 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Mackerras Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" pseudo-DMA mode Four TCEs are reserved for legacy 32-bit DMA mappings in psuedo DMA mode. Mark these with an invalid address to avoid their use by the TCE cache mapper. Signed-off-by: Timothy Pearson --- arch/powerpc/platforms/powernv/pci-ioda.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index a6097dd323f8..e8a1333f6b3e 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -1783,7 +1783,7 @@ static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe) static int pnv_pci_pseudo_bypass_setup(struct pnv_ioda_pe *pe) { - u64 tce_count, table_size, window_size; + u64 i, tce_count, table_size, window_size; struct pnv_phb *p = pe->phb; struct page *table_pages; __be64 *tces; @@ -1835,6 +1835,12 @@ static int pnv_pci_pseudo_bypass_setup(struct pnv_ioda_pe *pe) /* mark the first 4GB as reserved so this can still be used for 32bit */ bitmap_set(pe->tce_bitmap, 0, 1ULL << (32 - p->ioda.max_tce_order)); + /* make sure reserved first 4GB TCEs are not used by the mapper + * set each address to -1, which will never match an incoming request + */ + for (i = 0; i < 4; i++) + pe->tce_tracker[i * 2] = -1; + pe_info(pe, "pseudo-bypass sizes: tracker %d bitmap %d TCEs %lld\n", tracker_entries, bitmap_size, tce_count);