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dmarc=pass (p=none dis=none) header.from=gmail.com X-Mailman-Original-Authentication-Results: smtp1.osuosl.org; dkim=pass (2048-bit key, unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=j//1ZpVQ Subject: [Buildroot] [PATCH v2 01/11] platform/layerscape: bump Linux Factory tag to lf-6.6.36-2.1.0 X-BeenThere: buildroot@buildroot.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: buildroot-bounces@buildroot.org Sender: "buildroot" Update the following packages to the latest Linux Factory tag: - qoriq-cadence-dp-firmware - the updated download path was taken from the Yocto BSP at https://github.com/nxp-qoriq/yocto-sdk. - the recipe is here: https://github.com/Freescale/meta-freescale/blob/master/recipes-bsp/dp-firmware-cadence/dp-firmware-cadence_22.04.bb - arm-trusted-firmware - linux - u-boot - fmc - fmlib - qoriq-rcw Signed-off-by: Vladimir Oltean --- v1->v2: - reference LDLSDKUG instead of LLDPUG which is now apparently obsolete. - explain relationship to Linux Factory .../arm-trusted-firmware.hash | 2 +- .../ls1028ardb/patches/linux/linux.hash | 2 +- .../ls1028ardb/patches/uboot/uboot.hash | 2 +- board/freescale/ls1028ardb/readme.txt | 27 ++++++++++------ .../arm-trusted-firmware.hash | 2 +- .../ls1046a-frwy/patches/linux/linux.hash | 2 +- .../ls1046a-frwy/patches/uboot/uboot.hash | 2 +- board/freescale/ls1046a-frwy/readme.txt | 31 +++++++++++++------ configs/ls1028ardb_defconfig | 6 ++-- configs/ls1046a-frwy_defconfig | 6 ++-- package/fmc/fmc.hash | 2 +- package/fmc/fmc.mk | 2 +- package/fmlib/fmlib.hash | 2 +- package/fmlib/fmlib.mk | 2 +- .../qoriq-cadence-dp-firmware.hash | 2 +- .../qoriq-cadence-dp-firmware.mk | 10 +++--- package/qoriq-fm-ucode/qoriq-fm-ucode.hash | 2 +- package/qoriq-fm-ucode/qoriq-fm-ucode.mk | 2 +- package/qoriq-rcw/qoriq-rcw.hash | 2 +- package/qoriq-rcw/qoriq-rcw.mk | 2 +- 20 files changed, 65 insertions(+), 45 deletions(-) diff --git a/board/freescale/ls1028ardb/patches/arm-trusted-firmware/arm-trusted-firmware.hash b/board/freescale/ls1028ardb/patches/arm-trusted-firmware/arm-trusted-firmware.hash index f9af28ab3cf5..942dab47072c 100644 --- a/board/freescale/ls1028ardb/patches/arm-trusted-firmware/arm-trusted-firmware.hash +++ b/board/freescale/ls1028ardb/patches/arm-trusted-firmware/arm-trusted-firmware.hash @@ -1,2 +1,2 @@ # Locally calculated -sha256 4f4dc78bfb5b7391a65ae0f83856661071f666ac2bf6a9380fddbe376a8bdaaa atf-lf-6.6.23-2.0.0.tar.gz +sha256 4562efdc08efae7d36f3ee481871aac8ed0c856f8023d2186e4affdc5b768270 atf-lf-6.6.36-2.1.0.tar.gz diff --git a/board/freescale/ls1028ardb/patches/linux/linux.hash b/board/freescale/ls1028ardb/patches/linux/linux.hash index e038c2286237..bfdc2c268d2d 100644 --- a/board/freescale/ls1028ardb/patches/linux/linux.hash +++ b/board/freescale/ls1028ardb/patches/linux/linux.hash @@ -1,2 +1,2 @@ # Locally computed -sha256 6d592722e004516309f8ce33e654f1322e4d1f0f33567acb86ca19229176fd9e linux-lf-6.6.23-2.0.0.tar.gz +sha256 26e0db3dda786d939269f85df0f605e28cb55646ab8c541fc9bbbb4ab7fd9bf3 linux-lf-6.6.36-2.1.0.tar.gz diff --git a/board/freescale/ls1028ardb/patches/uboot/uboot.hash b/board/freescale/ls1028ardb/patches/uboot/uboot.hash index a5ccd82b2b0d..b1d83aa9135e 100644 --- a/board/freescale/ls1028ardb/patches/uboot/uboot.hash +++ b/board/freescale/ls1028ardb/patches/uboot/uboot.hash @@ -1,2 +1,2 @@ # Locally computed -sha256 a2bcd7a34d4908ffbadfea731d0f0fd20f19a31cff6ff6310980e7f6743ceb24 u-boot-lf-6.6.23-2.0.0.tar.gz +sha256 51adf233d53af875f70cf451e5950dd0b6af09ff35e546eacc4ec6998454c7eb u-boot-lf-6.6.36-2.1.0.tar.gz diff --git a/board/freescale/ls1028ardb/readme.txt b/board/freescale/ls1028ardb/readme.txt index 6633d60b9013..95f0694b744e 100644 --- a/board/freescale/ls1028ardb/readme.txt +++ b/board/freescale/ls1028ardb/readme.txt @@ -4,19 +4,28 @@ NXP LS1028ARDB This file documents the Buildroot support for the LS1028A Reference Design Board. -for more details about the board and the QorIQ Layerscape SoC, see the following pages: +For more details about the board and the QorIQ Layerscape SoC, see the following pages: - https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1028a-reference-design-board:LS1028ARDB - https://www.nxp.com/LS1028A -for the software NXP LSDK (Layerscape Software Development Kit), see - - https://www.nxp.com/docs/en/user-guide/LSDKUG_Rev21.08.pdf +Layerscape platforms are officially supported by NXP under the Layerscape +Debian Linux SDK (LDLSDK). This uses components from Linux Factory, currently +tag lf-6.6.3_1.0.0, a few releases behind the latest lf-6.6.36-2.1.0. +In Buildroot, the latest Linux Factory release tag is used. -the components from NXP are: - - rcw, lf-6.6.23-2.0.0 - - atf (fork), lf-6.6.23-2.0.0 - - uboot (fork), lf-6.6.23-2.0.0 - - cadence-dp-firmware (blob), LSDK 20.12 - - linux (fork), lf-6.6.23-2.0.0 +For the software Layerscape Debian Linux SDK User Guide, see: + - https://docs.nxp.com/bundle/UG10143/page/topics/about_this_document.html + - https://www.nxp.com/docs/en/user-guide/UG10143.pdf + +Note: the latest Linux Factory release may contain features which are not yet +documented in the LDLSDKUG. + +The components from NXP are: + - rcw, lf-6.6.36-2.1.0 + - atf (fork), lf-6.6.36-2.1.0 + - uboot (fork), lf-6.6.36-2.1.0 + - cadence-dp-firmware (blob), lf-6.6.36-2.1.0 + - linux (fork), lf-6.6.36-2.1.0 Build ===== diff --git a/board/freescale/ls1046a-frwy/patches/arm-trusted-firmware/arm-trusted-firmware.hash b/board/freescale/ls1046a-frwy/patches/arm-trusted-firmware/arm-trusted-firmware.hash index f9af28ab3cf5..942dab47072c 100644 --- a/board/freescale/ls1046a-frwy/patches/arm-trusted-firmware/arm-trusted-firmware.hash +++ b/board/freescale/ls1046a-frwy/patches/arm-trusted-firmware/arm-trusted-firmware.hash @@ -1,2 +1,2 @@ # Locally calculated -sha256 4f4dc78bfb5b7391a65ae0f83856661071f666ac2bf6a9380fddbe376a8bdaaa atf-lf-6.6.23-2.0.0.tar.gz +sha256 4562efdc08efae7d36f3ee481871aac8ed0c856f8023d2186e4affdc5b768270 atf-lf-6.6.36-2.1.0.tar.gz diff --git a/board/freescale/ls1046a-frwy/patches/linux/linux.hash b/board/freescale/ls1046a-frwy/patches/linux/linux.hash index e038c2286237..bfdc2c268d2d 100644 --- a/board/freescale/ls1046a-frwy/patches/linux/linux.hash +++ b/board/freescale/ls1046a-frwy/patches/linux/linux.hash @@ -1,2 +1,2 @@ # Locally computed -sha256 6d592722e004516309f8ce33e654f1322e4d1f0f33567acb86ca19229176fd9e linux-lf-6.6.23-2.0.0.tar.gz +sha256 26e0db3dda786d939269f85df0f605e28cb55646ab8c541fc9bbbb4ab7fd9bf3 linux-lf-6.6.36-2.1.0.tar.gz diff --git a/board/freescale/ls1046a-frwy/patches/uboot/uboot.hash b/board/freescale/ls1046a-frwy/patches/uboot/uboot.hash index a5ccd82b2b0d..b1d83aa9135e 100644 --- a/board/freescale/ls1046a-frwy/patches/uboot/uboot.hash +++ b/board/freescale/ls1046a-frwy/patches/uboot/uboot.hash @@ -1,2 +1,2 @@ # Locally computed -sha256 a2bcd7a34d4908ffbadfea731d0f0fd20f19a31cff6ff6310980e7f6743ceb24 u-boot-lf-6.6.23-2.0.0.tar.gz +sha256 51adf233d53af875f70cf451e5950dd0b6af09ff35e546eacc4ec6998454c7eb u-boot-lf-6.6.36-2.1.0.tar.gz diff --git a/board/freescale/ls1046a-frwy/readme.txt b/board/freescale/ls1046a-frwy/readme.txt index 4d1e0e1dcd9c..17dc23cc7c4a 100644 --- a/board/freescale/ls1046a-frwy/readme.txt +++ b/board/freescale/ls1046a-frwy/readme.txt @@ -4,20 +4,31 @@ NXP LS1046A-FRWY This file documents the Buildroot support for the LS1046A Freeway Board. -for more details about the board and the QorIQ Layerscape SoC, see the following pages: +For more details about the board and the QorIQ Layerscape SoC, see the following pages: - https://www.nxp.com/design/software/qoriq-developer-resources/ls1046a-freeway-board:FRWY-LS1046A - https://www.nxp.com/FRWY-LS1046A - https://www.nxp.com/docs/en/quick-reference-guide/FRWY-LS1046AGSG.pdf -for the software NXP LSDK (Layerscape Software Development Kit), see - - https://www.nxp.com/docs/en/user-guide/LSDKUG_Rev21.08.pdf - -the components from NXP are: - - rcw, lf-6.6.23-2.0.0 - - atf (fork), lf-6.6.23-2.0.0 - - uboot (fork), lf-6.6.23-2.0.0 - - qoriq-fm-ucode (blob), lf-6.6.23-2.0.0 - - linux (fork), lf-6.6.23-2.0.0 +Layerscape platforms are officially supported by NXP under the Layerscape +Debian Linux SDK (LDLSDK). This uses components from Linux Factory, currently +tag lf-6.6.3_1.0.0, a few releases behind the latest lf-6.6.36-2.1.0. +In Buildroot, the latest Linux Factory release tag is used. + +For the software Layerscape Debian Linux SDK User Guide, see: + - https://docs.nxp.com/bundle/UG10143/page/topics/about_this_document.html + - https://www.nxp.com/docs/en/user-guide/UG10143.pdf + +Note: the latest Linux Factory release may contain features which are not yet +documented in the LDLSDKUG. + +The components from NXP are: + - rcw, lf-6.6.36-2.1.0 + - atf (fork), lf-6.6.36-2.1.0 + - uboot (fork), lf-6.6.36-2.1.0 + - qoriq-fm-ucode (blob), lf-6.6.36-2.1.0 + - linux (fork), lf-6.6.36-2.1.0 + - fmlib, lf-6.6.36-2.1.0 + - fmc, lf-6.6.36-2.1.0 Build ===== diff --git a/configs/ls1028ardb_defconfig b/configs/ls1028ardb_defconfig index 0d1843bf5fce..e73e9a954584 100644 --- a/configs/ls1028ardb_defconfig +++ b/configs/ls1028ardb_defconfig @@ -12,7 +12,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="support/scripts/genimage.sh" BR2_ROOTFS_POST_SCRIPT_ARGS="-c board/freescale/ls1028ardb/genimage.cfg" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_TARBALL=y -BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="$(call github,nxp-qoriq,linux,lf-6.6.23-2.0.0)/linux-lf-6.6.23-2.0.0.tar.gz" +BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="$(call github,nxp-qoriq,linux,lf-6.6.36-2.1.0)/linux-lf-6.6.36-2.1.0.tar.gz" BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG=y BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(LINUX_DIR)/arch/arm64/configs/lsdk.config" BR2_LINUX_KERNEL_DTS_SUPPORT=y @@ -25,7 +25,7 @@ BR2_TARGET_ROOTFS_EXT2_SIZE="128M" # BR2_TARGET_ROOTFS_TAR is not set BR2_TARGET_ARM_TRUSTED_FIRMWARE=y BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL=y -BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL_LOCATION="$(call github,nxp-qoriq,atf,lf-6.6.23-2.0.0)/atf-lf-6.6.23-2.0.0.tar.gz" +BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL_LOCATION="$(call github,nxp-qoriq,atf,lf-6.6.36-2.1.0)/atf-lf-6.6.36-2.1.0.tar.gz" BR2_TARGET_ARM_TRUSTED_FIRMWARE_PLATFORM="ls1028ardb" BR2_TARGET_ARM_TRUSTED_FIRMWARE_FIP=y BR2_TARGET_ARM_TRUSTED_FIRMWARE_UBOOT_AS_BL33=y @@ -35,7 +35,7 @@ BR2_TARGET_ARM_TRUSTED_FIRMWARE_IMAGES="fip.bin bl2_sd.pbl" BR2_TARGET_UBOOT=y BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y BR2_TARGET_UBOOT_CUSTOM_TARBALL=y -BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="$(call github,nxp-qoriq,u-boot,lf-6.6.23-2.0.0)/u-boot-lf-6.6.23-2.0.0.tar.gz" +BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="$(call github,nxp-qoriq,u-boot,lf-6.6.36-2.1.0)/u-boot-lf-6.6.36-2.1.0.tar.gz" BR2_TARGET_UBOOT_BOARD_DEFCONFIG="ls1028ardb_tfa" BR2_TARGET_UBOOT_NEEDS_DTC=y BR2_PACKAGE_HOST_GENIMAGE=y diff --git a/configs/ls1046a-frwy_defconfig b/configs/ls1046a-frwy_defconfig index 2cf0f9c8bc50..7b86d6ba9810 100644 --- a/configs/ls1046a-frwy_defconfig +++ b/configs/ls1046a-frwy_defconfig @@ -12,7 +12,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="support/scripts/genimage.sh" BR2_ROOTFS_POST_SCRIPT_ARGS="-c board/freescale/ls1046a-frwy/genimage.cfg" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_TARBALL=y -BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="$(call github,nxp-qoriq,linux,lf-6.6.23-2.0.0)/linux-lf-6.6.23-2.0.0.tar.gz" +BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="$(call github,nxp-qoriq,linux,lf-6.6.36-2.1.0)/linux-lf-6.6.36-2.1.0.tar.gz" BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG=y BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(LINUX_DIR)/arch/arm64/configs/lsdk.config" BR2_LINUX_KERNEL_DTS_SUPPORT=y @@ -25,7 +25,7 @@ BR2_TARGET_ROOTFS_EXT2_SIZE="128M" # BR2_TARGET_ROOTFS_TAR is not set BR2_TARGET_ARM_TRUSTED_FIRMWARE=y BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL=y -BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL_LOCATION="$(call github,nxp-qoriq,atf,lf-6.6.23-2.0.0)/atf-lf-6.6.23-2.0.0.tar.gz" +BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL_LOCATION="$(call github,nxp-qoriq,atf,lf-6.6.36-2.1.0)/atf-lf-6.6.36-2.1.0.tar.gz" BR2_TARGET_ARM_TRUSTED_FIRMWARE_PLATFORM="ls1046afrwy" BR2_TARGET_ARM_TRUSTED_FIRMWARE_FIP=y BR2_TARGET_ARM_TRUSTED_FIRMWARE_UBOOT_AS_BL33=y @@ -35,7 +35,7 @@ BR2_TARGET_ARM_TRUSTED_FIRMWARE_IMAGES="fip.bin bl2_sd.pbl" BR2_TARGET_UBOOT=y BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y BR2_TARGET_UBOOT_CUSTOM_TARBALL=y -BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="$(call github,nxp-qoriq,u-boot,lf-6.6.23-2.0.0)/u-boot-lf-6.6.23-2.0.0.tar.gz" +BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="$(call github,nxp-qoriq,u-boot,lf-6.6.36-2.1.0)/u-boot-lf-6.6.36-2.1.0.tar.gz" BR2_TARGET_UBOOT_BOARD_DEFCONFIG="ls1046afrwy_tfa" BR2_TARGET_UBOOT_NEEDS_DTC=y BR2_PACKAGE_HOST_GENIMAGE=y diff --git a/package/fmc/fmc.hash b/package/fmc/fmc.hash index 961ce18ac713..a467e99af842 100644 --- a/package/fmc/fmc.hash +++ b/package/fmc/fmc.hash @@ -1,3 +1,3 @@ # Locally calculated -sha256 a58514816108a16d07307f924ebceb67c7d61709e4449978763fc44ed6e1fc44 fmc-LSDK-21.08.tar.gz +sha256 a58514816108a16d07307f924ebceb67c7d61709e4449978763fc44ed6e1fc44 fmc-lf-6.6.36-2.1.0.tar.gz sha256 f92862ceb95db5492f50a59d7c799c9395b714db88db92d11891dc0233e2ac42 COPYING diff --git a/package/fmc/fmc.mk b/package/fmc/fmc.mk index 4f25545ffd8c..1135b46fe042 100644 --- a/package/fmc/fmc.mk +++ b/package/fmc/fmc.mk @@ -4,7 +4,7 @@ # ################################################################################ -FMC_VERSION = LSDK-21.08 +FMC_VERSION = lf-6.6.36-2.1.0 FMC_SITE = $(call github,nxp-qoriq,fmc,$(FMC_VERSION)) FMC_LICENSE = MIT FMC_LICENSE_FILES = COPYING diff --git a/package/fmlib/fmlib.hash b/package/fmlib/fmlib.hash index f81b017869c3..034c44c5e10e 100644 --- a/package/fmlib/fmlib.hash +++ b/package/fmlib/fmlib.hash @@ -1,3 +1,3 @@ # Locally computed -sha256 64dc76c0adc3aa58bce6aba470dee7dee001d4964ccb1958e899a59d9917b21d fmlib-LSDK-21.08.tar.gz +sha256 64dc76c0adc3aa58bce6aba470dee7dee001d4964ccb1958e899a59d9917b21d fmlib-lf-6.6.36-2.1.0.tar.gz sha256 5d7770fa9f70f0c6f0b4784bbca8401811259a4b1e03455dbd863ffd0d34d2ca COPYING diff --git a/package/fmlib/fmlib.mk b/package/fmlib/fmlib.mk index 3d185979d51e..2682d0683cc8 100644 --- a/package/fmlib/fmlib.mk +++ b/package/fmlib/fmlib.mk @@ -4,7 +4,7 @@ # ################################################################################ -FMLIB_VERSION = LSDK-21.08 +FMLIB_VERSION = lf-6.6.36-2.1.0 FMLIB_SITE = $(call github,nxp-qoriq,fmlib,$(FMLIB_VERSION)) FMLIB_LICENSE = BSD-3-Clause FMLIB_LICENSE_FILES = COPYING diff --git a/package/qoriq-cadence-dp-firmware/qoriq-cadence-dp-firmware.hash b/package/qoriq-cadence-dp-firmware/qoriq-cadence-dp-firmware.hash index 6e5c761463d9..eb6579b919c9 100644 --- a/package/qoriq-cadence-dp-firmware/qoriq-cadence-dp-firmware.hash +++ b/package/qoriq-cadence-dp-firmware/qoriq-cadence-dp-firmware.hash @@ -1,5 +1,5 @@ # Locally calculated -sha256 e267655a47fbe118f6960bca7994bd6b8986ef955344fe006a424be96f868602 firmware-cadence-lsdk2012.bin +sha256 65f829a9e2597bffc58a680aaefa638122144a083633d1ae09b3aec1d9f8ab84 firmware-imx-8.16.bin sha256 9c16421e7c702f56756650b8ac954d34556327e598a8666e6e8f4eb3a1aa95f1 COPYING sha256 72edc2072c86d93aa1993d15d4d19d96270af3749b0108995ad50c81d1461f52 EULA sha256 53e3eb0b2bd81c171fa04c17514e20b39b7bb1fe1224c593f7717f615fb9d52b EULA.txt diff --git a/package/qoriq-cadence-dp-firmware/qoriq-cadence-dp-firmware.mk b/package/qoriq-cadence-dp-firmware/qoriq-cadence-dp-firmware.mk index 4f75287269a3..04e3a2a6d9ee 100644 --- a/package/qoriq-cadence-dp-firmware/qoriq-cadence-dp-firmware.mk +++ b/package/qoriq-cadence-dp-firmware/qoriq-cadence-dp-firmware.mk @@ -4,9 +4,9 @@ # ################################################################################ -QORIQ_CADENCE_DP_FIRMWARE_VERSION = lsdk2012 -QORIQ_CADENCE_DP_FIRMWARE_SITE = http://www.nxp.com/lgfiles/sdk/$(QORIQ_CADENCE_DP_FIRMWARE_VERSION) -QORIQ_CADENCE_DP_FIRMWARE_SOURCE = firmware-cadence-$(QORIQ_CADENCE_DP_FIRMWARE_VERSION).bin +QORIQ_CADENCE_DP_FIRMWARE_VERSION = 8.16 +QORIQ_CADENCE_DP_FIRMWARE_SITE = https://www.nxp.com/lgfiles/NMG/MAD/YOCTO +QORIQ_CADENCE_DP_FIRMWARE_SOURCE = firmware-imx-$(QORIQ_CADENCE_DP_FIRMWARE_VERSION).bin QORIQ_CADENCE_DP_FIRMWARE_LICENSE = NXP Semiconductor Software License Agreement QORIQ_CADENCE_DP_FIRMWARE_LICENSE_FILES = COPYING EULA EULA.txt QORIQ_CADENCE_DP_FIRMWARE_REDISTRIBUTE = NO @@ -20,11 +20,11 @@ define QORIQ_CADENCE_DP_FIRMWARE_EXTRACT_CMDS endef define QORIQ_CADENCE_DP_FIRMWARE_INSTALL_TARGET_CMDS - $(INSTALL) -D -m 0644 $(@D)/dp/ls1028a-dp-fw.bin $(TARGET_DIR)/boot/ls1028a-dp-fw.bin + $(INSTALL) -D -m 0644 $(@D)/firmware/hdmi/cadence/dp_ls1028a.bin $(TARGET_DIR)/boot/ls1028a-dp-fw.bin endef define QORIQ_CADENCE_DP_FIRMWARE_INSTALL_IMAGES_CMDS - $(INSTALL) -D -m 0644 $(@D)/dp/ls1028a-dp-fw.bin $(BINARIES_DIR)/ls1028a-dp-fw.bin + $(INSTALL) -D -m 0644 $(@D)/firmware/hdmi/cadence/dp_ls1028a.bin $(BINARIES_DIR)/ls1028a-dp-fw.bin endef $(eval $(generic-package)) diff --git a/package/qoriq-fm-ucode/qoriq-fm-ucode.hash b/package/qoriq-fm-ucode/qoriq-fm-ucode.hash index 67efd675cc26..ba284664ab25 100644 --- a/package/qoriq-fm-ucode/qoriq-fm-ucode.hash +++ b/package/qoriq-fm-ucode/qoriq-fm-ucode.hash @@ -1,3 +1,3 @@ # Locally calculated -sha256 c994367c74dd2ff6cd70ea269cf1bc775c5f4e11294a8db414491ce6c2eb9dc3 qoriq-fm-ucode-lf-6.6.23-2.0.0.tar.gz +sha256 2c6b69c34cf689178f8ee7db312c1bfd0e5e4d12dfe1e7f097ab35212f7776b0 qoriq-fm-ucode-lf-6.6.36-2.1.0.tar.gz sha256 7a223031d76339df0e4e5a94d193a270fb9963d42b577aa42fe130a4657f3e17 LICENSE diff --git a/package/qoriq-fm-ucode/qoriq-fm-ucode.mk b/package/qoriq-fm-ucode/qoriq-fm-ucode.mk index 84360533eb1d..1718b1566730 100644 --- a/package/qoriq-fm-ucode/qoriq-fm-ucode.mk +++ b/package/qoriq-fm-ucode/qoriq-fm-ucode.mk @@ -4,7 +4,7 @@ # ################################################################################ -QORIQ_FM_UCODE_VERSION = lf-6.6.23-2.0.0 +QORIQ_FM_UCODE_VERSION = lf-6.6.36-2.1.0 QORIQ_FM_UCODE_SITE = $(call github,nxp-qoriq,qoriq-fm-ucode,$(QORIQ_FM_UCODE_VERSION)) QORIQ_FM_UCODE_LICENSE = NXP Binary EULA QORIQ_FM_UCODE_LICENSE_FILES = LICENSE diff --git a/package/qoriq-rcw/qoriq-rcw.hash b/package/qoriq-rcw/qoriq-rcw.hash index 1f664842f5ea..876733c39a19 100644 --- a/package/qoriq-rcw/qoriq-rcw.hash +++ b/package/qoriq-rcw/qoriq-rcw.hash @@ -1,3 +1,3 @@ # Locally calculated -sha256 52dfb95a3d8e811609dd8a982a5c6f3ba88fac096ea8448a27b571b7c25e3a83 qoriq-rcw-lf-6.6.23-2.0.0.tar.gz +sha256 ed952fa73b290cff67603aeb6a37970d69ea56b66656f002f531912782416a35 qoriq-rcw-lf-6.6.36-2.1.0.tar.gz sha256 68f4b15ecc085729419bc60ca6eeadca5af0237bbfec791e8a79da9c943d42e9 LICENSE diff --git a/package/qoriq-rcw/qoriq-rcw.mk b/package/qoriq-rcw/qoriq-rcw.mk index c6cfe59a5629..1acf5758a0ab 100644 --- a/package/qoriq-rcw/qoriq-rcw.mk +++ b/package/qoriq-rcw/qoriq-rcw.mk @@ -4,7 +4,7 @@ # ################################################################################ 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dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=fCbHkk8V Subject: [Buildroot] [PATCH v2 02/11] package/qoriq-ddr-phy-binary: new package X-BeenThere: buildroot@buildroot.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: buildroot-bounces@buildroot.org Sender: "buildroot" The DDR PHY on the NXP LX2160A SoC needs firmware. This is distributed as prebuilt binaries by NXP through GitHub. Signed-off-by: Vladimir Oltean Reviewed-by: Romain Naour Reviewed-by: Vincent Jardin --- v1->v2: none DEVELOPERS | 3 +++ package/Config.in | 1 + package/qoriq-ddr-phy-binary/Config.in | 6 ++++++ .../qoriq-ddr-phy-binary.hash | 3 +++ .../qoriq-ddr-phy-binary.mk | 18 ++++++++++++++++++ 5 files changed, 31 insertions(+) create mode 100644 package/qoriq-ddr-phy-binary/Config.in create mode 100644 package/qoriq-ddr-phy-binary/qoriq-ddr-phy-binary.hash create mode 100644 package/qoriq-ddr-phy-binary/qoriq-ddr-phy-binary.mk diff --git a/DEVELOPERS b/DEVELOPERS index aedd73677257..0260fc52e4e3 100644 --- a/DEVELOPERS +++ b/DEVELOPERS @@ -3301,6 +3301,9 @@ N: Vivien Didelot F: board/technologic/ts5500/ F: configs/ts5500_defconfig +N: Vladimir Oltean +F: package/qoriq-ddr-phy-binary/ + N: Volkov Viacheslav F: package/v4l2grab/ F: package/zbar/ diff --git a/package/Config.in b/package/Config.in index 1eb5e1e0208f..53e3170ea0f6 100644 --- a/package/Config.in +++ b/package/Config.in @@ -454,6 +454,7 @@ menu "Firmware" source "package/murata-cyw-fw/Config.in" source "package/odroidc2-firmware/Config.in" source "package/qcom-db410c-firmware/Config.in" + source "package/qoriq-ddr-phy-binary/Config.in" source "package/qoriq-fm-ucode/Config.in" source "package/rcw-smarc-sal28/Config.in" source "package/rpi-firmware/Config.in" diff --git a/package/qoriq-ddr-phy-binary/Config.in b/package/qoriq-ddr-phy-binary/Config.in new file mode 100644 index 000000000000..301a2c197421 --- /dev/null +++ b/package/qoriq-ddr-phy-binary/Config.in @@ -0,0 +1,6 @@ +config BR2_PACKAGE_QORIQ_DDR_PHY_BINARY + bool "qoriq-ddr-phy-binary" + help + Firmware binary for DDR PHY of NXP LX2160A family of SoCs. + + https://github.com/nxp-qoriq/ddr-phy-binary diff --git a/package/qoriq-ddr-phy-binary/qoriq-ddr-phy-binary.hash b/package/qoriq-ddr-phy-binary/qoriq-ddr-phy-binary.hash new file mode 100644 index 000000000000..7357e741fcfa --- /dev/null +++ b/package/qoriq-ddr-phy-binary/qoriq-ddr-phy-binary.hash @@ -0,0 +1,3 @@ +# Locally calculated +sha256 b49cb34f941f7e534ec31d3d14d18d4e565e4875b690ecb0d7e2992b72c64dc7 qoriq-ddr-phy-binary-lf-6.6.36-2.1.0.tar.gz +sha256 7a223031d76339df0e4e5a94d193a270fb9963d42b577aa42fe130a4657f3e17 NXP-Binary-EULA.txt diff --git a/package/qoriq-ddr-phy-binary/qoriq-ddr-phy-binary.mk b/package/qoriq-ddr-phy-binary/qoriq-ddr-phy-binary.mk new file mode 100644 index 000000000000..ab25ff541d9c --- /dev/null +++ b/package/qoriq-ddr-phy-binary/qoriq-ddr-phy-binary.mk @@ -0,0 +1,18 @@ +################################################################################ +# +# qoriq-ddr-phy-binary +# +################################################################################ + +QORIQ_DDR_PHY_BINARY_VERSION = lf-6.6.36-2.1.0 +QORIQ_DDR_PHY_BINARY_SITE = $(call github,nxp-qoriq,ddr-phy-binary,$(QORIQ_DDR_PHY_BINARY_VERSION)) +QORIQ_DDR_PHY_BINARY_LICENSE = NXP Binary EULA +QORIQ_DDR_PHY_BINARY_LICENSE_FILES = NXP-Binary-EULA.txt +QORIQ_DDR_PHY_BINARY_INSTALL_IMAGES = YES +QORIQ_DDR_PHY_BINARY_INSTALL_TARGET = NO + +define QORIQ_DDR_PHY_BINARY_INSTALL_IMAGES_CMDS + $(INSTALL) -D $(@D)/lx2160a/fip_ddr.bin $(BINARIES_DIR)/fip_ddr.bin +endef + +$(eval $(generic-package)) From patchwork Sun Dec 8 14:37:54 2024 Content-Type: text/plain; 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dmarc=pass (p=none dis=none) header.from=gmail.com X-Mailman-Original-Authentication-Results: smtp2.osuosl.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=SjrxBpNx Subject: [Buildroot] [PATCH v2 03/11] package/qoriq-mc-binary: new package X-BeenThere: buildroot@buildroot.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: buildroot-bounces@buildroot.org Sender: "buildroot" Add a package which deploys the NXP MC (Management Complex) firmware to the target. This is necessary for NXP DPAA2 SoCs (LS1088A, LS2080A, LS2088A, LX2160A). Signed-off-by: Vladimir Oltean --- v1->v2: none DEVELOPERS | 1 + package/Config.in | 1 + package/qoriq-mc-binary/Config.in | 48 ++++++++++++++++++++ package/qoriq-mc-binary/qoriq-mc-binary.hash | 3 ++ package/qoriq-mc-binary/qoriq-mc-binary.mk | 22 +++++++++ 5 files changed, 75 insertions(+) create mode 100644 package/qoriq-mc-binary/Config.in create mode 100644 package/qoriq-mc-binary/qoriq-mc-binary.hash create mode 100644 package/qoriq-mc-binary/qoriq-mc-binary.mk diff --git a/DEVELOPERS b/DEVELOPERS index 0260fc52e4e3..68c8af0ddc15 100644 --- a/DEVELOPERS +++ b/DEVELOPERS @@ -3303,6 +3303,7 @@ F: configs/ts5500_defconfig N: Vladimir Oltean F: package/qoriq-ddr-phy-binary/ +F: package/qoriq-mc-binary/ N: Volkov Viacheslav F: package/v4l2grab/ diff --git a/package/Config.in b/package/Config.in index 53e3170ea0f6..36337834f284 100644 --- a/package/Config.in +++ b/package/Config.in @@ -456,6 +456,7 @@ menu "Firmware" source "package/qcom-db410c-firmware/Config.in" source "package/qoriq-ddr-phy-binary/Config.in" source "package/qoriq-fm-ucode/Config.in" + source "package/qoriq-mc-binary/Config.in" source "package/rcw-smarc-sal28/Config.in" source "package/rpi-firmware/Config.in" source "package/sunxi-boards/Config.in" diff --git a/package/qoriq-mc-binary/Config.in b/package/qoriq-mc-binary/Config.in new file mode 100644 index 000000000000..fa0983759082 --- /dev/null +++ b/package/qoriq-mc-binary/Config.in @@ -0,0 +1,48 @@ +config BR2_PACKAGE_QORIQ_MC_BINARY + bool "qoriq-mc-binary" + help + The Management Complex (MC) is a key component of the networking + subsystem named DPAA2 (Data Path Acceleration Architecture, second + version) in some NXP Layerscape SoCs. + + The MC coprocessor runs a closed-source, NXP-supplied firmware image + that abstracts and simplifies the allocation and configuration of the + networking hardware primitives into DPAA2 "objects". The MC firmware + exclusively manages the networking control path, and not the data path. + + https://github.com/nxp-qoriq/qoriq-mc-binary + https://www.nxp.com/webapp/Download?colCode=DPAA2UM # sign in required + +if BR2_PACKAGE_QORIQ_MC_BINARY +choice + prompt "QorIQ MC Target" + help + Select the target for the QorIQ MC firmware. + +config BR2_PACKAGE_QORIQ_MC_TARGET_LS1088A + bool "ls1088a" + +config BR2_PACKAGE_QORIQ_MC_TARGET_LS2080A + bool "ls2080a" + +config BR2_PACKAGE_QORIQ_MC_TARGET_LS2088A + bool "ls2088a" + +config BR2_PACKAGE_QORIQ_MC_TARGET_LX2160A + bool "lx2160a" + +endchoice + +config BR2_QORIQ_MC_PLATFORM + string + default "ls1088a" if BR2_PACKAGE_QORIQ_MC_TARGET_LS1088A + default "ls2080a" if BR2_PACKAGE_QORIQ_MC_TARGET_LS2080A + default "ls2088a" if BR2_PACKAGE_QORIQ_MC_TARGET_LS2088A + default "lx2160a" if BR2_PACKAGE_QORIQ_MC_TARGET_LX2160A + +config BR2_QORIQ_MC_DIR + string + default "lx216xa" if BR2_PACKAGE_QORIQ_MC_TARGET_LX2160A + default BR2_QORIQ_MC_PLATFORM + +endif diff --git a/package/qoriq-mc-binary/qoriq-mc-binary.hash b/package/qoriq-mc-binary/qoriq-mc-binary.hash new file mode 100644 index 000000000000..7afa62183c6c --- /dev/null +++ b/package/qoriq-mc-binary/qoriq-mc-binary.hash @@ -0,0 +1,3 @@ +# Locally calculated +sha256 912ad8effd5c7b08eb277719b1e021b8b1fe4022dc3d961b419562e1d2d7a860 qoriq-mc-binary-10.39.0.tar.gz +sha256 7a223031d76339df0e4e5a94d193a270fb9963d42b577aa42fe130a4657f3e17 LICENSE diff --git a/package/qoriq-mc-binary/qoriq-mc-binary.mk b/package/qoriq-mc-binary/qoriq-mc-binary.mk new file mode 100644 index 000000000000..21f9468e7c45 --- /dev/null +++ b/package/qoriq-mc-binary/qoriq-mc-binary.mk @@ -0,0 +1,22 @@ +################################################################################ +# +# qoriq-mc-binary +# +################################################################################ + +QORIQ_MC_BINARY_VERSION = 10.39.0 +QORIQ_MC_BINARY_SITE = $(call github,nxp-qoriq,qoriq-mc-binary,mc_release_$(QORIQ_MC_BINARY_VERSION)) +QORIQ_MC_BINARY_LICENSE = NXP Binary EULA +QORIQ_MC_BINARY_LICENSE_FILES = LICENSE +QORIQ_MC_BINARY_INSTALL_IMAGES = YES +QORIQ_MC_BINARY_INSTALL_TARGET = NO + +MC_PLATFORM = $(call qstrip,$(BR2_QORIQ_MC_PLATFORM)) +MC_DIR = $(call qstrip,$(BR2_QORIQ_MC_DIR)) +MC_BIN = mc_$(MC_PLATFORM)_$(QORIQ_MC_BINARY_VERSION).itb + +define QORIQ_MC_BINARY_INSTALL_IMAGES_CMDS + $(INSTALL) -D $(@D)/${MC_DIR}/${MC_BIN} $(BINARIES_DIR)/mc.itb +endef + +$(eval $(generic-package)) From patchwork Sun Dec 8 14:37:55 2024 Content-Type: text/plain; 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Sun, 08 Dec 2024 06:38:29 -0800 (PST) Received: from skbuf.lan ([86.127.124.81]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa666cf5743sm204660366b.65.2024.12.08.06.38.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Dec 2024 06:38:28 -0800 (PST) From: Vladimir Oltean To: buildroot@buildroot.org Cc: Brandon Maier , Rabeeh Khoury , Josua Mayer , Ioana Ciornei Date: Sun, 8 Dec 2024 16:37:55 +0200 Message-ID: <20241208143802.1048266-5-olteanv@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241208143802.1048266-1-olteanv@gmail.com> References: <20241208143802.1048266-1-olteanv@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1733668709; x=1734273509; darn=buildroot.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QzacwWNkIb2TlKDI34zEAKqLPu/oPCxJVUafJ6+whQM=; b=UAIlhhArifytjPON22AlAKSQLoY0oUjKEZLuju+6HU/yWllm/A1f6Gcki6zgeZjPNM WivHtHpcEacuDxf/LUVkzlnA+YYZ8/hwGH7fmsBWYnlITv3mvmXXUWNsF6h3VBxLVLP9 A6nVMQK3C+JPhV5PyqIBhGKbAOdF5gh031m6ueUfV6bIY7/kBpqJhObhaLyU2684YhD9 ZEctmMWUw2aJdKMSf75tbWyHNy/QgWL67PwEJE9aBzPK3240JN5dvF40dK0BLJW0jwrs DiTrD7OHEeeMIL3vrdATkUTgKe7zHjmQ/83MDi4B5TTT4uNxq8vRj98uI43u+PuIdqwL hiQQ== X-Mailman-Original-Authentication-Results: smtp1.osuosl.org; dmarc=pass (p=none dis=none) header.from=gmail.com X-Mailman-Original-Authentication-Results: smtp1.osuosl.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=UAIlhhAr Subject: [Buildroot] [PATCH v2 04/11] package/qoriq-mc-utils: new package X-BeenThere: buildroot@buildroot.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: buildroot-bounces@buildroot.org Sender: "buildroot" The configuration files for the MC firmware binary are distributed through a separate repository on GitHub, and need a different package. They are licensed differently than the firmware itself, and unlike the firmware, they are customizable. Signed-off-by: Vladimir Oltean --- v1->v2: none DEVELOPERS | 1 + package/Config.in | 1 + package/qoriq-mc-utils/Config.in | 35 ++++++++++++++++++++++ package/qoriq-mc-utils/qoriq-mc-utils.hash | 3 ++ package/qoriq-mc-utils/qoriq-mc-utils.mk | 22 ++++++++++++++ 5 files changed, 62 insertions(+) create mode 100644 package/qoriq-mc-utils/Config.in create mode 100644 package/qoriq-mc-utils/qoriq-mc-utils.hash create mode 100644 package/qoriq-mc-utils/qoriq-mc-utils.mk diff --git a/DEVELOPERS b/DEVELOPERS index 68c8af0ddc15..44628db3bef5 100644 --- a/DEVELOPERS +++ b/DEVELOPERS @@ -3304,6 +3304,7 @@ F: configs/ts5500_defconfig N: Vladimir Oltean F: package/qoriq-ddr-phy-binary/ F: package/qoriq-mc-binary/ +F: package/qoriq-mc-utils/ N: Volkov Viacheslav F: package/v4l2grab/ diff --git a/package/Config.in b/package/Config.in index 36337834f284..52b28871e96d 100644 --- a/package/Config.in +++ b/package/Config.in @@ -457,6 +457,7 @@ menu "Firmware" source "package/qoriq-ddr-phy-binary/Config.in" source "package/qoriq-fm-ucode/Config.in" source "package/qoriq-mc-binary/Config.in" + source "package/qoriq-mc-utils/Config.in" source "package/rcw-smarc-sal28/Config.in" source "package/rpi-firmware/Config.in" source "package/sunxi-boards/Config.in" diff --git a/package/qoriq-mc-utils/Config.in b/package/qoriq-mc-utils/Config.in new file mode 100644 index 000000000000..bb45ffbc9ca7 --- /dev/null +++ b/package/qoriq-mc-utils/Config.in @@ -0,0 +1,35 @@ +config BR2_PACKAGE_QORIQ_MC_UTILS + bool "qoriq-mc-utils" + help + The Management Complex (MC) is a key component of the networking + subsystem named DPAA2 (Data Path Acceleration Architecture, second + version) in some NXP Layerscape SoCs. + + The MC firmware is configured through two distinct files named DPL + and DPC, which are customizable by the end user. Example + configuration files for NXP reference boards are distributed through + this package, and are frequently patched to produce the configuration + required in other scenarios. + + https://github.com/nxp-qoriq/mc-utils + https://www.nxp.com/webapp/Download?colCode=DPAA2UM # sign in required + +if BR2_PACKAGE_QORIQ_MC_UTILS + +config BR2_PACKAGE_QORIQ_MC_UTILS_DPC + string "Data Path Configuration (DPC) file" + help + The DPC file contains the settings defining the behavior of the MC + firmware. Its source code follows the device tree syntax and is + compiled to a device tree blob, which is the file that must be + specified here. + +config BR2_PACKAGE_QORIQ_MC_UTILS_DPL + string "Data Path Layout (DPL) file" + help + The DPL file contains a description of the initial networking objects + created by the MC firmware when it boots. Its source code follows the + device tree syntax and is compiled to a device tree blob, which is + the file that must be specified here. + +endif diff --git a/package/qoriq-mc-utils/qoriq-mc-utils.hash b/package/qoriq-mc-utils/qoriq-mc-utils.hash new file mode 100644 index 000000000000..f0234b9d1ff8 --- /dev/null +++ b/package/qoriq-mc-utils/qoriq-mc-utils.hash @@ -0,0 +1,3 @@ +# Locally calculated +sha256 1d3f4a6b2661cff9cfb5d4fcba3b181eb6febdd88a127fa069e306f51d778fc5 qoriq-mc-utils-10.39.0.tar.gz +sha256 7a223031d76339df0e4e5a94d193a270fb9963d42b577aa42fe130a4657f3e17 LICENSE diff --git a/package/qoriq-mc-utils/qoriq-mc-utils.mk b/package/qoriq-mc-utils/qoriq-mc-utils.mk new file mode 100644 index 000000000000..d4fc5e27385e --- /dev/null +++ b/package/qoriq-mc-utils/qoriq-mc-utils.mk @@ -0,0 +1,22 @@ +################################################################################ +# +# qoriq-mc-utils +# +################################################################################ + +QORIQ_MC_UTILS_VERSION = 10.39.0 +QORIQ_MC_UTILS_SITE = $(call github,nxp-qoriq,mc-utils,mc_release_$(QORIQ_MC_UTILS_VERSION)) +QORIQ_MC_UTILS_LICENSE = BSD-3-Clause +QORIQ_MC_UTILS_INSTALL_IMAGES = YES +QORIQ_MC_UTILS_INSTALL_TARGET = NO + +define QORIQ_MC_UTILS_BUILD_CMDS + $(MAKE) -C $(@D)/config/ +endef + +define QORIQ_MC_UTILS_INSTALL_IMAGES_CMDS + $(INSTALL) -D $(@D)/config/$(call qstrip,$(BR2_PACKAGE_QORIQ_MC_UTILS_DPC)) $(BINARIES_DIR)/dpc.dtb + $(INSTALL) -D $(@D)/config/$(call qstrip,$(BR2_PACKAGE_QORIQ_MC_UTILS_DPL)) $(BINARIES_DIR)/dpl.dtb +endef + +$(eval $(generic-package)) From patchwork Sun Dec 8 14:37:56 2024 Content-Type: text/plain; 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Sun, 08 Dec 2024 06:38:30 -0800 (PST) Received: from skbuf.lan ([86.127.124.81]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa666cf5743sm204660366b.65.2024.12.08.06.38.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Dec 2024 06:38:29 -0800 (PST) From: Vladimir Oltean To: buildroot@buildroot.org Cc: Brandon Maier , Rabeeh Khoury , Josua Mayer , Ioana Ciornei Date: Sun, 8 Dec 2024 16:37:56 +0200 Message-ID: <20241208143802.1048266-6-olteanv@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241208143802.1048266-1-olteanv@gmail.com> References: <20241208143802.1048266-1-olteanv@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1733668711; x=1734273511; darn=buildroot.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zNJWb2aaTnaqFA407nSdAkJEivLbSdkDlpOPA4NnaNc=; b=SQsdsvBX9BFFtHocTYpgvhKy0cmrqWaAXg64bJx8M1LvXBiPY60Y5o178vsIIcIgWj l1hZ+Q2XQMQcbkg838HrhnqLsl4mP9+vnXgirnxjvU6tfI9PsNtgiCLDXowitM80RZzW v4y5/kfzxFZNw+KV2GNV0sHPO8CiVKQ8uNZwR2s6oAvstHQApg6Hgw4c6/7ILzQWeZkY sWWlvxs/0IRW/5YYXSS0EphWfku9HiVlTEfg1u65sqW3Hg9KptFs9vKG7aJ6kFVCVZbQ H+uE3ocyB/HUS+T4MFZ2UjnD5oFQrmgoeJCXoO4eK+Maa/rEDuUID6IiObvmLSyV6Pps hhFw== X-Mailman-Original-Authentication-Results: smtp1.osuosl.org; dmarc=pass (p=none dis=none) header.from=gmail.com X-Mailman-Original-Authentication-Results: smtp1.osuosl.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=SQsdsvBX Subject: [Buildroot] [PATCH v2 05/11] package/qoriq-restool: new package X-BeenThere: buildroot@buildroot.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: buildroot-bounces@buildroot.org Sender: "buildroot" Introduce a package for the restool program, which permits the user to modify the network configuration of the DPAA2 subsystem and create one that is adequate to their use case. Signed-off-by: Vladimir Oltean --- v1->v2: none DEVELOPERS | 1 + package/Config.in | 1 + package/qoriq-restool/Config.in | 21 +++++++++++++++++++++ package/qoriq-restool/qoriq-restool.hash | 3 +++ package/qoriq-restool/qoriq-restool.mk | 24 ++++++++++++++++++++++++ 5 files changed, 50 insertions(+) create mode 100644 package/qoriq-restool/Config.in create mode 100644 package/qoriq-restool/qoriq-restool.hash create mode 100644 package/qoriq-restool/qoriq-restool.mk diff --git a/DEVELOPERS b/DEVELOPERS index 44628db3bef5..dba4bbbb21e6 100644 --- a/DEVELOPERS +++ b/DEVELOPERS @@ -3305,6 +3305,7 @@ N: Vladimir Oltean F: package/qoriq-ddr-phy-binary/ F: package/qoriq-mc-binary/ F: package/qoriq-mc-utils/ +F: package/qoriq-restool/ N: Volkov Viacheslav F: package/v4l2grab/ diff --git a/package/Config.in b/package/Config.in index 52b28871e96d..ddbe41e0ff20 100644 --- a/package/Config.in +++ b/package/Config.in @@ -599,6 +599,7 @@ endmenu source "package/pru-software-support/Config.in" source "package/pulseview/Config.in" source "package/qoriq-cadence-dp-firmware/Config.in" + source "package/qoriq-restool/Config.in" source "package/raspi-gpio/Config.in" source "package/rdma-core/Config.in" source "package/read-edid/Config.in" diff --git a/package/qoriq-restool/Config.in b/package/qoriq-restool/Config.in new file mode 100644 index 000000000000..3f1834a7dce0 --- /dev/null +++ b/package/qoriq-restool/Config.in @@ -0,0 +1,21 @@ +config BR2_PACKAGE_QORIQ_RESTOOL + bool "qoriq-restool" + help + The DPAA2 architecture in Layerscape SoCs consists of + networking resources that can be assembled into various + nuggets of functionality, called "objects" (DPMAC, DPNI, + DPDMUX, DPSW etc), by the Management Complex (MC) firmware. + + The MC firmware reads a file called Data Path Layout (DPL) + which describes the set of networking objects it should + create statically, at boot time. + + The restool program is able to talk to the Management Complex + at runtime and permits the dynamic reconfiguration of + networking objects, as well as saving the current configuration + into a new DPL file. Without the restool program, the only + possible networking configuration is that specified in the + boot-time DPL file. + + https://github.com/nxp-qoriq/restool + https://www.nxp.com/webapp/Download?colCode=DPAA2UM # sign in required diff --git a/package/qoriq-restool/qoriq-restool.hash b/package/qoriq-restool/qoriq-restool.hash new file mode 100644 index 000000000000..c2332d9b27eb --- /dev/null +++ b/package/qoriq-restool/qoriq-restool.hash @@ -0,0 +1,3 @@ +# Locally calculated +sha256 0cfced32caa615266ff633946d40a36660c856d7eb057b81de392570e136c5e5 qoriq-restool-lf-6.6.36-2.1.0.tar.gz +sha256 68f4b15ecc085729419bc60ca6eeadca5af0237bbfec791e8a79da9c943d42e9 LICENSE diff --git a/package/qoriq-restool/qoriq-restool.mk b/package/qoriq-restool/qoriq-restool.mk new file mode 100644 index 000000000000..4a89a80afa70 --- /dev/null +++ b/package/qoriq-restool/qoriq-restool.mk @@ -0,0 +1,24 @@ +############################################################################### +# +# qoriq-restool +# +################################################################################ + +QORIQ_RESTOOL_VERSION = lf-6.6.36-2.1.0 +QORIQ_RESTOOL_SITE = $(call github,nxp-qoriq,restool,$(QORIQ_RESTOOL_VERSION)) +QORIQ_RESTOOL_LICENSE = GPL2.0 +QORIQ_RESTOOL_LICENSE_FILES = COPYING + +QORIQ_RESTOOL_MAKE_OPTS = \ + CC="$(TARGET_CC)" \ + CROSS_COMPILE="$(TARGET_CROSS)" + +define QORIQ_RESTOOL_BUILD_CMDS + cd $(@D) && $(TARGET_MAKE_ENV) $(MAKE) $(QORIQ_RESTOOL_MAKE_OPTS) +endef + +define QORIQ_RESTOOL_INSTALL_TARGET_CMDS + $(TARGET_MAKE_ENV) $(MAKE) -C $(@D) DESTDIR=$(TARGET_DIR) prefix=/usr install +endef + +$(eval $(generic-package)) From patchwork Sun Dec 8 14:37:57 2024 Content-Type: text/plain; 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Sun, 08 Dec 2024 06:38:32 -0800 (PST) Received: from skbuf.lan ([86.127.124.81]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa666cf5743sm204660366b.65.2024.12.08.06.38.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Dec 2024 06:38:31 -0800 (PST) From: Vladimir Oltean To: buildroot@buildroot.org Cc: Brandon Maier , Rabeeh Khoury , Josua Mayer , Ioana Ciornei Date: Sun, 8 Dec 2024 16:37:57 +0200 Message-ID: <20241208143802.1048266-7-olteanv@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241208143802.1048266-1-olteanv@gmail.com> References: <20241208143802.1048266-1-olteanv@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1733668712; x=1734273512; darn=buildroot.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OK7yx0OVneQo71/6W1Mo4/BBwBpGz0Q6okf9hBT5IUc=; b=TdjTR9taZFmtJhL0jaa3X/P8r3RNppbNI6JRIelEu6pkVje8gvFj6WU1nPXW/kHezf rZn/qEptA0XHPqJ5OYVF3L/05uav0aPq17TGs6hK/NLO+rVcC5b34ib4RuRgJlINDSNm m3tMPdXrH/WatD6DslDfSTbJD7MXXwissJ8thP45hCaE9U7AFp1HN3fuxYBoKgqFoeFO b811ey94O7RHwGLxTxNsHd/zd58XynunFBjRk9/TXvFes5bn1+gYwbpo6lOUnjQj4VyO ULL2nrQUqQ5IvvaXPifQHjKgrOXrWfYZKq3DsIH+E7pLViSNm3ouGO0jVK5vnXSQe+OF 5n5A== X-Mailman-Original-Authentication-Results: smtp2.osuosl.org; dmarc=pass (p=none dis=none) header.from=gmail.com X-Mailman-Original-Authentication-Results: smtp2.osuosl.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=TdjTR9ta Subject: [Buildroot] [PATCH v2 06/11] board/lx2160acex7: new platform X-BeenThere: buildroot@buildroot.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: buildroot-bounces@buildroot.org Sender: "buildroot" Introduce the SolidRun LX2160A-CEX7 platform, which uses the NXP LX2160A SoC and much of the infrastructure associated with DPAA2 networking. This defconfig is not functional yet. Patches on various components have been split out to separate changes, to reduce chances of the mailing list flagging emails due to excessive size. More details in board/solidrun/lx2160acex7/readme.txt. Signed-off-by: Vladimir Oltean --- v1->v2: - split out patches on firmware components to separate changes - enable more Kconfig options required for this board in board/solidrun/lx2160acex7/linux.config board/solidrun/lx2160acex7/extlinux.conf | 4 + board/solidrun/lx2160acex7/genimage.cfg | 54 +++++++++ board/solidrun/lx2160acex7/linux.config | 5 + .../arm-trusted-firmware.hash | 2 + .../patches/linux-headers/linux-headers.hash | 1 + .../lx2160acex7/patches/linux/linux.hash | 2 + .../lx2160acex7/patches/uboot/uboot.hash | 2 + board/solidrun/lx2160acex7/post-build.sh | 8 ++ board/solidrun/lx2160acex7/readme.txt | 112 ++++++++++++++++++ .../udev/rules.d/74-dpaa2-networking.rules | 12 ++ .../lx2160acex7/u-boot-environment-sd.txt | 96 +++++++++++++++ configs/solidrun_lx2160acex7_defconfig | 53 +++++++++ 12 files changed, 351 insertions(+) create mode 100644 board/solidrun/lx2160acex7/extlinux.conf create mode 100644 board/solidrun/lx2160acex7/genimage.cfg create mode 100644 board/solidrun/lx2160acex7/linux.config create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/arm-trusted-firmware.hash create mode 120000 board/solidrun/lx2160acex7/patches/linux-headers/linux-headers.hash create mode 100644 board/solidrun/lx2160acex7/patches/linux/linux.hash create mode 100644 board/solidrun/lx2160acex7/patches/uboot/uboot.hash create mode 100755 board/solidrun/lx2160acex7/post-build.sh create mode 100644 board/solidrun/lx2160acex7/readme.txt create mode 100644 board/solidrun/lx2160acex7/rootfs_overlay/etc/udev/rules.d/74-dpaa2-networking.rules create mode 100644 board/solidrun/lx2160acex7/u-boot-environment-sd.txt create mode 100644 configs/solidrun_lx2160acex7_defconfig diff --git a/board/solidrun/lx2160acex7/extlinux.conf b/board/solidrun/lx2160acex7/extlinux.conf new file mode 100644 index 000000000000..018f35a2ec9f --- /dev/null +++ b/board/solidrun/lx2160acex7/extlinux.conf @@ -0,0 +1,4 @@ +label Solidrun LX2160A COM Express Type 7 + kernel /boot/Image + devicetree /boot/fsl-lx2160a-clearfog-cx.dtb + append root=PARTUUID=%PARTUUID% rw rootwait cma=256M diff --git a/board/solidrun/lx2160acex7/genimage.cfg b/board/solidrun/lx2160acex7/genimage.cfg new file mode 100644 index 000000000000..8a1be0e466e0 --- /dev/null +++ b/board/solidrun/lx2160acex7/genimage.cfg @@ -0,0 +1,54 @@ +image sdcard.img { + hdimage { + partition-table-type = "gpt" + gpt-location = 6M + } + + partition rcw { + offset = 4K + in-partition-table = "no" + image = "bl2_sd.pbl" + } + + partition u-boot { + offset = 1M + in-partition-table = "no" + image = "fip.bin" + } + + partition u-boot-environment { + in-partition-table = "no" + image = "uboot-env.bin" + offset = 5M + } + + partition ddr-phy { + in-partition-table = "no" + image = "fip_ddr.bin" + offset = 8M + } + + partition dpaa2-mc { + in-partition-table = "no" + image = "mc.itb" + offset = 10M + } + + partition dpaa2-dpl { + in-partition-table = "no" + image = "dpl.dtb" + offset = 13M + } + + partition dpaa2-dpc { + in-partition-table = "no" + image = "dpc.dtb" + offset = 14M + } + + partition rootfs { + bootable = "true" + image = "rootfs.ext4" + partition-uuid = %PARTUUID% + } +} diff --git a/board/solidrun/lx2160acex7/linux.config b/board/solidrun/lx2160acex7/linux.config new file mode 100644 index 000000000000..8b8ad7369278 --- /dev/null +++ b/board/solidrun/lx2160acex7/linux.config @@ -0,0 +1,5 @@ +CONFIG_BLK_DEV_NVME=y +CONFIG_PMBUS=y +CONFIG_SENSORS_AMC6821=y +CONFIG_SENSORS_LTC2978=y +CONFIG_SENSORS_LTC2978_REGULATOR=y diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/arm-trusted-firmware.hash b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/arm-trusted-firmware.hash new file mode 100644 index 000000000000..713195e67fb5 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/arm-trusted-firmware.hash @@ -0,0 +1,2 @@ +# Locally computed +sha256 3f7a1239b8a6be011bf85286f37c333110b5404f0711ab85d66f3b1864c9fc65 atf-lf-5.15.71-2.2.0.tar.gz diff --git a/board/solidrun/lx2160acex7/patches/linux-headers/linux-headers.hash b/board/solidrun/lx2160acex7/patches/linux-headers/linux-headers.hash new file mode 120000 index 000000000000..5808d92afe89 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/linux-headers/linux-headers.hash @@ -0,0 +1 @@ +../linux/linux.hash \ No newline at end of file diff --git a/board/solidrun/lx2160acex7/patches/linux/linux.hash b/board/solidrun/lx2160acex7/patches/linux/linux.hash new file mode 100644 index 000000000000..bfdc2c268d2d --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/linux/linux.hash @@ -0,0 +1,2 @@ +# Locally computed +sha256 26e0db3dda786d939269f85df0f605e28cb55646ab8c541fc9bbbb4ab7fd9bf3 linux-lf-6.6.36-2.1.0.tar.gz diff --git a/board/solidrun/lx2160acex7/patches/uboot/uboot.hash b/board/solidrun/lx2160acex7/patches/uboot/uboot.hash new file mode 100644 index 000000000000..c2dbfcdc8755 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/uboot/uboot.hash @@ -0,0 +1,2 @@ +# Locally computed +sha256 3244dd3ae1d1d18ac683e2efc9353d92b496c4b163706b8ea0035344e06554a3 u-boot-lf-5.15.71-2.2.0.tar.gz diff --git a/board/solidrun/lx2160acex7/post-build.sh b/board/solidrun/lx2160acex7/post-build.sh new file mode 100755 index 000000000000..0602fa576219 --- /dev/null +++ b/board/solidrun/lx2160acex7/post-build.sh @@ -0,0 +1,8 @@ +#!/bin/sh + +BOARD_DIR="$(dirname $0)" +PARTUUID="$($HOST_DIR/bin/uuidgen)" + +install -d "$TARGET_DIR/boot/extlinux/" +sed "s/%PARTUUID%/$PARTUUID/g" "$BOARD_DIR/extlinux.conf" > "$TARGET_DIR/boot/extlinux/extlinux.conf" +sed "s/%PARTUUID%/$PARTUUID/g" "$BOARD_DIR/genimage.cfg" > "$BINARIES_DIR/genimage.cfg" diff --git a/board/solidrun/lx2160acex7/readme.txt b/board/solidrun/lx2160acex7/readme.txt new file mode 100644 index 000000000000..17c650c4c0be --- /dev/null +++ b/board/solidrun/lx2160acex7/readme.txt @@ -0,0 +1,112 @@ +********************* +SolidRun LX2160A-CEx7 +********************* + +This file documents the Buildroot support for the NXP Layerscape CEx7 LX2160A +board made by SolidRun. The CEx7 (COM Express type 7) is a Computer On Module +which can be plugged into different carrier boards. It is sold either +separately, or with the HoneyComb LX2 or Clearfog CX LX2 carrier boards, both +having Mini ITX form factors. + +Both the HoneyComb LX2 and Clearfog CX LX2 carrier boards are targeted towards +networking use cases, with 4 10G-capable SFP+ cages, and the Clearfog +additionally having a 4x25G-capable QSFP28 cage. In addition, the carrier +boards have 4x SATA III interfaces, PCIe Gen 3 x8, 2x USB 3.0, an m.2 slot +compatible with NVMe SSDs, pin headers for traditional PC/NAS cases, and +regular RJ45 1G Ethernet. + +The developer resources for the platform can be found at: + - https://solidrun.atlassian.net/wiki/spaces/developer/pages/197493977/NXP+LX2160A+Based+Products + +SolidRun keeps build scripts for the firmware on GitHub, which track NXP Linux +Factory (LF) releases in the form of patches: + - https://github.com/SolidRun/lx2160a_build + +The most recent functional branch is develop-ls-5.15.71-2.2.0. These patches +are also included into Buildroot, except for the Linux kernel, where the most +recent lf-6.6.36-2.1.0 NXP tag is used directly. + +The Buildroot support is for the maximal configuration, which is the CEX7 +platform on the Clearfog CX LX2 carrier board. + +Build +===== + +First, configure Buildroot for the LX2160A-CEX7 platform: + + make solidrun_lx2160acex7_defconfig + +Build all components: + + make + +You will find in output/images/ the following files: + - bl2_sd.pbl - RCW + ATF BL2 stage + - dpc.dtb + - dpl.dtb + - fip.bin - U-Boot packaged as ATF payload + - fip_ddr.bin - DDR PHY firmware + - fsl-lx2160a-clearfog-cx.dtb + - fsl-lx2160a-honeycomb.dtb + - Image + - mc.itb - MC firmware + - PBL.bin + - rootfs.ext2 + - rootfs.ext4 + - sdcard.img + - u-boot.bin + - uboot-env.bin + +Create a bootable SD card +========================= + +To determine the device associated to the SD card have a look in the +/proc/partitions file: + + cat /proc/partitions + +Buildroot prepares a bootable "sdcard.img" image in the output/images/ +directory, ready to be dumped on a SD card. Launch the following +command as root: + + dd if=output/images/sdcard.img of=/dev/sdX + +*** WARNING! This will destroy all the card content. Use with care! *** + +For details about the medium image layout, see the definition in +board/solidrun/lx2160acex7/genimage.cfg. + +Boot the LX2160A-CEX7 board +=========================== + +To boot your newly created system: +- configure the DIP switches for SD boot selection as per SolidRun instructions: + https://solidrun.atlassian.net/wiki/spaces/developer/pages/197494288/HoneyComb+LX2+ClearFog+CX+LX2+Quick+Start+Guide#Boot-Select +- insert the Micro-SD card in the Micro-SD slot of the board +- put a Micro-USB cable into the Micro-USB connector labeled CONSOLE (CON9) + and connect using a terminal emulator at 115200 bps, 8n1. +- power on the board. + +The DPL file only contains a static description for the 1G RGMII RJ45 port +(endpmac17). By default, this will attempt acquire an IP address over DHCP. + +The 4 interfaces routed to the SFP+ cages are endpmac7, endpmac8, endpmac9 and +endpmac10. Among the more usual networking choices, one could create individual +DPNIs for each MAC: + +$ ls-addni dpmac.7 && ls-addni dpmac.8 && ls-addni dpmac.9 && ls-addni dpmac.10 + +or a DPSW object to accelerate L2 forwarding between them: + +$ ls-addsw --num-ifs=4 --max-fdbs=4 --flooding-cfg=DPSW_FLOODING_PER_FDB \ + --broadcast-cfg=DPSW_BROADCAST_PER_FDB dpmac.7 dpmac.8 dpmac.9 dpmac.10 +$ ip link add br0 type bridge vlan_filtering 1 && ip link set br0 up +$ for eth in endpmac7 endpmac8 endpmac9 endpmac10; do \ + ip link set $eth master br0 && ip link set $eth up; done + +Once the runtime configuration is satisfactory, it can be converted back into a +permanent DPL file which can be plugged back into the build system: + +$ restool dprc generate-dpl > dpl-new.dts + +Networking options through the QSFP28 cage have not yet been investigated. diff --git a/board/solidrun/lx2160acex7/rootfs_overlay/etc/udev/rules.d/74-dpaa2-networking.rules b/board/solidrun/lx2160acex7/rootfs_overlay/etc/udev/rules.d/74-dpaa2-networking.rules new file mode 100644 index 000000000000..3c6f6999ecc7 --- /dev/null +++ b/board/solidrun/lx2160acex7/rootfs_overlay/etc/udev/rules.d/74-dpaa2-networking.rules @@ -0,0 +1,12 @@ +SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc@80c000000/dpmacs/ethernet@1", NAME="endpmac1" +SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc@80c000000/dpmacs/ethernet@2", NAME="endpmac2" +SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc@80c000000/dpmacs/ethernet@3", NAME="endpmac3" +SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc@80c000000/dpmacs/ethernet@4", NAME="endpmac4" +SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc@80c000000/dpmacs/ethernet@5", NAME="endpmac5" +SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc@80c000000/dpmacs/ethernet@6", NAME="endpmac6" +SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc@80c000000/dpmacs/ethernet@7", NAME="endpmac7" +SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc@80c000000/dpmacs/ethernet@8", NAME="endpmac8" +SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc@80c000000/dpmacs/ethernet@9", NAME="endpmac9" +SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc@80c000000/dpmacs/ethernet@a", NAME="endpmac10" +SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc@80c000000/dpmacs/ethernet@11", NAME="endpmac17" +SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc@80c000000/dpmacs/ethernet@12", NAME="endpmac18" diff --git a/board/solidrun/lx2160acex7/u-boot-environment-sd.txt b/board/solidrun/lx2160acex7/u-boot-environment-sd.txt new file mode 100644 index 000000000000..e5041fe6a210 --- /dev/null +++ b/board/solidrun/lx2160acex7/u-boot-environment-sd.txt @@ -0,0 +1,96 @@ +BOARD=lx2160acex7 +arch=arm +baudrate=115200 +board=lx2160a +board_name=lx2160a +boot_a_script=load ${devtype} ${devnum}:${distro_bootpart} ${scriptaddr} ${prefix}${script}; env exists secureboot && load ${devtype} ${devnum}:${distro_bootpart} ${scripthdraddr} ${prefix}${boot_script_hdr} && esbc_validate ${scripthdraddr};source ${scriptaddr} +boot_efi_binary=load ${devtype} ${devnum}:${distro_bootpart} ${kernel_addr_r} efi/boot/bootaa64.efi; if fdt addr ${fdt_addr_r}; then bootefi ${kernel_addr_r} ${fdt_addr_r};else bootefi ${kernel_addr_r} ${fdtcontroladdr};fi +boot_efi_bootmgr=if fdt addr ${fdt_addr_r}; then bootefi bootmgr ${fdt_addr_r};else bootefi bootmgr;fi +boot_extlinux=sysboot ${devtype} ${devnum}:${distro_bootpart} any ${scriptaddr} ${prefix}${boot_syslinux_conf} +boot_net_usb_start=usb start +boot_pci_enum=pci enum +boot_prefixes=/ /boot/ +boot_script_dhcp=boot.scr.uimg +boot_scripts=boot.scr.uimg boot.scr +boot_syslinux_conf=extlinux/extlinux.conf +boot_targets=usb0 mmc0 mmc1 scsi0 nvme0 dhcp +bootargs=console=ttyAMA0,115200 earlycon=pl011,mmio32,0x21c0000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf cma=256M iommu.passthrough=1 arm-smmu.disable_bypass=0 +bootcmd=run distro_bootcmd +bootcmd_dhcp=setenv devtype dhcp; run boot_net_usb_start; run boot_pci_enum; if dhcp ${scriptaddr} ${boot_script_dhcp}; then source ${scriptaddr}; fi;setenv efi_fdtfile ${fdtfile}; setenv efi_old_vci ${bootp_vci};setenv efi_old_arch ${bootp_arch};setenv bootp_vci PXEClient:Arch:00011:UNDI:003000;setenv bootp_arch 0xb;if dhcp ${kernel_addr_r}; then tftpboot ${fdt_addr_r} dtb/${efi_fdtfile};if fdt addr ${fdt_addr_r}; then bootefi ${kernel_addr_r} ${fdt_addr_r}; else bootefi ${kernel_addr_r} ${fdtcontroladdr};fi;fi;setenv bootp_vci ${efi_old_vci};setenv bootp_arch ${efi_old_arch};setenv efi_fdtfile;setenv efi_old_arch;setenv efi_old_vci; +bootcmd_mmc0=devnum=0; run mmc_boot +bootcmd_mmc1=devnum=1; run mmc_boot +bootcmd_nvme0=devnum=0; run nvme_boot +bootcmd_scsi0=devnum=0; run scsi_boot +bootcmd_usb0=devnum=0; run usb_boot +bootdelay=3 +console=ttyAMA0,115200 +cpu=armv8 +distro_bootcmd=scsi_need_init=; setenv nvme_need_init; for target in ${boot_targets}; do run bootcmd_${target}; done +efi_dtb_prefixes=/ /dtb/ /dtb/current/ +emmc_bootcmd=echo Trying load from emmc card..;mmc dev 1; mmcinfo; mmc read $load_addr $kernel_addr_sd $kernel_size_sd ;env exists secureboot && mmc read $kernelheader_addr_r $kernelhdr_addr_sd $kernelhdr_size_sd && esbc_validate ${kernelheader_addr_r};bootm $load_addr#$BOARD +eth10addr=00:11:22:44:11:4E +eth11addr=00:11:22:44:11:4F +eth12addr=00:11:22:44:11:50 +eth13addr=00:11:22:44:11:51 +eth14addr=00:11:22:44:11:52 +eth15addr=00:11:22:44:11:53 +eth1addr=00:11:22:44:11:45 +eth2addr=00:11:22:44:11:46 +eth3addr=00:11:22:44:11:47 +eth4addr=00:11:22:44:11:48 +eth5addr=00:11:22:44:11:49 +eth6addr=00:11:22:44:11:4A +eth7addr=00:11:22:44:11:4B +eth8addr=00:11:22:44:11:4C +eth9addr=00:11:22:44:11:4D +ethaddr=00:11:22:44:11:44 +ethprime=DPMAC17@rgmii-id +fdt_addr=0x81000000 +fdt_addr_r=0x81000000 +fdt_high=0xa0000000 +fdtfile=fsl-lx2160a-cex7.dtb +fdtheader_addr_r=0x80100000 +hwconfig=fsl_ddr:bank_intlv=auto +initrd_high=0xffffffffffffffff +kernel_addr_r=0x81100000 +kernel_addr_sd=0x8000 +kernel_comp_addr_r=0x9f000000 +kernel_comp_size=0x10000000 +kernel_size=0x2800000 +kernel_size_sd=0x14000 +kernel_start=0x1000000 +kernelhdr_addr_sd=0x3000 +kernelhdr_size_sd=0x20 +kernelheader_addr_r=0x80200000 +kernelheader_size=0x40000 +kernelheader_start=0x600000 +load_addr=0xa0000000 +load_efi_dtb=load ${devtype} ${devnum}:${distro_bootpart} ${fdt_addr_r} ${prefix}${efi_fdtfile} +lx2160acex7_vdd_mv=800 +dpl_addr_r=0x80d00000 +mc_fw_addr_r=0x80a00000 +dpc_addr_r=0x80e00000 +mcinitcmd=mmcinfo && mmc read $mc_fw_addr_r 0x5000 0x1200 && mmc read $dpc_addr_r 0x7000 0x800 && mmc read $dpl_addr_r 0x6800 0x800 && fsl_mc start mc $mc_fw_addr_r $dpc_addr_r && fsl_mc lazyapply dpl $dpl_addr_r +mcmemsize=0x70000000 +fsl_bootcmd_mcinitcmd_set=y +mmc_boot=if mmc dev ${devnum}; then devtype=mmc; run scan_dev_for_boot_part; fi +nvme_boot=run boot_pci_enum; run nvme_init; if nvme dev ${devnum}; then devtype=nvme; run scan_dev_for_boot_part; fi +nvme_init=if ${nvme_need_init}; then setenv nvme_need_init false; nvme scan; fi +nvme_need_init=true +ramdisk_addr=0x85100000 +ramdisk_addr_r=0x85100000 +ramdisk_size=0x2000000 +scan_dev_for_boot=echo Scanning ${devtype} ${devnum}:${distro_bootpart}...; for prefix in ${boot_prefixes}; do run scan_dev_for_extlinux; run scan_dev_for_scripts; done;run scan_dev_for_efi; +scan_dev_for_boot_part=part list ${devtype} ${devnum} devplist; env exists devplist || setenv devplist 1; for distro_bootpart in ${devplist}; do if fstype ${devtype} ${devnum}:${distro_bootpart} bootfstype; then run scan_dev_for_boot; fi; done +scan_dev_for_efi=setenv efi_fdtfile ${fdtfile}; for prefix in ${efi_dtb_prefixes}; do if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${efi_fdtfile}; then run load_efi_dtb; fi;done;run boot_efi_bootmgr;if test -e ${devtype} ${devnum}:${distro_bootpart} efi/boot/bootaa64.efi; then echo Found EFI removable media binary efi/boot/bootaa64.efi; run boot_efi_binary; echo EFI LOAD FAILED: continuing...; fi; setenv efi_fdtfile +scan_dev_for_extlinux=if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${boot_syslinux_conf}; then echo Found ${prefix}${boot_syslinux_conf}; run boot_extlinux; echo SCRIPT FAILED: continuing...; fi +scan_dev_for_scripts=for script in ${boot_scripts}; do if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${script}; then echo Found U-Boot script ${prefix}${script}; run boot_a_script; echo SCRIPT FAILED: continuing...; fi; done +scriptaddr=0x80000000 +scripthdraddr=0x80080000 +scsi_boot=run scsi_init; if scsi dev ${devnum}; then devtype=scsi; run scan_dev_for_boot_part; fi +scsi_init=if ${scsi_need_init}; then scsi_need_init=false; scsi scan; fi +sd_bootcmd=echo Trying load from sd card..;mmcinfo; mmc read $load_addr $kernel_addr_sd $kernel_size_sd ;env exists secureboot && mmc read $kernelheader_addr_r $kernelhdr_addr_sd $kernelhdr_size_sd && esbc_validate ${kernelheader_addr_r};bootm $load_addr#$BOARD +soc=fsl-layerscape +usb_boot=usb start; if usb dev ${devnum}; then devtype=usb; run scan_dev_for_boot_part; fi +vendor=solidrun +xspi_bootcmd=echo Trying load from flexspi..;sf probe 0:0 && sf read $load_addr $kernel_start $kernel_size ; env exists secureboot &&sf read $kernelheader_addr_r $kernelheader_start $kernelheader_size && esbc_validate ${kernelheader_addr_r}; bootm $load_addr#$BOARD diff --git a/configs/solidrun_lx2160acex7_defconfig b/configs/solidrun_lx2160acex7_defconfig new file mode 100644 index 000000000000..7037821ff127 --- /dev/null +++ b/configs/solidrun_lx2160acex7_defconfig @@ -0,0 +1,53 @@ +BR2_aarch64=y +BR2_cortex_a72=y +BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_6_6=y +BR2_GLOBAL_PATCH_DIR="board/solidrun/lx2160acex7/patches" +BR2_DOWNLOAD_FORCE_CHECK_HASHES=y +BR2_TARGET_GENERIC_HOSTNAME="lx2160acex7" +BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_EUDEV=y +BR2_TARGET_GENERIC_GETTY_PORT="ttyAMA0" +BR2_ROOTFS_OVERLAY="board/solidrun/lx2160acex7/rootfs_overlay" +BR2_ROOTFS_POST_BUILD_SCRIPT="board/solidrun/lx2160acex7/post-build.sh" +BR2_ROOTFS_POST_IMAGE_SCRIPT="support/scripts/genimage.sh" +BR2_ROOTFS_POST_SCRIPT_ARGS="-c $(BINARIES_DIR)/genimage.cfg" +BR2_LINUX_KERNEL=y +BR2_LINUX_KERNEL_CUSTOM_TARBALL=y +BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="$(call github,nxp-qoriq,linux,lf-6.6.36-2.1.0)/linux-lf-6.6.36-2.1.0.tar.gz" +BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG=y +BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(LINUX_DIR)/arch/arm64/configs/lsdk.config board/solidrun/lx2160acex7/linux.config" +BR2_LINUX_KERNEL_DTS_SUPPORT=y +BR2_LINUX_KERNEL_INTREE_DTS_NAME="freescale/fsl-lx2160a-clearfog-cx freescale/fsl-lx2160a-honeycomb" +BR2_LINUX_KERNEL_INSTALL_TARGET=y +BR2_TARGET_ROOTFS_EXT2=y +BR2_TARGET_ROOTFS_EXT2_4=y +BR2_TARGET_ROOTFS_EXT2_SIZE="130M" +BR2_TARGET_ROOTFS_CPIO=y +BR2_TARGET_ARM_TRUSTED_FIRMWARE=y +BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL=y +BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL_LOCATION="$(call github,nxp-qoriq,atf,lf-5.15.71-2.2.0)/atf-lf-5.15.71-2.2.0.tar.gz" +BR2_TARGET_ARM_TRUSTED_FIRMWARE_PLATFORM="lx2160acex7" +BR2_TARGET_ARM_TRUSTED_FIRMWARE_FIP=y +BR2_TARGET_ARM_TRUSTED_FIRMWARE_RCW=y +BR2_TARGET_ARM_TRUSTED_FIRMWARE_UBOOT_AS_BL33=y +BR2_TARGET_ARM_TRUSTED_FIRMWARE_ADDITIONAL_VARIABLES="BOOT_MODE=sd" +BR2_TARGET_ARM_TRUSTED_FIRMWARE_IMAGES="fip.bin bl2_sd.pbl" +BR2_TARGET_UBOOT=y +BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y +BR2_TARGET_UBOOT_CUSTOM_TARBALL=y +BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="$(call github,nxp-qoriq,u-boot,lf-5.15.71-2.2.0)/u-boot-lf-5.15.71-2.2.0.tar.gz" +BR2_TARGET_UBOOT_BOARD_DEFCONFIG="lx2160acex7_tfa" +BR2_TARGET_UBOOT_NEEDS_DTC=y +BR2_PACKAGE_HOST_GENIMAGE=y +BR2_PACKAGE_HOST_QORIQ_RCW=y +BR2_PACKAGE_HOST_QORIQ_RCW_INTREE="lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw" +BR2_PACKAGE_HOST_UBOOT_TOOLS=y +BR2_PACKAGE_HOST_UBOOT_TOOLS_ENVIMAGE=y +BR2_PACKAGE_HOST_UBOOT_TOOLS_ENVIMAGE_SOURCE="board/solidrun/lx2160acex7/u-boot-environment-sd.txt" +BR2_PACKAGE_HOST_UBOOT_TOOLS_ENVIMAGE_SIZE="0x2000" +BR2_PACKAGE_QORIQ_DDR_PHY_BINARY=y +BR2_PACKAGE_QORIQ_MC_BINARY=y +BR2_PACKAGE_QORIQ_MC_TARGET_LX2160A=y +BR2_PACKAGE_QORIQ_MC_UTILS=y +BR2_PACKAGE_QORIQ_MC_UTILS_DPL="lx2160a/LX2160A-CEX7/clearfog-cx-s1_8-s2_0-dpl.dtb" +BR2_PACKAGE_QORIQ_MC_UTILS_DPC="lx2160a/LX2160A-CEX7/clearfog-cx-s1_8-s2_0-dpc.dtb" +BR2_PACKAGE_QORIQ_RESTOOL=y From patchwork Sun Dec 8 14:37:58 2024 Content-Type: text/plain; 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Sun, 08 Dec 2024 06:38:34 -0800 (PST) Received: from skbuf.lan ([86.127.124.81]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa666cf5743sm204660366b.65.2024.12.08.06.38.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Dec 2024 06:38:33 -0800 (PST) From: Vladimir Oltean To: buildroot@buildroot.org Cc: Brandon Maier , Rabeeh Khoury , Josua Mayer , Ioana Ciornei Date: Sun, 8 Dec 2024 16:37:58 +0200 Message-ID: <20241208143802.1048266-8-olteanv@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241208143802.1048266-1-olteanv@gmail.com> References: <20241208143802.1048266-1-olteanv@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1733668717; x=1734273517; darn=buildroot.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a+1EcYNbaQA7kcg79+QWY9wQyULBeibglvxuPNrcOZI=; b=UAA6KKESYKMaiv6/8F5giXZnifzUauj2csGLqsrcJDG48xGJ0kGWa2hlX/14IMzU0w s4K5qHtuCbWna0GXGBEl9u1UAd4u6jKVv7cFL5z3M0DDnjAk+nmq79nioUx2B2Nq7SzI y+8TbDpLjoJmYGpqozWDucwQQN5VmKbrpGJuFRlQgIKn0OsUozd6X2pTxa41rylwNT36 L4vpQjC2FoOjjGCitJF0ZVQIgg9iSk2RESIvEklsVpar2CptPjWAUooDr6sum0SBSYwF 6mBHCqnv4FR598F20dEOj3c4cO86e1Nz52CmNfzmeaF/cBiAEI6V1TFgfnvCO7j1/DlE /NqQ== X-Mailman-Original-Authentication-Results: smtp1.osuosl.org; dmarc=pass (p=none dis=none) header.from=gmail.com X-Mailman-Original-Authentication-Results: smtp1.osuosl.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=UAA6KKES Subject: [Buildroot] [PATCH v2 07/11] board/lx2160acex7: add Arm Trusted Firmware patches X-BeenThere: buildroot@buildroot.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: buildroot-bounces@buildroot.org Sender: "buildroot" These come straight from https://github.com/SolidRun/lx2160a_build/, commit 497e9ebf0e2a ("atf: update sdram configuration for internal cex6 evb revision 1.2"), and are unmodified. I've also symlinked the extra patch at board/freescale/common/patches/arm-trusted-firmware/0001-feat-build-add-support-for-new-binutils-versions.patch to avoid this warning treated as error: $(HOSTDIR)/bin/aarch64-buildroot-linux-gnu-ld: warning: $(BUILDDIR)/arm-trusted-firmware-custom/build/lx2160acex7/release/bl2/bl2.elf has a LOAD segment with RWX permissions make[2]: *** [Makefile:1240: $(BUILDDIR)/arm-trusted-firmware-custom/build/lx2160acex7/release/bl2/bl2.elf] Error 1 make[2]: *** Waiting for unfinished jobs.... Since commit 7cbc240ac2c3 ("configs/ls1028ardb: update to Linux 6.6"), Layerscape platforms no longer use board/freescale/common/patches, and neither do we, here. But we use an older arm-trusted-firmware tag of lf-5.15.71-2.2.0, so we need to selectively include that one patch. Signed-off-by: Vladimir Oltean --- v1->v2: - split out from previous [PATCH 6/7] board/lx2160acex7: new platform - update to latest lx2160a_build HEAD .../0001-plat-nxp-lx2160a-auto-boot.patch | 219 +++++++ ...ccount-MEM_PLL_CFG_SHIFT-for-ddr-fre.patch | 85 +++ ...sert-SUS_S5-GPIO-to-poweroff-the-COM.patch | 29 + ...assert-IRQ0-GPIO-to-poweroff-the-EVB.patch | 29 + ...ptional-S5-gpio-from-Makefile-consta.patch | 63 ++ ...te-platform-for-solidrun-cex7-module.patch | 418 ++++++++++++ ...flexible-value-for-CONFIG_DDR_NODIMM.patch | 33 + ...tform-for-solidrun-internal-cex6-eva.patch | 544 ++++++++++++++++ ...ort-flushing-i2c-bus-before-ddr-init.patch | 365 +++++++++++ ...h-i2c-bus-with-spd-eeprom-before-ddr.patch | 30 + ...h-i2c-bus-with-spd-eeprom-before-ddr.patch | 30 + ...-building-without-NXP_NV_SW_MAINT_LA.patch | 49 ++ ...-boot-without-spi-flash-disable-non-.patch | 33 + ...te-platform-for-solidrun-lx2162a-som.patch | 597 ++++++++++++++++++ ...ddr-configuration-for-pcb-v1.2-with-.patch | 127 ++++ ...g-output-for-dimm-parameters-parsed-.patch | 83 +++ ...dq-mapping-and-remove-invalid-spd-ee.patch | 36 ++ ...dd-support-for-new-binutils-versions.patch | 1 + 18 files changed, 2771 insertions(+) create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0001-plat-nxp-lx2160a-auto-boot.patch create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0002-dcfg-Take-into-account-MEM_PLL_CFG_SHIFT-for-ddr-fre.patch create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0003-lx2160acex7-assert-SUS_S5-GPIO-to-poweroff-the-COM.patch create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0004-lx2160acex6-assert-IRQ0-GPIO-to-poweroff-the-EVB.patch create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0005-lx2160a-assert-optional-S5-gpio-from-Makefile-consta.patch create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0006-add-separate-platform-for-solidrun-cex7-module.patch create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0007-lx2160a-support-flexible-value-for-CONFIG_DDR_NODIMM.patch create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0008-add-separate-platform-for-solidrun-internal-cex6-eva.patch create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0009-lx2160a-support-flushing-i2c-bus-before-ddr-init.patch create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0010-lx2160acex6-flush-i2c-bus-with-spd-eeprom-before-ddr.patch create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0011-lx2160acex7-flush-i2c-bus-with-spd-eeprom-before-ddr.patch create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0012-plat-lx2160a-fix-building-without-NXP_NV_SW_MAINT_LA.patch create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0013-plat-lx2160a-fix-boot-without-spi-flash-disable-non-.patch create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0014-add-separate-platform-for-solidrun-lx2162a-som.patch create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0015-lx2160acex6-add-ddr-configuration-for-pcb-v1.2-with-.patch create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0016-nxp-ddr-add-debug-output-for-dimm-parameters-parsed-.patch create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0017-lx2160acex6-fix-dq-mapping-and-remove-invalid-spd-ee.patch create mode 120000 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0018-feat-build-add-support-for-new-binutils-versions.patch diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0001-plat-nxp-lx2160a-auto-boot.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0001-plat-nxp-lx2160a-auto-boot.patch new file mode 100644 index 000000000000..4b47054b0d78 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0001-plat-nxp-lx2160a-auto-boot.patch @@ -0,0 +1,219 @@ +From 5d13f425bd0dea29912bf253a7be83a7cdca591d Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury +Date: Sun, 28 Nov 2021 14:00:07 +0200 +Subject: [PATCH] plat/nxp: lx2160a auto boot + +This patch adds support to patch RCW that already has SD/eMMC/SPI boot +support embedded with conditional load and jump. +The idea is to look for SD/eMMC/SPI boot, and modify src/dst/size +address with the correct values; rather than adding blockread at the end +of RCW code. + +With this patch images are unified and can be used to boot from SD / +eMMC and SPI. + +Signed-off-by: Rabeeh Khoury +--- + .../plat_make_helper/plat_common_def.mk | 5 ++ + plat/nxp/soc-lx2160a/lx2160ardb/platform.mk | 3 +- + plat/nxp/soc-lx2160a/soc.mk | 5 ++ + tools/nxp/create_pbl/create_pbl.c | 74 ++++++++++++++++--- + 4 files changed, 76 insertions(+), 11 deletions(-) + +diff --git a/plat/nxp/common/plat_make_helper/plat_common_def.mk b/plat/nxp/common/plat_make_helper/plat_common_def.mk +index 86dacf83d..a1038a073 100644 +--- a/plat/nxp/common/plat_make_helper/plat_common_def.mk ++++ b/plat/nxp/common/plat_make_helper/plat_common_def.mk +@@ -91,6 +91,11 @@ define add_boot_mode_define + else ifeq ($(1),flexspi_nor) + $$(eval $$(call SET_NXP_MAKE_FLAG,XSPI_NEEDED,BL2)) + $$(eval $$(call add_define,FLEXSPI_NOR_BOOT)) ++ else ifeq ($(1),auto) ++ $$(eval $$(call SET_FLAG,SD_MMC_NEEDED,BL2)) ++ $$(eval $$(call add_define,EMMC_BOOT)) ++ $$(eval $$(call SET_FLAG,XSPI_NEEDED,BL2)) ++ $$(eval $$(call add_define,FLEXSPI_NOR_BOOT)) + else + $$(error $(PLAT) Cannot Support Boot Mode: $(BOOT_MODE)) + endif +diff --git a/plat/nxp/soc-lx2160a/lx2160ardb/platform.mk b/plat/nxp/soc-lx2160a/lx2160ardb/platform.mk +index ffb5fadee..09c552c72 100644 +--- a/plat/nxp/soc-lx2160a/lx2160ardb/platform.mk ++++ b/plat/nxp/soc-lx2160a/lx2160ardb/platform.mk +@@ -42,7 +42,8 @@ BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\ + + SUPPORTED_BOOT_MODE := flexspi_nor \ + sd \ +- emmc ++ emmc \ ++ auto + + # Adding platform board build info + include plat/nxp/common/plat_make_helper/plat_common_def.mk +diff --git a/plat/nxp/soc-lx2160a/soc.mk b/plat/nxp/soc-lx2160a/soc.mk +index 239442c20..a72b4113d 100644 +--- a/plat/nxp/soc-lx2160a/soc.mk ++++ b/plat/nxp/soc-lx2160a/soc.mk +@@ -82,6 +82,11 @@ else + ifeq (${BOOT_MODE}, emmc) + $(eval $(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2)) + $(eval $(call add_define,EMMC_BOOT)) ++else ifeq (${BOOT_MODE}, auto) ++$(eval $(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2)) ++$(eval $(call add_define,EMMC_BOOT)) ++$(eval $(call SET_NXP_MAKE_FLAG,XSPI_NEEDED,BL2)) ++$(eval $(call add_define,FLEXSPI_NOR_BOOT)) + else + $(error Un-supported Boot Mode = ${BOOT_MODE}) + endif +diff --git a/tools/nxp/create_pbl/create_pbl.c b/tools/nxp/create_pbl/create_pbl.c +index 792747f0e..35cd39b61 100644 +--- a/tools/nxp/create_pbl/create_pbl.c ++++ b/tools/nxp/create_pbl/create_pbl.c +@@ -66,6 +66,7 @@ typedef enum { + FLXSPI_NOR_BOOT, + FLXSPI_NAND_BOOT, + FLXSPI_NAND4K_BOOT, ++ AUTO_BOOT, + MAX_BOOT /* must be last item in list */ + } boot_src_t; + +@@ -140,6 +141,7 @@ char *boot_src_string[] = { + "FLXSPI_NOR_BOOT", + "FLXSPI_NAND_BOOT", + "FLXSPI_NAND4K_BOOT", ++ "AUTO_BOOT", + }; + + enum stop_command { +@@ -193,7 +195,7 @@ struct pbl_image { + #define SOC_LS2088 2088 + #define SOC_LX2160 2160 + +-static uint32_t pbl_size; ++static uint32_t pbl_size = 0; + bool sb_flag; + + /*************************************************************************** +@@ -703,6 +705,8 @@ int main(int argc, char **argv) + int ret = FAILURE; + bool bootptr_flag = false; + enum stop_command flag_stop_cmd = CRC_STOP_COMMAND; ++ int skip = 0; ++ uint32_t saved_src; + + /* Initializing the global structure to zero. */ + memset(&pblimg, 0x0, sizeof(struct pbl_image)); +@@ -802,6 +806,8 @@ int main(int argc, char **argv) + pblimg.boot_src = FLXSPI_NAND_BOOT; + } else if (strcmp(optarg, "flexspi_nand2k") == 0) { + pblimg.boot_src = FLXSPI_NAND4K_BOOT; ++ } else if (strcmp(optarg, "auto") == 0) { ++ pblimg.boot_src = AUTO_BOOT; + } else { + printf("CMD Error: Invalid boot source.\n"); + goto exit_main; +@@ -909,13 +915,14 @@ int main(int argc, char **argv) + printf("%s: Error reading PBI Cmd.\n", __func__); + goto exit_main; + } ++ saved_src = pblimg.src_addr; + while (word != 0x808f0000 && word != 0x80ff0000) { + pbl_size++; + /* 11th words in RCW has PBL length. Update it + * with new length. 2 comamnds get added + * Block copy + CCSR Write/CSF header write + */ +- if (pbl_size == 11) { ++ if ((pbl_size == 11) && (pblimg.boot_src != AUTO_BOOT)) { + word_1 = (word & PBI_LEN_MASK) + + (PBI_LEN_ADD << 20); + word = word & ~PBI_LEN_MASK; +@@ -933,8 +940,50 @@ int main(int argc, char **argv) + goto exit_main; + } + } +- if (fwrite(&word, sizeof(word), NUM_MEM_BLOCK, +- fp_rcw_pbi_op) != NUM_MEM_BLOCK) { ++ if (pblimg.boot_src == AUTO_BOOT) { ++ if (word == 0x80000008) { ++ printf ("Found SD boot at %d\n",pbl_size); ++ pblimg.boot_src = SD_BOOT; ++ add_blk_cpy_cmd(fp_rcw_pbi_op, args); ++ skip = 4; // skip original blockcopy ++ pblimg.boot_src = AUTO_BOOT; ++ pblimg.src_addr = saved_src; ++ if (bootptr_flag == true) { ++ add_boot_ptr_cmd(fp_rcw_pbi_op); ++ skip += 2; // skip original bootlocptr write (low byte only) ++ printf("added bootptr\n"); ++ } ++ } ++ if (word == 0x80000009) { ++ printf ("Found eMMC boot at %d\n",pbl_size); ++ pblimg.boot_src = EMMC_BOOT; ++ add_blk_cpy_cmd(fp_rcw_pbi_op, args); ++ skip = 4; // skip original blockcopy ++ pblimg.boot_src = AUTO_BOOT; ++ pblimg.src_addr = saved_src; ++ if (bootptr_flag == true) { ++ add_boot_ptr_cmd(fp_rcw_pbi_op); ++ skip += 2; // skip original bootlocptr write (low byte only) ++ printf("added bootptr\n"); ++ } ++ } ++ if (word == 0x8000000f) { ++ printf ("Found SPI boot at %d\n",pbl_size); ++ pblimg.boot_src = FLXSPI_NOR_BOOT; ++ add_blk_cpy_cmd(fp_rcw_pbi_op, args); ++ skip = 4; // skip original blockcopy ++ pblimg.boot_src = AUTO_BOOT; ++ pblimg.src_addr = saved_src; ++ if (bootptr_flag == true) { ++ add_boot_ptr_cmd(fp_rcw_pbi_op); ++ skip += 2; // skip original bootlocptr write (low byte only) ++ printf("added bootptr\n"); ++ } ++ } ++ } ++ if (!skip && ++ (fwrite(&word, sizeof(word), NUM_MEM_BLOCK, ++ fp_rcw_pbi_op) != NUM_MEM_BLOCK)) { + printf("%s: [CH3] Error in Writing PBI Words\n", + __func__); + goto exit_main; +@@ -951,8 +1000,11 @@ int main(int argc, char **argv) + } else if (word == STOP_CMD_ARM_CH3) { + flag_stop_cmd = STOP_COMMAND; + } ++ ++ if (skip) ++ skip--; + } +- if (bootptr_flag == true) { ++ if ((pblimg.boot_src != AUTO_BOOT) && (bootptr_flag == true)) { + /* Add command to set boot_loc ptr */ + ret = add_boot_ptr_cmd(fp_rcw_pbi_op); + if (ret != SUCCESS) { +@@ -963,11 +1015,13 @@ int main(int argc, char **argv) + } + + /* Write acs write commands to output file */ +- ret = add_blk_cpy_cmd(fp_rcw_pbi_op, args); +- if (ret != SUCCESS) { +- printf("%s: Function add_blk_cpy_cmd return failure.\n", +- __func__); +- goto exit_main; ++ if (pblimg.boot_src != AUTO_BOOT) { ++ ret = add_blk_cpy_cmd(fp_rcw_pbi_op, args); ++ if (ret != SUCCESS) { ++ printf("%s: Function add_blk_cpy_cmd return failure.\n", ++ __func__); ++ goto exit_main; ++ } + } + + /* Add stop command after adding pbi commands */ +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0002-dcfg-Take-into-account-MEM_PLL_CFG_SHIFT-for-ddr-fre.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0002-dcfg-Take-into-account-MEM_PLL_CFG_SHIFT-for-ddr-fre.patch new file mode 100644 index 000000000000..9fb5de84bc89 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0002-dcfg-Take-into-account-MEM_PLL_CFG_SHIFT-for-ddr-fre.patch @@ -0,0 +1,85 @@ +From f750b41bf323d04791b4b25962f693c1fb43bade Mon Sep 17 00:00:00 2001 +From: Jon Nettleton +Date: Tue, 8 Oct 2024 04:56:45 +0200 +Subject: [PATCH] dcfg: Take into account MEM_PLL_CFG_SHIFT for ddr frequency + +The base ddr clock frequency is 1/4 the speed of the final +ddr clock frequency. By default the RCW config is setting +the CFG_SHIFT to be a 1/4 divider of the memory speed, +i.e. 3200 / 4 (800MHz). The parent DDRCLK is 100MHz so PLL_RAT +needs to be rounded to 100MHz. However using a divider of / 3 for +a lower speed always us to match industry standard ddr4 speeds +2666 and 2933 (2000 / 3 * 4 = 2666.67) + +This patch takes into account the PLL_CFG_SHIFT divider so these +speeds can be configured in the RCW and then updates the helper +function that reports ddr_clk_freq to properly multiply the +clock fed into the DDRC * 4 to properly reflect the actual MTs +that the memory is being configured for. + +Signed-off-by: Jon Nettleton +--- + drivers/nxp/dcfg/dcfg.c | 6 ++++++ + drivers/nxp/ddr/nxp-ddr/utility.c | 6 +++--- + include/drivers/nxp/dcfg/dcfg_lsch3.h | 4 ++++ + 3 files changed, 13 insertions(+), 3 deletions(-) + +diff --git a/drivers/nxp/dcfg/dcfg.c b/drivers/nxp/dcfg/dcfg.c +index e5c4db437..4a5820a64 100644 +--- a/drivers/nxp/dcfg/dcfg.c ++++ b/drivers/nxp/dcfg/dcfg.c +@@ -104,9 +104,15 @@ int get_clocks(struct sysinfo *sys) + sys->freq_ddr_pll0 *= (gur_in32(rcwsr0) >> + RCWSR0_MEM_PLL_RAT_SHIFT) & + RCWSR0_MEM_PLL_RAT_MASK; ++ sys->freq_ddr_pll0 /= ((gur_in32(rcwsr0) >> ++ RCWSR0_MEM_PLL_CFG_SHIFT) & ++ RCWSR0_MEM_PLL_CFG_MASK) + 1; + sys->freq_ddr_pll1 *= (gur_in32(rcwsr0) >> + RCWSR0_MEM2_PLL_RAT_SHIFT) & + RCWSR0_MEM2_PLL_RAT_MASK; ++ sys->freq_ddr_pll1 /= ((gur_in32(rcwsr0) >> ++ RCWSR0_MEM2_PLL_CFG_SHIFT) & ++ RCWSR0_MEM2_PLL_CFG_MASK) + 1; + if (sys->freq_platform == 0) { + return 1; + } else { +diff --git a/drivers/nxp/ddr/nxp-ddr/utility.c b/drivers/nxp/ddr/nxp-ddr/utility.c +index b6dffc872..3920b4488 100644 +--- a/drivers/nxp/ddr/nxp-ddr/utility.c ++++ b/drivers/nxp/ddr/nxp-ddr/utility.c +@@ -47,11 +47,11 @@ unsigned long get_ddr_freq(struct sysinfo *sys, int ctrl_num) + + switch (ctrl_num) { + case 0: +- return sys->freq_ddr_pll0; ++ return sys->freq_ddr_pll0 * 4; + case 1: +- return sys->freq_ddr_pll0; ++ return sys->freq_ddr_pll0 * 4; + case 2: +- return sys->freq_ddr_pll1; ++ return sys->freq_ddr_pll1 * 4; + } + + return 0; +diff --git a/include/drivers/nxp/dcfg/dcfg_lsch3.h b/include/drivers/nxp/dcfg/dcfg_lsch3.h +index cde86fe19..f9409d1a7 100644 +--- a/include/drivers/nxp/dcfg/dcfg_lsch3.h ++++ b/include/drivers/nxp/dcfg/dcfg_lsch3.h +@@ -53,8 +53,12 @@ + #define RCWSR0_OFFSET 0x100 + #define RCWSR0_SYS_PLL_RAT_SHIFT 2 + #define RCWSR0_SYS_PLL_RAT_MASK 0x1f ++#define RCWSR0_MEM_PLL_CFG_SHIFT 8 ++#define RCWSR0_MEM_PLL_CFG_MASK 0x3 + #define RCWSR0_MEM_PLL_RAT_SHIFT 10 + #define RCWSR0_MEM_PLL_RAT_MASK 0x3f ++#define RCWSR0_MEM2_PLL_CFG_SHIFT 16 ++#define RCWSR0_MEM2_PLL_CFG_MASK 0x3 + #define RCWSR0_MEM2_PLL_RAT_SHIFT 18 + #define RCWSR0_MEM2_PLL_RAT_MASK 0x3f + +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0003-lx2160acex7-assert-SUS_S5-GPIO-to-poweroff-the-COM.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0003-lx2160acex7-assert-SUS_S5-GPIO-to-poweroff-the-COM.patch new file mode 100644 index 000000000000..d77020956579 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0003-lx2160acex7-assert-SUS_S5-GPIO-to-poweroff-the-COM.patch @@ -0,0 +1,29 @@ +From 72557b712198e3292776fbe8697322c68583acf4 Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury +Date: Sun, 28 Nov 2021 13:33:10 +0200 +Subject: [PATCH] lx2160acex7: assert SUS_S5# GPIO to poweroff the COM + +Signed-off-by: Rabeeh Khoury +--- + plat/nxp/soc-lx2160a/aarch64/lx2160a.S | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/plat/nxp/soc-lx2160a/aarch64/lx2160a.S b/plat/nxp/soc-lx2160a/aarch64/lx2160a.S +index cc679f2ba..01b3c7ecd 100644 +--- a/plat/nxp/soc-lx2160a/aarch64/lx2160a.S ++++ b/plat/nxp/soc-lx2160a/aarch64/lx2160a.S +@@ -563,6 +563,11 @@ endfunc _soc_sys_reset + */ + func _soc_sys_off + ++ /* assert GPIO3[7] (IRQ07 - CEX-7 SUS_S5) */ ++ mov x3, #NXP_GPIO3_ADDR ++ mov w1, #0x01000000 ++ str w1, [x3] ++ + /* disable sec, QBman, spi and qspi */ + ldr x2, =NXP_DCFG_ADDR + ldr x0, =DCFG_DEVDISR1_OFFSET +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0004-lx2160acex6-assert-IRQ0-GPIO-to-poweroff-the-EVB.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0004-lx2160acex6-assert-IRQ0-GPIO-to-poweroff-the-EVB.patch new file mode 100644 index 000000000000..848951cf2a82 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0004-lx2160acex6-assert-IRQ0-GPIO-to-poweroff-the-EVB.patch @@ -0,0 +1,29 @@ +From 6bc7cf0b6de6427b230d47ae7ee273175ffe95dd Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Mon, 14 Oct 2024 11:55:03 +0200 +Subject: [PATCH] lx2160acex6: assert IRQ0 GPIO to poweroff the EVB + +Signed-off-by: Josua Mayer +--- + plat/nxp/soc-lx2160a/aarch64/lx2160a.S | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/plat/nxp/soc-lx2160a/aarch64/lx2160a.S b/plat/nxp/soc-lx2160a/aarch64/lx2160a.S +index 01b3c7ecd..8035b145e 100644 +--- a/plat/nxp/soc-lx2160a/aarch64/lx2160a.S ++++ b/plat/nxp/soc-lx2160a/aarch64/lx2160a.S +@@ -563,9 +563,9 @@ endfunc _soc_sys_reset + */ + func _soc_sys_off + +- /* assert GPIO3[7] (IRQ07 - CEX-7 SUS_S5) */ ++ /* assert GPIO3[7] (IRQ07 - CEX-7 SUS_S5), GPIO3[0] (IRQ00 - CEX-6 EVB IRQ0) */ + mov x3, #NXP_GPIO3_ADDR +- mov w1, #0x01000000 ++ mov w1, #0x81000000 + str w1, [x3] + + /* disable sec, QBman, spi and qspi */ +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0005-lx2160a-assert-optional-S5-gpio-from-Makefile-consta.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0005-lx2160a-assert-optional-S5-gpio-from-Makefile-consta.patch new file mode 100644 index 000000000000..25865c759e8d --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0005-lx2160a-assert-optional-S5-gpio-from-Makefile-consta.patch @@ -0,0 +1,63 @@ +From 13496d248f11fe09d5a634fe15dd6b507a520a87 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Fri, 18 Oct 2024 21:09:04 +0200 +Subject: [PATCH 5/6] lx2160a: assert optional S5 gpio from Makefile constant + +GPIO address and number for S5 are specific per board and should not be +set globally across lx2160. + +Add support for setting gpio address and number form platform.mk, into +soc.mk: + +- LX2160A_S5_GPIO_ADDR: gpio value register address +- LX2160A_S5_GPIO: gpio number + +This feature can be enabled for individual boards by setting a non-zero +address in platform.mk file, before including soc.mk. + +Signed-off-by: Josua Mayer +--- + plat/nxp/soc-lx2160a/aarch64/lx2160a.S | 9 ++++++--- + plat/nxp/soc-lx2160a/soc.mk | 8 ++++++++ + 2 files changed, 14 insertions(+), 3 deletions(-) + +diff --git a/plat/nxp/soc-lx2160a/aarch64/lx2160a.S b/plat/nxp/soc-lx2160a/aarch64/lx2160a.S +index 8035b145e..67ade7b66 100644 +--- a/plat/nxp/soc-lx2160a/aarch64/lx2160a.S ++++ b/plat/nxp/soc-lx2160a/aarch64/lx2160a.S +@@ -563,10 +563,13 @@ endfunc _soc_sys_reset + */ + func _soc_sys_off + +- /* assert GPIO3[7] (IRQ07 - CEX-7 SUS_S5), GPIO3[0] (IRQ00 - CEX-6 EVB IRQ0) */ +- mov x3, #NXP_GPIO3_ADDR +- mov w1, #0x81000000 ++#if defined(CONFIG_LX2160A_S5_GPIO_ADDR) && defined(CONFIG_LX2160A_S5_GPIO) ++ /* assert s5 gpio */ ++ mov x3, # CONFIG_LX2160A_S5_GPIO_ADDR ++ ldr w1, [x3] ++ orr w1, w1, # 1 << (31 - CONFIG_LX2160A_S5_GPIO) + str w1, [x3] ++#endif + + /* disable sec, QBman, spi and qspi */ + ldr x2, =NXP_DCFG_ADDR +diff --git a/plat/nxp/soc-lx2160a/soc.mk b/plat/nxp/soc-lx2160a/soc.mk +index a72b4113d..20e64753c 100644 +--- a/plat/nxp/soc-lx2160a/soc.mk ++++ b/plat/nxp/soc-lx2160a/soc.mk +@@ -177,3 +177,11 @@ include ${PLAT_PATH}/common/setup/common.mk + + # Adding source files to generate separate DDR FIP image + include ${PLAT_SOC_PATH}/ddr_fip.mk ++ ++# S5 GPIO (optional) ++LX2160A_S5_GPIO_ADDR ?= 0 ++LX2160A_S5_GPIO ?= 0 ++ifneq (${LX2160A_S5_GPIO_ADDR},0) ++$(eval $(call add_define_val,CONFIG_LX2160A_S5_GPIO_ADDR,$(LX2160A_S5_GPIO_ADDR))) ++$(eval $(call add_define_val,CONFIG_LX2160A_S5_GPIO,$(LX2160A_S5_GPIO))) ++endif +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0006-add-separate-platform-for-solidrun-cex7-module.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0006-add-separate-platform-for-solidrun-cex7-module.patch new file mode 100644 index 000000000000..8e961b6e0e86 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0006-add-separate-platform-for-solidrun-cex7-module.patch @@ -0,0 +1,418 @@ +From 1fc354074e5fe98e185633b8d7f62836d5b2b710 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Fri, 18 Oct 2024 15:11:53 +0200 +Subject: [PATCH 6/6] add separate platform for solidrun cex7 module + +Signed-off-by: Josua Mayer +--- + plat/nxp/soc-lx2160a/lx2160acex7/ddr_init.c | 116 ++++++++++++++++++ + plat/nxp/soc-lx2160a/lx2160acex7/plat_def.h | 105 ++++++++++++++++ + plat/nxp/soc-lx2160a/lx2160acex7/platform.c | 29 +++++ + plat/nxp/soc-lx2160a/lx2160acex7/platform.mk | 56 +++++++++ + .../soc-lx2160a/lx2160acex7/platform_def.h | 14 +++ + plat/nxp/soc-lx2160a/lx2160acex7/policy.h | 38 ++++++ + 6 files changed, 358 insertions(+) + create mode 100644 plat/nxp/soc-lx2160a/lx2160acex7/ddr_init.c + create mode 100644 plat/nxp/soc-lx2160a/lx2160acex7/plat_def.h + create mode 100644 plat/nxp/soc-lx2160a/lx2160acex7/platform.c + create mode 100644 plat/nxp/soc-lx2160a/lx2160acex7/platform.mk + create mode 100644 plat/nxp/soc-lx2160a/lx2160acex7/platform_def.h + create mode 100644 plat/nxp/soc-lx2160a/lx2160acex7/policy.h + +diff --git a/plat/nxp/soc-lx2160a/lx2160acex7/ddr_init.c b/plat/nxp/soc-lx2160a/lx2160acex7/ddr_init.c +new file mode 100644 +index 000000000..2bd014a7e +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2160acex7/ddr_init.c +@@ -0,0 +1,116 @@ ++/* ++ * Copyright 2021 NXP ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "plat_common.h" ++#include ++ ++#if defined(CONFIG_STATIC_DDR) || defined(CONFIG_DDR_NODIMM) ++#error not implemented ++#endif /* defined(CONFIG_STATIC_DDR) || defined(CONFIG_DDR_NODIMM) */ ++ ++int ddr_board_options(struct ddr_info *priv) ++{ ++ struct memctl_opt *popts = &priv->opt; ++ const struct ddr_conf *conf = &priv->conf; ++ ++ popts->vref_dimm = U(0x24); /* range 1, 83.4% */ ++ popts->rtt_override = 0; ++ popts->rtt_park = U(240); ++ popts->otf_burst_chop_en = 0; ++ popts->burst_length = U(DDR_BL8); ++ popts->trwt_override = U(1); ++ popts->bstopre = U(0); /* auto precharge */ ++ popts->addr_hash = 1; ++ ++ /* Set ODT impedance on PHY side */ ++ switch (conf->cs_on_dimm[1]) { ++ case 0xc: /* Two slots dual rank */ ++ case 0x4: /* Two slots single rank, not valid for interleaving */ ++ popts->trwt = U(0xf); ++ popts->twrt = U(0x7); ++ popts->trrt = U(0x7); ++ popts->twwt = U(0x7); ++ popts->vref_phy = U(0x6B); /* 83.6% */ ++ popts->odt = U(60); ++ popts->phy_tx_impedance = U(28); ++ break; ++ case 0: /* One slot used */ ++ default: ++ popts->trwt = U(0x3); ++ popts->twrt = U(0x3); ++ popts->trrt = U(0x3); ++ popts->twwt = U(0x3); ++ popts->vref_phy = U(0x60); /* 75% */ ++ popts->odt = U(48); ++ popts->phy_tx_impedance = U(28); ++ break; ++ } ++ ++ return 0; ++} ++ ++long long init_ddr(void) ++{ ++ int spd_addr[] = { 0x51, 0x52, 0x53, 0x54 }; ++ struct ddr_info info; ++ struct sysinfo sys; ++ long long dram_size; ++ ++ zeromem(&sys, sizeof(sys)); ++ if (get_clocks(&sys) != 0) { ++ ERROR("System clocks are not set\n"); ++ panic(); ++ } ++ debug("platform clock %lu\n", sys.freq_platform); ++ debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); ++ debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1); ++ ++ zeromem(&info, sizeof(info)); ++ ++ /* Set two DDRC. Unused DDRC will be removed automatically. */ ++ info.num_ctlrs = NUM_OF_DDRC; ++ info.spd_addr = spd_addr; ++ info.ddr[0] = (void *)NXP_DDR_ADDR; ++ info.ddr[1] = (void *)NXP_DDR2_ADDR; ++ info.phy[0] = (void *)NXP_DDR_PHY1_ADDR; ++ info.phy[1] = (void *)NXP_DDR_PHY2_ADDR; ++ info.clk = get_ddr_freq(&sys, 0); ++ info.img_loadr = load_img; ++ info.phy_gen2_fw_img_buf = PHY_GEN2_FW_IMAGE_BUFFER; ++ if (info.clk == 0) { ++ info.clk = get_ddr_freq(&sys, 1); ++ } ++ info.dimm_on_ctlr = DDRC_NUM_DIMM; ++ ++ info.warm_boot_flag = DDR_WRM_BOOT_NT_SUPPORTED; ++ ++ dram_size = dram_init(&info ++#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508) ++ , NXP_CCN_HN_F_0_ADDR ++#endif ++ ); ++ ++ ++ if (dram_size < 0) { ++ ERROR("DDR init failed.\n"); ++ } ++ ++ return dram_size; ++} +diff --git a/plat/nxp/soc-lx2160a/lx2160acex7/plat_def.h b/plat/nxp/soc-lx2160a/lx2160acex7/plat_def.h +new file mode 100644 +index 000000000..02f51e74d +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2160acex7/plat_def.h +@@ -0,0 +1,105 @@ ++/* ++ * Copyright 2021 NXP ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ */ ++ ++#ifndef PLAT_DEF_H ++#define PLAT_DEF_H ++ ++#include ++#include ++/* Required without TBBR. ++ * To include the defines for DDR PHY ++ * Images. ++ */ ++#include ++ ++#include ++#include ++ ++#if defined(IMAGE_BL31) ++#define LS_SYS_TIMCTL_BASE 0x2890000 ++#define PLAT_LS_NSTIMER_FRAME_ID 0 ++#define LS_CONFIG_CNTACR 1 ++#endif ++ ++#define NXP_SYSCLK_FREQ 100000000 ++#define NXP_DDRCLK_FREQ 100000000 ++ ++/* UART related definition */ ++#define NXP_CONSOLE_ADDR NXP_UART_ADDR ++#define NXP_CONSOLE_BAUDRATE 115200 ++ ++/* Size of cacheable stacks */ ++#if defined(IMAGE_BL2) ++#if defined(TRUSTED_BOARD_BOOT) ++#define PLATFORM_STACK_SIZE 0x2000 ++#else ++#define PLATFORM_STACK_SIZE 0x1000 ++#endif ++#elif defined(IMAGE_BL31) ++#define PLATFORM_STACK_SIZE 0x1000 ++#endif ++ ++/* SD block buffer */ ++#define NXP_SD_BLOCK_BUF_SIZE (0x8000) ++#define NXP_SD_BLOCK_BUF_ADDR (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \ ++ - NXP_SD_BLOCK_BUF_SIZE) ++ ++#ifdef SD_BOOT ++#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \ ++ - NXP_SD_BLOCK_BUF_SIZE) ++#else ++#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) ++#endif ++ ++/* IO defines as needed by IO driver framework */ ++#define MAX_IO_DEVICES 4 ++#define MAX_IO_BLOCK_DEVICES 1 ++#define MAX_IO_HANDLES 4 ++ ++#define PHY_GEN2_FW_IMAGE_BUFFER (NXP_OCRAM_ADDR + CSF_HDR_SZ) ++ ++/* ++ * FIP image defines - Offset at which FIP Image would be present ++ * Image would include Bl31 , Bl33 and Bl32 (optional) ++ */ ++#ifdef POLICY_FUSE_PROVISION ++#define MAX_FIP_DEVICES 3 ++#endif ++ ++#ifndef MAX_FIP_DEVICES ++#define MAX_FIP_DEVICES 2 ++#endif ++ ++/* ++ * ID of the secure physical generic timer interrupt used by the BL32. ++ */ ++#define BL32_IRQ_SEC_PHY_TIMER 29 ++ ++#define BL31_WDOG_SEC 89 ++ ++#define BL31_NS_WDOG_WS1 108 ++ ++/* ++ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 ++ * terminology. On a GICv2 system or mode, the lists will be merged and treated ++ * as Group 0 interrupts. ++ */ ++#define PLAT_LS_G1S_IRQ_PROPS(grp) \ ++ INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ ++ GIC_INTR_CFG_EDGE) ++ ++/* SGI 15 and Secure watchdog interrupts assigned to Group 0 */ ++#define NXP_IRQ_SEC_SGI_7 15 ++ ++#define PLAT_LS_G0_IRQ_PROPS(grp) \ ++ INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \ ++ GIC_INTR_CFG_EDGE), \ ++ INTR_PROP_DESC(BL31_NS_WDOG_WS1, GIC_HIGHEST_SEC_PRIORITY, grp, \ ++ GIC_INTR_CFG_EDGE), \ ++ INTR_PROP_DESC(NXP_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ ++ GIC_INTR_CFG_LEVEL) ++#endif +diff --git a/plat/nxp/soc-lx2160a/lx2160acex7/platform.c b/plat/nxp/soc-lx2160a/lx2160acex7/platform.c +new file mode 100644 +index 000000000..b00adb51d +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2160acex7/platform.c +@@ -0,0 +1,29 @@ ++/* ++ * Copyright 2021 NXP ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ */ ++ ++#include ++ ++#pragma weak board_enable_povdd ++#pragma weak board_disable_povdd ++ ++bool board_enable_povdd(void) ++{ ++#ifdef CONFIG_POVDD_ENABLE ++ return true; ++#else ++ return false; ++#endif ++} ++ ++bool board_disable_povdd(void) ++{ ++#ifdef CONFIG_POVDD_ENABLE ++ return true; ++#else ++ return false; ++#endif ++} +diff --git a/plat/nxp/soc-lx2160a/lx2160acex7/platform.mk b/plat/nxp/soc-lx2160a/lx2160acex7/platform.mk +new file mode 100644 +index 000000000..37598c2d7 +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2160acex7/platform.mk +@@ -0,0 +1,56 @@ ++# ++# Copyright 2021 NXP ++# ++# SPDX-License-Identifier: BSD-3-Clause ++# ++ ++# board-specific build parameters ++ ++BOOT_MODE ?= flexspi_nor ++BOARD ?= lx2160acex7 ++POVDD_ENABLE := no ++NXP_COINED_BB := no ++ ++ # DDR Compilation Configs ++NUM_OF_DDRC := 2 ++DDRC_NUM_DIMM := 2 ++DDRC_NUM_CS := 4 ++DDR_ECC_EN := yes ++ #enable address decoding feature ++DDR_ADDR_DEC := yes ++APPLY_MAX_CDD := yes ++ ++# S5 GPIO ++LX2160A_S5_GPIO_ADDR := NXP_GPIO3_ADDR ++LX2160A_S5_GPIO := 7 ++ ++# DDR Errata ++ERRATA_DDR_A011396 := 1 ++ERRATA_DDR_A050450 := 1 ++ ++ # On-Board Flash Details ++FLASH_TYPE := MT35XU512A ++XSPI_FLASH_SZ := 0x10000000 ++NXP_XSPI_NOR_UNIT_SIZE := 0x20000 ++BL2_BIN_XSPI_NOR_END_ADDRESS := 0x100000 ++# CONFIG_FSPI_ERASE_4K is required to erase 4K sector sizes. This ++# config is enabled for future use cases. ++FSPI_ERASE_4K := 0 ++ ++ # Platform specific features. ++WARM_BOOT := no ++ ++ # Adding Platform files build files ++BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\ ++ ${BOARD_PATH}/platform.c ++ ++SUPPORTED_BOOT_MODE := flexspi_nor \ ++ sd \ ++ emmc \ ++ auto ++ ++# Adding platform board build info ++include plat/nxp/common/plat_make_helper/plat_common_def.mk ++ ++ # Adding SoC build info ++include plat/nxp/soc-lx2160a/soc.mk +diff --git a/plat/nxp/soc-lx2160a/lx2160acex7/platform_def.h b/plat/nxp/soc-lx2160a/lx2160acex7/platform_def.h +new file mode 100644 +index 000000000..666099800 +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2160acex7/platform_def.h +@@ -0,0 +1,14 @@ ++/* ++ * Copyright 2021 NXP ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ */ ++ ++#ifndef PLATFORM_DEF_H ++#define PLATFORM_DEF_H ++ ++#include "plat_def.h" ++#include "plat_default_def.h" ++ ++#endif +diff --git a/plat/nxp/soc-lx2160a/lx2160acex7/policy.h b/plat/nxp/soc-lx2160a/lx2160acex7/policy.h +new file mode 100644 +index 000000000..19ad6dbec +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2160acex7/policy.h +@@ -0,0 +1,38 @@ ++/* ++ * Copyright 2021 NXP ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ */ ++ ++#ifndef POLICY_H ++#define POLICY_H ++ ++/* Following defines affect the PLATFORM SECURITY POLICY */ ++ ++/* set this to 0x0 if the platform is not using/responding to ECC errors ++ * set this to 0x1 if ECC is being used (we have to do some init) ++ */ ++#define POLICY_USING_ECC 0x0 ++ ++/* Set this to 0x0 to leave the default SMMU page size in sACR ++ * Set this to 0x1 to change the SMMU page size to 64K ++ */ ++#define POLICY_SMMU_PAGESZ_64K 0x1 ++ ++/* ++ * POLICY_PERF_WRIOP = 0 : No Performance enhancement for WRIOP RN-I ++ * POLICY_PERF_WRIOP = 1 : No Performance enhancement for WRIOP RN-I = 7 ++ * POLICY_PERF_WRIOP = 2 : No Performance enhancement for WRIOP RN-I = 23 ++ */ ++#define POLICY_PERF_WRIOP 0 ++ ++/* ++ * set this to '1' if the debug clocks need to remain enabled during ++ * system entry to low-power (LPM20) - this should only be necessary ++ * for testing and NEVER set for normal production ++ */ ++#define POLICY_DEBUG_ENABLE 0 ++ ++ ++#endif /* POLICY_H */ +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0007-lx2160a-support-flexible-value-for-CONFIG_DDR_NODIMM.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0007-lx2160a-support-flexible-value-for-CONFIG_DDR_NODIMM.patch new file mode 100644 index 000000000000..f38c770eaf67 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0007-lx2160a-support-flexible-value-for-CONFIG_DDR_NODIMM.patch @@ -0,0 +1,33 @@ +From 92d0a6fab056eb43fa5561fb1888c8c393ebee29 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Fri, 18 Oct 2024 21:17:12 +0200 +Subject: [PATCH 7/8] lx2160a: support flexible value for CONFIG_DDR_NODIMM + +Add support for values other than 0 and 1 for CONFIG_DDR_NODIMM. +This macro can be used for both enabling, and selecting a specific +memory configuration at compile-time. + +Signed-off-by: Josua Mayer +--- + plat/nxp/common/plat_make_helper/plat_common_def.mk | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/plat/nxp/common/plat_make_helper/plat_common_def.mk b/plat/nxp/common/plat_make_helper/plat_common_def.mk +index a1038a073..ed6e0bdac 100644 +--- a/plat/nxp/common/plat_make_helper/plat_common_def.mk ++++ b/plat/nxp/common/plat_make_helper/plat_common_def.mk +@@ -39,8 +39,9 @@ ifneq (${NUM_OF_DDRC},) + $(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC})) + endif + +-ifeq (${CONFIG_DDR_NODIMM},1) +-$(eval $(call add_define,CONFIG_DDR_NODIMM)) ++CONFIG_DDR_NODIMM ?= 0 ++ifneq (${CONFIG_DDR_NODIMM},0) ++$(eval $(call add_define_val,CONFIG_DDR_NODIMM,${CONFIG_DDR_NODIMM})) + DDRC_NUM_DIMM := 1 + endif + +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0008-add-separate-platform-for-solidrun-internal-cex6-eva.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0008-add-separate-platform-for-solidrun-internal-cex6-eva.patch new file mode 100644 index 000000000000..0a499e669c33 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0008-add-separate-platform-for-solidrun-internal-cex6-eva.patch @@ -0,0 +1,544 @@ +From 067c11cd6a6de8c7480b1f8c1002f29a9bc85787 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Fri, 18 Oct 2024 15:05:13 +0200 +Subject: [PATCH 8/8] add separate platform for solidrun internal cex6 + evaluation board + +Signed-off-by: Josua Mayer +--- + plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c | 236 ++++++++++++++++++ + plat/nxp/soc-lx2160a/lx2160acex6/plat_def.h | 105 ++++++++ + plat/nxp/soc-lx2160a/lx2160acex6/platform.c | 29 +++ + plat/nxp/soc-lx2160a/lx2160acex6/platform.mk | 61 +++++ + .../soc-lx2160a/lx2160acex6/platform_def.h | 14 ++ + plat/nxp/soc-lx2160a/lx2160acex6/policy.h | 38 +++ + 6 files changed, 483 insertions(+) + create mode 100644 plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c + create mode 100644 plat/nxp/soc-lx2160a/lx2160acex6/plat_def.h + create mode 100644 plat/nxp/soc-lx2160a/lx2160acex6/platform.c + create mode 100644 plat/nxp/soc-lx2160a/lx2160acex6/platform.mk + create mode 100644 plat/nxp/soc-lx2160a/lx2160acex6/platform_def.h + create mode 100644 plat/nxp/soc-lx2160a/lx2160acex6/policy.h + +diff --git a/plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c b/plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c +new file mode 100644 +index 000000000..0b978e298 +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c +@@ -0,0 +1,236 @@ ++/* ++ * Copyright 2021 NXP ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "plat_common.h" ++#include ++ ++#ifdef CONFIG_STATIC_DDR ++#error not implemented ++#elif defined(CONFIG_DDR_NODIMM) ++#if CONFIG_DDR_NODIMM == 1 ++/* ++ * PCB Revision 1.0: 9 x K4A8G085WC-BCWE TODO ++ */ ++#error Not implemented. ++#endif /* CONFIG_DDR_NODIMM == 1 */ ++ ++#if CONFIG_DDR_NODIMM == 2 ++/* ++ * PCB Revision 1.1: 2 x 5 x K4A8G165WB-BCRC ++ * ++ * ECC disabled because of training failures. ++ */ ++#define CONFIG_DDR_NODIMM_CH2 ++static const struct dimm_params static_dimm = { ++ .mpart = "Fixed DDR Config 2", ++ .n_ranks = 1, ++ .die_density = 0x6, // encoded per spd byte 4, 0b110 = 16Gbit ++ .rank_density = 0x200000000, // 16GB ++ .capacity = 0x200000000, // 16GB ++ .primary_sdram_width = 64, ++ .ec_sdram_width = 0, // no ecc extension ++ .rdimm = 0, ++ .package_3ds = 0, ++ .device_width = 16, // 16 bit per sdram ++ .rc = 0, ++ ++ .n_row_addr = 17, ++ .n_col_addr = 10, ++ .edc_config = 0, // disable ecc ++ .bank_addr_bits = 0, // 4 banks ++ .bank_group_bits = 1, // 2 bank groups ++ .burst_lengths_bitmask = 0xc, // enable 4 & 8-bit burst (DDR4 spec) ++ ++ .mirrored_dimm = 0, ++ ++ // timings based on K4A8G085WC-BCTD (DDR4-2666), missing values for 3200 ++ .mtb_ps = 125, // MTB per SPD spec ++ .ftb_10th_ps = 10, // default value, unused by nxp ddr driver ++ .taa_ps = 13750, // min. 13.75ns ++ .tfaw_ps = 30000, // min: max(30ns or 28CK) (this 16Gbit sdram has 2KB pages) ++ ++ .tckmin_x_ps = 625, // 3200 (CK=1600) ++ .tckmax_ps = 1250, // 1600 (CK=800) ++ ++ .caslat_x = 0b00000001010101010101010000000000, // CL = [10,12,14,16,18,20,22,24] (1 << CL) ++ ++ .trcd_ps = 13750, // 13.75ns - CL22-22-22 ++ .trp_ps = 13750, // 13.75ns - CL22-22-22 ++ .tras_ps = 32000, // 32ns ++ ++ .trfc1_ps = 350000, // 350ns, ++ .trfc2_ps = 260000, // 260ns ++ .trfc4_ps = 160000, // 160ns ++ .trrds_ps = 5300, // min: max(4CK or 5.3ns) ++ .trrdl_ps = 6400, // min: max(4CK or 6.4ns) ++ .tccdl_ps = 5000, // min: max(4CK or 5ns) ++ .trfc_slr_ps = 0, ++ ++ .trc_ps = 45750, // tras + trp 45.75ns ++ .twr_ps = 15000, // 15ns ++ ++ .refresh_rate_ps = 7800000, // 1x mode 7.8us for standard temperature range (TODO: pick correct range based on temperature?!) ++ // .extended_op_srt = 0, ++ ++ // .rcw = {}, // only for registered dimm ++ .dq_mapping = { ++ 0x00, ++ 0x20, ++ 0x00, ++ 0x20, ++ 0x00, ++ 0x20, ++ 0x00, ++ 0x20, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x20, ++ 0x00, ++ 0x20, ++ 0x00, ++ 0x20, ++ 0x00, ++ 0x20, ++ }, ++ .dq_mapping_ors = 1, ++}; ++#endif /* CONFIG_DDR_NODIMM == 2 */ ++ ++int ddr_get_ddr_params(struct dimm_params *pdimm, ++ struct ddr_conf *conf) ++{ ++ // channel 1 ++ conf->dimm_in_use[0] = 1; ++ memcpy(&pdimm[0], &static_dimm, sizeof(struct dimm_params)); ++ ++#if defined(CONFIG_DDR_NODIMM_CH2) ++ // channel 2 ++ conf->dimm_in_use[1] = 1; // enable (module on) channel 2 ++ memcpy(&pdimm[1], &static_dimm, sizeof(struct dimm_params)); ++ ++ /* 2 modules */ ++ return 0x3; ++#else ++ /* 1 module */ ++ return 0x1; ++#endif /* defined(CONFIG_DDR_NODIMM_CH2) */ ++} ++#endif /* defined(CONFIG_DDR_NODIMM) */ ++ ++int ddr_board_options(struct ddr_info *priv) ++{ ++ struct memctl_opt *popts = &priv->opt; ++ const struct ddr_conf *conf = &priv->conf; ++ ++ popts->vref_dimm = U(0x24); /* range 1, 83.4% */ ++ popts->rtt_override = 0; ++ popts->rtt_park = U(240); ++ popts->otf_burst_chop_en = 0; ++ popts->burst_length = U(DDR_BL8); ++ popts->trwt_override = U(0); ++ popts->bstopre = U(0); /* auto precharge */ ++ popts->addr_hash = 1; ++ popts->caslat_override = 0; // TODO: why is this set by default?! ++ popts->caslat_override_value = 0; // TODO: why is this set by default?! ++ popts->auto_self_refresh_en = 1; ++ popts->output_driver_impedance = 0; // 34 Ohm ++ popts->twot_en = 0; ++ popts->threet_en = 0; ++ popts->addt_lat_override = 0; // TODO: why is this set by default?! ++ popts->addt_lat_override_value = 0; // TODO: why is this set by default?! ++ popts->phy_atx_impedance = 30; ++ popts->skip2d = 0; ++ ++ /* Set ODT impedance on PHY side */ ++ switch (conf->cs_on_dimm[1]) { ++ case 0xc: /* Two slots dual rank */ ++ case 0x4: /* Two slots single rank, not valid for interleaving */ ++ popts->trwt = U(0xf); ++ popts->twrt = U(0x7); ++ popts->trrt = U(0x7); ++ popts->twwt = U(0x7); ++ popts->vref_phy = U(0x6B); /* 83.6% */ ++ popts->odt = U(60); ++ popts->phy_tx_impedance = U(28); ++ break; ++ case 0: /* One slot used */ ++ default: ++ popts->trwt = U(0x3); ++ popts->twrt = U(0x3); ++ popts->trrt = U(0x3); ++ popts->twwt = U(0x3); ++ popts->vref_phy = U(0x60); /* 75% */ ++ popts->odt = U(48); ++ popts->phy_tx_impedance = U(28); ++ break; ++ } ++ ++ return 0; ++} ++ ++long long init_ddr(void) ++{ ++ int spd_addr[] = { 0x51, 0x52, 0x53, 0x54 }; ++ struct ddr_info info; ++ struct sysinfo sys; ++ long long dram_size; ++ ++ zeromem(&sys, sizeof(sys)); ++ if (get_clocks(&sys) != 0) { ++ ERROR("System clocks are not set\n"); ++ panic(); ++ } ++ debug("platform clock %lu\n", sys.freq_platform); ++ debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); ++ debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1); ++ ++ zeromem(&info, sizeof(info)); ++ ++ /* Set two DDRC. Unused DDRC will be removed automatically. */ ++ info.num_ctlrs = NUM_OF_DDRC; ++ info.spd_addr = spd_addr; ++ info.ddr[0] = (void *)NXP_DDR_ADDR; ++ info.ddr[1] = (void *)NXP_DDR2_ADDR; ++ info.phy[0] = (void *)NXP_DDR_PHY1_ADDR; ++ info.phy[1] = (void *)NXP_DDR_PHY2_ADDR; ++ info.clk = get_ddr_freq(&sys, 0); ++ info.img_loadr = load_img; ++ info.phy_gen2_fw_img_buf = PHY_GEN2_FW_IMAGE_BUFFER; ++ if (info.clk == 0) { ++ info.clk = get_ddr_freq(&sys, 1); ++ } ++ info.dimm_on_ctlr = DDRC_NUM_DIMM; ++ ++ info.warm_boot_flag = DDR_WRM_BOOT_NT_SUPPORTED; ++ ++ dram_size = dram_init(&info ++#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508) ++ , NXP_CCN_HN_F_0_ADDR ++#endif ++ ); ++ ++ ++ if (dram_size < 0) { ++ ERROR("DDR init failed.\n"); ++ } ++ ++ return dram_size; ++} +diff --git a/plat/nxp/soc-lx2160a/lx2160acex6/plat_def.h b/plat/nxp/soc-lx2160a/lx2160acex6/plat_def.h +new file mode 100644 +index 000000000..02f51e74d +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2160acex6/plat_def.h +@@ -0,0 +1,105 @@ ++/* ++ * Copyright 2021 NXP ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ */ ++ ++#ifndef PLAT_DEF_H ++#define PLAT_DEF_H ++ ++#include ++#include ++/* Required without TBBR. ++ * To include the defines for DDR PHY ++ * Images. ++ */ ++#include ++ ++#include ++#include ++ ++#if defined(IMAGE_BL31) ++#define LS_SYS_TIMCTL_BASE 0x2890000 ++#define PLAT_LS_NSTIMER_FRAME_ID 0 ++#define LS_CONFIG_CNTACR 1 ++#endif ++ ++#define NXP_SYSCLK_FREQ 100000000 ++#define NXP_DDRCLK_FREQ 100000000 ++ ++/* UART related definition */ ++#define NXP_CONSOLE_ADDR NXP_UART_ADDR ++#define NXP_CONSOLE_BAUDRATE 115200 ++ ++/* Size of cacheable stacks */ ++#if defined(IMAGE_BL2) ++#if defined(TRUSTED_BOARD_BOOT) ++#define PLATFORM_STACK_SIZE 0x2000 ++#else ++#define PLATFORM_STACK_SIZE 0x1000 ++#endif ++#elif defined(IMAGE_BL31) ++#define PLATFORM_STACK_SIZE 0x1000 ++#endif ++ ++/* SD block buffer */ ++#define NXP_SD_BLOCK_BUF_SIZE (0x8000) ++#define NXP_SD_BLOCK_BUF_ADDR (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \ ++ - NXP_SD_BLOCK_BUF_SIZE) ++ ++#ifdef SD_BOOT ++#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \ ++ - NXP_SD_BLOCK_BUF_SIZE) ++#else ++#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) ++#endif ++ ++/* IO defines as needed by IO driver framework */ ++#define MAX_IO_DEVICES 4 ++#define MAX_IO_BLOCK_DEVICES 1 ++#define MAX_IO_HANDLES 4 ++ ++#define PHY_GEN2_FW_IMAGE_BUFFER (NXP_OCRAM_ADDR + CSF_HDR_SZ) ++ ++/* ++ * FIP image defines - Offset at which FIP Image would be present ++ * Image would include Bl31 , Bl33 and Bl32 (optional) ++ */ ++#ifdef POLICY_FUSE_PROVISION ++#define MAX_FIP_DEVICES 3 ++#endif ++ ++#ifndef MAX_FIP_DEVICES ++#define MAX_FIP_DEVICES 2 ++#endif ++ ++/* ++ * ID of the secure physical generic timer interrupt used by the BL32. ++ */ ++#define BL32_IRQ_SEC_PHY_TIMER 29 ++ ++#define BL31_WDOG_SEC 89 ++ ++#define BL31_NS_WDOG_WS1 108 ++ ++/* ++ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 ++ * terminology. On a GICv2 system or mode, the lists will be merged and treated ++ * as Group 0 interrupts. ++ */ ++#define PLAT_LS_G1S_IRQ_PROPS(grp) \ ++ INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ ++ GIC_INTR_CFG_EDGE) ++ ++/* SGI 15 and Secure watchdog interrupts assigned to Group 0 */ ++#define NXP_IRQ_SEC_SGI_7 15 ++ ++#define PLAT_LS_G0_IRQ_PROPS(grp) \ ++ INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \ ++ GIC_INTR_CFG_EDGE), \ ++ INTR_PROP_DESC(BL31_NS_WDOG_WS1, GIC_HIGHEST_SEC_PRIORITY, grp, \ ++ GIC_INTR_CFG_EDGE), \ ++ INTR_PROP_DESC(NXP_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ ++ GIC_INTR_CFG_LEVEL) ++#endif +diff --git a/plat/nxp/soc-lx2160a/lx2160acex6/platform.c b/plat/nxp/soc-lx2160a/lx2160acex6/platform.c +new file mode 100644 +index 000000000..b00adb51d +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2160acex6/platform.c +@@ -0,0 +1,29 @@ ++/* ++ * Copyright 2021 NXP ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ */ ++ ++#include ++ ++#pragma weak board_enable_povdd ++#pragma weak board_disable_povdd ++ ++bool board_enable_povdd(void) ++{ ++#ifdef CONFIG_POVDD_ENABLE ++ return true; ++#else ++ return false; ++#endif ++} ++ ++bool board_disable_povdd(void) ++{ ++#ifdef CONFIG_POVDD_ENABLE ++ return true; ++#else ++ return false; ++#endif ++} +diff --git a/plat/nxp/soc-lx2160a/lx2160acex6/platform.mk b/plat/nxp/soc-lx2160a/lx2160acex6/platform.mk +new file mode 100644 +index 000000000..1165cfa09 +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2160acex6/platform.mk +@@ -0,0 +1,61 @@ ++# ++# Copyright 2021 NXP ++# ++# SPDX-License-Identifier: BSD-3-Clause ++# ++ ++# board-specific build parameters ++ ++BOOT_MODE ?= flexspi_nor ++BOARD ?= lx2160acex6 ++POVDD_ENABLE := no ++NXP_COINED_BB := no ++ ++ # DDR Compilation Configs ++NUM_OF_DDRC := 2 ++DDRC_NUM_DIMM := 2 ++DDRC_NUM_CS := 4 ++DDR_ECC_EN := yes ++ #enable address decoding feature ++DDR_ADDR_DEC := yes ++APPLY_MAX_CDD := yes ++ ++# Mock SPD: ++# - 0: disable mock spd ++# - 2: 2 x 5 x K4A8G165WB-BCRC PCB v1.1 ++CONFIG_DDR_NODIMM := 0 ++ ++# S5 GPIO ++LX2160A_S5_GPIO_ADDR := NXP_GPIO3_ADDR ++LX2160A_S5_GPIO := 0 ++ ++# DDR Errata ++ERRATA_DDR_A011396 := 1 ++ERRATA_DDR_A050450 := 1 ++ ++ # On-Board Flash Details ++FLASH_TYPE := MT35XU512A ++XSPI_FLASH_SZ := 0x10000000 ++NXP_XSPI_NOR_UNIT_SIZE := 0x20000 ++BL2_BIN_XSPI_NOR_END_ADDRESS := 0x100000 ++# CONFIG_FSPI_ERASE_4K is required to erase 4K sector sizes. This ++# config is enabled for future use cases. ++FSPI_ERASE_4K := 0 ++ ++ # Platform specific features. ++WARM_BOOT := no ++ ++ # Adding Platform files build files ++BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\ ++ ${BOARD_PATH}/platform.c ++ ++SUPPORTED_BOOT_MODE := flexspi_nor \ ++ sd \ ++ emmc \ ++ auto ++ ++# Adding platform board build info ++include plat/nxp/common/plat_make_helper/plat_common_def.mk ++ ++ # Adding SoC build info ++include plat/nxp/soc-lx2160a/soc.mk +diff --git a/plat/nxp/soc-lx2160a/lx2160acex6/platform_def.h b/plat/nxp/soc-lx2160a/lx2160acex6/platform_def.h +new file mode 100644 +index 000000000..666099800 +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2160acex6/platform_def.h +@@ -0,0 +1,14 @@ ++/* ++ * Copyright 2021 NXP ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ */ ++ ++#ifndef PLATFORM_DEF_H ++#define PLATFORM_DEF_H ++ ++#include "plat_def.h" ++#include "plat_default_def.h" ++ ++#endif +diff --git a/plat/nxp/soc-lx2160a/lx2160acex6/policy.h b/plat/nxp/soc-lx2160a/lx2160acex6/policy.h +new file mode 100644 +index 000000000..19ad6dbec +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2160acex6/policy.h +@@ -0,0 +1,38 @@ ++/* ++ * Copyright 2021 NXP ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ */ ++ ++#ifndef POLICY_H ++#define POLICY_H ++ ++/* Following defines affect the PLATFORM SECURITY POLICY */ ++ ++/* set this to 0x0 if the platform is not using/responding to ECC errors ++ * set this to 0x1 if ECC is being used (we have to do some init) ++ */ ++#define POLICY_USING_ECC 0x0 ++ ++/* Set this to 0x0 to leave the default SMMU page size in sACR ++ * Set this to 0x1 to change the SMMU page size to 64K ++ */ ++#define POLICY_SMMU_PAGESZ_64K 0x1 ++ ++/* ++ * POLICY_PERF_WRIOP = 0 : No Performance enhancement for WRIOP RN-I ++ * POLICY_PERF_WRIOP = 1 : No Performance enhancement for WRIOP RN-I = 7 ++ * POLICY_PERF_WRIOP = 2 : No Performance enhancement for WRIOP RN-I = 23 ++ */ ++#define POLICY_PERF_WRIOP 0 ++ ++/* ++ * set this to '1' if the debug clocks need to remain enabled during ++ * system entry to low-power (LPM20) - this should only be necessary ++ * for testing and NEVER set for normal production ++ */ ++#define POLICY_DEBUG_ENABLE 0 ++ ++ ++#endif /* POLICY_H */ +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0009-lx2160a-support-flushing-i2c-bus-before-ddr-init.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0009-lx2160a-support-flushing-i2c-bus-before-ddr-init.patch new file mode 100644 index 000000000000..4c0b23822764 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0009-lx2160a-support-flushing-i2c-bus-before-ddr-init.patch @@ -0,0 +1,365 @@ +From efa6cca1a194050caa37a16ddccbf5d6e568b42f Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Fri, 25 Oct 2024 15:36:57 +0200 +Subject: [PATCH 09/11] lx2160a: support flushing i2c bus before ddr init + +The i2c bus can get locked by a slave device holding sda low, when the +cpu is reset during a transaction. +Implement workaround according to LX2160A Chip Errata 07/2020 A-010650. + +The workaround is inactive by default and must be explicitly enabled +through a board platform.mk file defining buses and muxes to flush: + +LX2160_FLUSH_IIC: 1D array, takes comma separate uint8 indicating +human-readable i2c bus number, +e.g: IIC1 & IIC2 = "1, 2". + +LX2160_FLUSH_IIC_MUX: 2D array, takes comma-separated 1D array +initializer expressions with i2c bus number, mux address on the bus and +a bitmask for channels to flush, +e.g. IIC1 mux @ 77, channels 1&2 = "{1, 0x77, 0x03}". + +Signed-off-by: Josua Mayer +--- + plat/nxp/common/setup/common.mk | 1 + + plat/nxp/common/setup/include/plat_common.h | 2 + + plat/nxp/common/setup/ls_bl2_el3_setup.c | 1 + + plat/nxp/common/setup/ls_i2c_init.c | 274 ++++++++++++++++++++ + plat/nxp/soc-lx2160a/soc.mk | 6 + + 5 files changed, 284 insertions(+) + create mode 100644 plat/nxp/common/setup/ls_i2c_init.c + +diff --git a/plat/nxp/common/setup/common.mk b/plat/nxp/common/setup/common.mk +index 1fcf1d093..6333ec515 100644 +--- a/plat/nxp/common/setup/common.mk ++++ b/plat/nxp/common/setup/common.mk +@@ -80,6 +80,7 @@ BL2_SOURCES += drivers/io/io_fip.c \ + plat/nxp/common/setup/ls_image_load.c \ + plat/nxp/common/setup/ls_io_storage.c \ + plat/nxp/common/setup/ls_bl2_el3_setup.c \ ++ plat/nxp/common/setup/ls_i2c_init.c \ + plat/nxp/common/setup/${ARCH}/ls_bl2_mem_params_desc.c + + BL31_SOURCES += plat/nxp/common/setup/ls_bl31_setup.c \ +diff --git a/plat/nxp/common/setup/include/plat_common.h b/plat/nxp/common/setup/include/plat_common.h +index 45832fa68..1c850ebe2 100644 +--- a/plat/nxp/common/setup/include/plat_common.h ++++ b/plat/nxp/common/setup/include/plat_common.h +@@ -77,6 +77,8 @@ int open_backend(const uintptr_t spec); + void ls_bl2_plat_arch_setup(void); + void ls_bl2_el3_plat_arch_setup(void); + ++void bl2_i2c_init(void); ++ + enum boot_device { + BOOT_DEVICE_IFC_NOR, + BOOT_DEVICE_IFC_NAND, +diff --git a/plat/nxp/common/setup/ls_bl2_el3_setup.c b/plat/nxp/common/setup/ls_bl2_el3_setup.c +index a4cbaef45..63e3460d7 100644 +--- a/plat/nxp/common/setup/ls_bl2_el3_setup.c ++++ b/plat/nxp/common/setup/ls_bl2_el3_setup.c +@@ -276,6 +276,7 @@ void bl2_el3_plat_prepare_exit(void) + */ + void bl2_plat_preload_setup(void) + { ++ bl2_i2c_init(); + + soc_preload_setup(); + +diff --git a/plat/nxp/common/setup/ls_i2c_init.c b/plat/nxp/common/setup/ls_i2c_init.c +new file mode 100644 +index 000000000..5392b160d +--- /dev/null ++++ b/plat/nxp/common/setup/ls_i2c_init.c +@@ -0,0 +1,274 @@ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#define NXP_IIC1_ADDR 0x02000000 ++#define NXP_IIC2_ADDR 0x02010000 ++#define NXP_IIC3_ADDR 0x02020000 ++#define NXP_IIC4_ADDR 0x02030000 ++#define NXP_IIC5_ADDR 0x02040000 ++#define NXP_IIC6_ADDR 0x02050000 ++#define NXP_IIC7_ADDR 0x02060000 ++#define NXP_IIC8_ADDR 0x02070000 ++ ++#define RCWSR12 0x01e0012c ++#define RCWSR12_IIC2_PMUX_MASK 0x00000007 /* [0..2] */ ++#define RCWSR12_IIC2_PMUX_IIC2 0x00000000 ++#define RCWSR12_IIC2_PMUX_GPIO 0x00000001 ++#define RCWSR12_IIC3_PMUX_MASK 0x00000038 /* [3..5] */ ++#define RCWSR12_IIC3_PMUX_IIC3 0x00000000 ++#define RCWSR12_IIC3_PMUX_GPIO 0x00000008 ++#define RCWSR12_IIC4_PMUX_MASK 0x000001c0 /* [6..8] */ ++#define RCWSR12_IIC4_PMUX_IIC4 0x00000000 ++#define RCWSR12_IIC4_PMUX_GPIO 0x00000040 ++#define RCWSR12_IIC5_PMUX_MASK 0x00000e00 /* [9..11] */ ++#define RCWSR12_IIC5_PMUX_IIC5 0x00000000 ++#define RCWSR12_IIC5_PMUX_GPIO 0x00000200 ++#define RCWSR12_IIC6_PMUX_MASK 0x00007000 /* [12..14] */ ++#define RCWSR12_IIC6_PMUX_IIC6 0x00000000 ++#define RCWSR12_IIC6_PMUX_GPIO 0x00001000 ++#define RCWSR13 0x01e00130 ++#define RCWSR12_SDHC2_DAT74_PMUX_MASK 0x00000003 ++#define RCWSR12_SDHC2_DAT74_PMUX_SDHC2 0x00000000 ++#define RCWSR12_SDHC2_DAT74_PMUX_IIC78 0x00000001 ++#define RCWSR14 0x01e00134 ++#define RCWSR14_IIC1_PMUX_MASK 0x00000400 /* [10] */ ++#define RCWSR14_IIC1_PMUX_IIC1 0x00000000 ++#define RCWSR14_IIC1_PMUX_GPIO 0x00000400 ++ ++static void ls_i2c_flush_pca9547(uint8_t busno, const char *busname, uint8_t address, uint8_t channels); ++static void ls_i2c_flush(uint8_t busno, const char *busname); ++ ++/** ++ * Flush i2c buses to make slave devices release sda, ++ * in case the system was reset during a transaction. ++ */ ++void bl2_i2c_init() { ++ const uint8_t bus_flush_list[] = {CONFIG_LX2160_FLUSH_IIC}; ++ /* ++ * List of muxes and channels to flush. Takes 2D array: ++ * {, , }, ++ */ ++ const uint8_t mux_flush_list[][3] = {CONFIG_LX2160_FLUSH_IIC_MUX}; ++ const uintptr_t iic_base_addr[] = { ++ NXP_IIC1_ADDR, ++ NXP_IIC2_ADDR, ++ NXP_IIC3_ADDR, ++ NXP_IIC4_ADDR, ++ NXP_IIC5_ADDR, ++ NXP_IIC6_ADDR, ++ }; ++ const char *iic_name[] = { ++ "IIC1", ++ "IIC2", ++ "IIC3", ++ "IIC4", ++ "IIC5", ++ "IIC6", ++ }; ++ int i; ++ uint8_t busno; ++ uint8_t address; ++ uint8_t channels; ++ ++ /* flush i2c buses */ ++ for (i = 0; i < ARRAY_SIZE(bus_flush_list); i++) { ++ busno = bus_flush_list[i] - 1; ++ i2c_init(iic_base_addr[busno]); ++ ls_i2c_flush(busno, iic_name[busno]); ++ } ++ ++ /* flush muxes channels */ ++ for (i = 0; i < ARRAY_SIZE(mux_flush_list); i++) { ++ busno = mux_flush_list[i][0] - 1; ++ address = mux_flush_list[i][1]; ++ channels = mux_flush_list[i][2]; ++ i2c_init(iic_base_addr[busno]); ++ ls_i2c_flush_pca9547(busno, iic_name[busno], address, channels); ++ } ++} ++ ++static void ls_i2c_flush_pca9547(uint8_t busno, const char *busname, uint8_t chip, uint8_t channels) { ++ uint8_t channel, creg = 0; ++ char buffer[64]; ++ int ret; ++ ++ /* try read configuration register */ ++ ret = i2c_read(chip, 0x00, 1, &creg, 1); ++ if(ret != 0) { ++ /* no device responding at address, skip */ ++ return; ++ } ++ ++ /* after reset configuration register reads 0x08 */ ++ if(creg != 0x08) { ++ /* probably not a pca9547, skip */ ++ return; ++ } ++ ++ /* flush selected channels */ ++ for(uint8_t i = 8; i > 0; i--) { ++ if (!(channels & (1 << (i-1)))) ++ continue; ++ ++ /* select channel i */ ++ channel = 0x08 | (i-1); ++ i2c_write(chip, 0x00, 1, &channel, 1); ++ ++ /* flush channel */ ++ snprintf(buffer, sizeof(buffer), "%s mux@%02x channel %u", busname, chip, i-1); ++ ls_i2c_flush(busno, buffer); ++ } ++} ++ ++static struct i2c_bus_info { ++ uintptr_t pinmux_addr; ++ uint32_t pinmux_mask; ++ uint32_t pinmux_sel; ++ uintptr_t gpio_addr; ++ uint8_t gpio_scl; ++ uint8_t gpio_sda; ++} ls_i2c_bus_info[] = { ++ { ++ .pinmux_addr = RCWSR14, ++ .pinmux_mask = RCWSR14_IIC1_PMUX_MASK, ++ .pinmux_sel = RCWSR14_IIC1_PMUX_GPIO, ++ .gpio_addr = NXP_GPIO1_ADDR, ++ .gpio_scl = 3, /* GPIO1_DAT03 */ ++ .gpio_sda = 2, /* GPIO1_DAT02 */ ++ }, ++ { ++ .pinmux_addr = RCWSR12, ++ .pinmux_mask = RCWSR12_IIC2_PMUX_MASK, ++ .pinmux_sel = RCWSR12_IIC2_PMUX_GPIO, ++ .gpio_addr = NXP_GPIO1_ADDR, ++ .gpio_scl = 31, /* GPIO1_DAT31 */ ++ .gpio_sda = 30, /* GPIO1_DAT30 */ ++ }, ++ { ++ .pinmux_addr = RCWSR12, ++ .pinmux_mask = RCWSR12_IIC3_PMUX_MASK, ++ .pinmux_sel = RCWSR12_IIC3_PMUX_GPIO, ++ .gpio_addr = NXP_GPIO1_ADDR, ++ .gpio_scl = 29, /* GPIO1_DAT29 */ ++ .gpio_sda = 28, /* GPIO1_DAT28 */ ++ }, ++ { ++ .pinmux_addr = RCWSR12, ++ .pinmux_mask = RCWSR12_IIC4_PMUX_MASK, ++ .pinmux_sel = RCWSR12_IIC4_PMUX_GPIO, ++ .gpio_addr = NXP_GPIO1_ADDR, ++ .gpio_scl = 27, /* GPIO1_DAT27 */ ++ .gpio_sda = 26, /* GPIO1_DAT26 */ ++ }, ++ { ++ .pinmux_addr = RCWSR12, ++ .pinmux_mask = RCWSR12_IIC5_PMUX_MASK, ++ .pinmux_sel = RCWSR12_IIC5_PMUX_GPIO, ++ .gpio_addr = NXP_GPIO1_ADDR, ++ .gpio_scl = 25, /* GPIO1_DAT25 */ ++ .gpio_sda = 24, /* GPIO1_DAT24 */ ++ }, ++ { ++ .pinmux_addr = RCWSR12, ++ .pinmux_mask = RCWSR12_IIC6_PMUX_MASK, ++ .pinmux_sel = RCWSR12_IIC6_PMUX_GPIO, ++ .gpio_addr = NXP_GPIO1_ADDR, ++ .gpio_scl = 23, /* GPIO1_DAT23 */ ++ .gpio_sda = 22, /* GPIO1_DAT22 */ ++ }, ++ { ++ .pinmux_addr = RCWSR13, ++ .pinmux_mask = RCWSR12_SDHC2_DAT74_PMUX_MASK, ++ .pinmux_sel = RCWSR12_SDHC2_DAT74_PMUX_IIC78, ++ .gpio_addr = NXP_GPIO2_ADDR, ++ .gpio_scl = 16, /* GPIO2_DAT16 */ ++ .gpio_sda = 15, /* GPIO2_DAT15 */ ++ }, ++ { ++ .pinmux_addr = RCWSR13, ++ .pinmux_mask = RCWSR12_SDHC2_DAT74_PMUX_MASK, ++ .pinmux_sel = RCWSR12_SDHC2_DAT74_PMUX_IIC78, ++ .gpio_addr = NXP_GPIO2_ADDR, ++ .gpio_scl = 18, /* GPIO2_DAT18 */ ++ .gpio_sda = 17, /* GPIO2_DAT17 */ ++ }, ++}; ++ ++/* ++ * Flush the i2c bus through any muxes with 9 clock cycles ++ * to ensure all slave devices release their locks on SDA. ++ * This is a work-around for i2c slave devices locking SDA, ++ * when the system has been reset during a transaction. ++ * ++ * The implementation is inspired by LX2160A Chip Errata 07/2020 A-010650. ++ */ ++static void ls_i2c_flush(uint8_t busno, const char *busname) { ++ struct i2c_bus_info *info; ++ uintptr_t gpdir_addr, gpodr_addr, gpdat_addr; ++ uint32_t pinmux, gpdir, gpodr, gpdat; ++ struct { ++ uint32_t pinmux, gpdir, gpodr, gpdat; ++ } backup; ++ uint32_t scl_mask, sda_mask; ++ ++ if(busno >= 8) { ++ ERROR("failed to flush i2c bus %u %s: invalid bus number!\n", busno, busname); ++ return; ++ } ++ /* load i2c bus specific information */ ++ info = &ls_i2c_bus_info[busno]; ++ gpdir_addr = info->gpio_addr + 0x0; ++ gpodr_addr = info->gpio_addr + 0x4; ++ gpdat_addr = info->gpio_addr + 0x8; ++ scl_mask = 0x80000000 >> info->gpio_scl; ++ sda_mask = 0x80000000 >> info->gpio_sda; ++ ++ /* backup configuration registers */ ++ pinmux = backup.pinmux = mmio_read_32(info->pinmux_addr); ++ gpdir = backup.gpdir = mmio_read_32(gpdir_addr); ++ gpodr = backup.gpodr = mmio_read_32(gpodr_addr); ++ gpdat = backup.gpdat = mmio_read_32(gpdat_addr); ++ ++ /* configure SCL+SDA as GPIOs */ ++ pinmux = (pinmux & ~info->pinmux_mask) | info->pinmux_sel; ++ mmio_write_32(info->pinmux_addr, pinmux); ++ ++ /* configure SCL+SDA as output open drain */ ++ gpdir |= scl_mask | sda_mask; ++ gpodr |= scl_mask | sda_mask; ++ gpdat |= scl_mask | sda_mask; ++ mmio_write_32(gpdir_addr, gpdir); ++ mmio_write_32(gpodr_addr, gpodr); ++ mmio_write_32(gpdat_addr, gpdat); ++ ++ /* ++ * reliable detection of blocked bus is hard ++ * because sda depends on the last sent bit. ++ * Flush unconditionally instead. ++ */ ++ ++ VERBOSE("flushing i2c bus %u (%s)\n", busno, busname); ++ ++ /* toggle clock 9 times */ ++ for(uint8_t i = 0; i < 9; i++) { ++ mmio_write_32(gpdat_addr, gpdat & ~scl_mask); ++ udelay(10); ++ mmio_write_32(gpdat_addr, gpdat | scl_mask); ++ udelay(10); ++ } ++ ++ /* restore configuration registers */ ++ mmio_write_32(gpdat_addr, backup.gpdat); ++ mmio_write_32(gpodr_addr, backup.gpodr); ++ mmio_write_32(gpdir_addr, backup.gpdir); ++ mmio_write_32(info->pinmux_addr, backup.pinmux); ++ ++ return; ++} +diff --git a/plat/nxp/soc-lx2160a/soc.mk b/plat/nxp/soc-lx2160a/soc.mk +index 20e64753c..fa8c63251 100644 +--- a/plat/nxp/soc-lx2160a/soc.mk ++++ b/plat/nxp/soc-lx2160a/soc.mk +@@ -185,3 +185,9 @@ ifneq (${LX2160A_S5_GPIO_ADDR},0) + $(eval $(call add_define_val,CONFIG_LX2160A_S5_GPIO_ADDR,$(LX2160A_S5_GPIO_ADDR))) + $(eval $(call add_define_val,CONFIG_LX2160A_S5_GPIO,$(LX2160A_S5_GPIO))) + endif ++ ++# I2C Bus Flushing (optional) ++LX2160_FLUSH_IIC ?= "" ++LX2160_FLUSH_IIC_MUX ?= "" ++$(eval $(call add_define_val,CONFIG_LX2160_FLUSH_IIC,"$(LX2160_FLUSH_IIC)")) ++$(eval $(call add_define_val,CONFIG_LX2160_FLUSH_IIC_MUX,"$(LX2160_FLUSH_IIC_MUX)")) +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0010-lx2160acex6-flush-i2c-bus-with-spd-eeprom-before-ddr.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0010-lx2160acex6-flush-i2c-bus-with-spd-eeprom-before-ddr.patch new file mode 100644 index 000000000000..ee7b9350043d --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0010-lx2160acex6-flush-i2c-bus-with-spd-eeprom-before-ddr.patch @@ -0,0 +1,30 @@ +From 668924da1e8df2036dc05022616eb7d15a8c8727 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Fri, 25 Oct 2024 16:43:59 +0200 +Subject: [PATCH 10/11] lx2160acex6: flush i2c bus with spd eeprom before ddr + init + +Signed-off-by: Josua Mayer +--- + plat/nxp/soc-lx2160a/lx2160acex6/platform.mk | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/plat/nxp/soc-lx2160a/lx2160acex6/platform.mk b/plat/nxp/soc-lx2160a/lx2160acex6/platform.mk +index 1165cfa09..950207878 100644 +--- a/plat/nxp/soc-lx2160a/lx2160acex6/platform.mk ++++ b/plat/nxp/soc-lx2160a/lx2160acex6/platform.mk +@@ -29,6 +29,11 @@ CONFIG_DDR_NODIMM := 0 + LX2160A_S5_GPIO_ADDR := NXP_GPIO3_ADDR + LX2160A_S5_GPIO := 0 + ++# I2C Bus Flushing: IIC1 ++LX2160_FLUSH_IIC := 1, ++# I2C Mux Flushing: IIC1: PCA9547@77: Channel 0 (SPD EEPROM) ++LX2160_FLUSH_IIC_MUX := { 1, 0x77, 0x01 }, ++ + # DDR Errata + ERRATA_DDR_A011396 := 1 + ERRATA_DDR_A050450 := 1 +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0011-lx2160acex7-flush-i2c-bus-with-spd-eeprom-before-ddr.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0011-lx2160acex7-flush-i2c-bus-with-spd-eeprom-before-ddr.patch new file mode 100644 index 000000000000..314da0a6311d --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0011-lx2160acex7-flush-i2c-bus-with-spd-eeprom-before-ddr.patch @@ -0,0 +1,30 @@ +From 722e93b7d159dfb9435e642cb0b38c2255a10391 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Fri, 25 Oct 2024 18:11:56 +0200 +Subject: [PATCH 11/11] lx2160acex7: flush i2c bus with spd eeprom before ddr + init + +Signed-off-by: Josua Mayer +--- + plat/nxp/soc-lx2160a/lx2160acex7/platform.mk | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/plat/nxp/soc-lx2160a/lx2160acex7/platform.mk b/plat/nxp/soc-lx2160a/lx2160acex7/platform.mk +index 37598c2d7..0b064bbbf 100644 +--- a/plat/nxp/soc-lx2160a/lx2160acex7/platform.mk ++++ b/plat/nxp/soc-lx2160a/lx2160acex7/platform.mk +@@ -24,6 +24,11 @@ APPLY_MAX_CDD := yes + LX2160A_S5_GPIO_ADDR := NXP_GPIO3_ADDR + LX2160A_S5_GPIO := 7 + ++# I2C Bus Flushing: IIC1 ++LX2160_FLUSH_IIC := 1, ++# I2C Mux Flushing: IIC1: PCA9547@77: Channel 0 (SPD EEPROM) ++LX2160_FLUSH_IIC_MUX := { 1, 0x77, 0x01 }, ++ + # DDR Errata + ERRATA_DDR_A011396 := 1 + ERRATA_DDR_A050450 := 1 +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0012-plat-lx2160a-fix-building-without-NXP_NV_SW_MAINT_LA.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0012-plat-lx2160a-fix-building-without-NXP_NV_SW_MAINT_LA.patch new file mode 100644 index 000000000000..278d7c249499 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0012-plat-lx2160a-fix-building-without-NXP_NV_SW_MAINT_LA.patch @@ -0,0 +1,49 @@ +From 94bdc4e055d10b89c7683c7966791612a7aed455 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Tue, 30 Jul 2024 17:45:33 +0300 +Subject: [PATCH 12/13] plat: lx2160a: fix building without + NXP_NV_SW_MAINT_LAST_EXEC_DATA + +Fix compiler errors encountered when disabling non-volatile storage of +execution state (NXP_NV_SW_MAINT_LAST_EXEC_DATA := no) while keeping +watchdog restart enabled (NXP_WDOG_RESTART := yes). + +Signed-off-by: Josua Mayer +--- + drivers/nxp/ddr/phy-gen2/phy.h | 2 +- + plat/nxp/soc-lx2160a/soc.c | 2 ++ + 2 files changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/nxp/ddr/phy-gen2/phy.h b/drivers/nxp/ddr/phy-gen2/phy.h +index 5e80f3638..7ddc7c7c6 100644 +--- a/drivers/nxp/ddr/phy-gen2/phy.h ++++ b/drivers/nxp/ddr/phy-gen2/phy.h +@@ -6,7 +6,7 @@ + #if !defined(PHY_H) && defined(NXP_WARM_BOOT) + #define PHY_H + +-#include ++#include + + /* To store sector size to be erase on flash*/ + #define PHY_ERASE_SIZE F_SECTOR_ERASE_SZ +diff --git a/plat/nxp/soc-lx2160a/soc.c b/plat/nxp/soc-lx2160a/soc.c +index 137c24ef8..4aebb1393 100644 +--- a/plat/nxp/soc-lx2160a/soc.c ++++ b/plat/nxp/soc-lx2160a/soc.c +@@ -521,10 +521,12 @@ void soc_init(void) + static uint64_t wdog_interrupt_handler(uint32_t id, uint32_t flags, + void *handle, void *cookie) + { ++#ifdef NXP_NV_SW_MAINT_LAST_EXEC_DATA + uint8_t data = WDOG_RESET_FLAG; + + wr_nv_app_data(WDT_RESET_FLAG_OFFSET, + (uint8_t *)&data, sizeof(data)); ++#endif + + mmio_write_32(NXP_RST_ADDR + RSTCNTL_OFFSET, SW_RST_REQ_INIT); + +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0013-plat-lx2160a-fix-boot-without-spi-flash-disable-non-.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0013-plat-lx2160a-fix-boot-without-spi-flash-disable-non-.patch new file mode 100644 index 000000000000..facda492f64c --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0013-plat-lx2160a-fix-boot-without-spi-flash-disable-non-.patch @@ -0,0 +1,33 @@ +From cbe4212aaa1b934135c8400f16265849d12689c0 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Tue, 30 Jul 2024 17:45:38 +0300 +Subject: [PATCH 13/13] plat: lx2160a: fix boot without spi flash / disable + non-volatile storage + +Watchdog restart function does not require book-keeping on non-volatile +storage. +Remove explicit enabling of NXP_NV_SW_MAINT_LAST_EXEC_DATA. + +This fixed hang during boot where atf gets stuck trying to erase a +sector of spi flash. + +Signed-off-by: Josua Mayer +--- + plat/nxp/soc-lx2160a/soc.mk | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/plat/nxp/soc-lx2160a/soc.mk b/plat/nxp/soc-lx2160a/soc.mk +index fa8c63251..4e864e164 100644 +--- a/plat/nxp/soc-lx2160a/soc.mk ++++ b/plat/nxp/soc-lx2160a/soc.mk +@@ -28,7 +28,6 @@ NXP_WDOG_RESTART := yes + + # for features enabled above. + ifeq (${NXP_WDOG_RESTART}, yes) +-NXP_NV_SW_MAINT_LAST_EXEC_DATA := yes + LS_EL3_INTERRUPT_HANDLER := yes + $(eval $(call add_define, NXP_WDOG_RESTART)) + endif +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0014-add-separate-platform-for-solidrun-lx2162a-som.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0014-add-separate-platform-for-solidrun-lx2162a-som.patch new file mode 100644 index 000000000000..0172514cf681 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0014-add-separate-platform-for-solidrun-lx2162a-som.patch @@ -0,0 +1,597 @@ +From 956be9ce8f365e7f9ac7d7d1f896f1c2a27f6287 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sun, 27 Oct 2024 18:00:11 +0100 +Subject: [PATCH] add separate platform for solidrun lx2162a som + +Signed-off-by: Josua Mayer +--- + plat/nxp/soc-lx2160a/lx2162asom/ddr_init.c | 290 ++++++++++++++++++ + plat/nxp/soc-lx2160a/lx2162asom/plat_def.h | 105 +++++++ + plat/nxp/soc-lx2160a/lx2162asom/platform.c | 29 ++ + plat/nxp/soc-lx2160a/lx2162asom/platform.mk | 61 ++++ + .../nxp/soc-lx2160a/lx2162asom/platform_def.h | 14 + + plat/nxp/soc-lx2160a/lx2162asom/policy.h | 38 +++ + 6 files changed, 537 insertions(+) + create mode 100644 plat/nxp/soc-lx2160a/lx2162asom/ddr_init.c + create mode 100644 plat/nxp/soc-lx2160a/lx2162asom/plat_def.h + create mode 100644 plat/nxp/soc-lx2160a/lx2162asom/platform.c + create mode 100644 plat/nxp/soc-lx2160a/lx2162asom/platform.mk + create mode 100644 plat/nxp/soc-lx2160a/lx2162asom/platform_def.h + create mode 100644 plat/nxp/soc-lx2160a/lx2162asom/policy.h + +diff --git a/plat/nxp/soc-lx2160a/lx2162asom/ddr_init.c b/plat/nxp/soc-lx2160a/lx2162asom/ddr_init.c +new file mode 100644 +index 000000000..2cadab7ba +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2162asom/ddr_init.c +@@ -0,0 +1,290 @@ ++/* ++ * Copyright 2018-2021 NXP ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "plat_common.h" ++#include ++ ++#ifdef CONFIG_STATIC_DDR ++#error not implemented ++#elif defined(CONFIG_DDR_NODIMM) ++#if CONFIG_DDR_NODIMM == 1 ++/* ++ * SoM Revision 1.1: 9 x K4A8G085WC-BCWE (SDP, 8GB w/ ECC) ++ * ++ * Use in production for units with empty SPD, ++ * and development. ++ */ ++static const struct dimm_params static_dimm = { ++ .mpart = "Fixed DDR Config 1", ++ .n_ranks = 1, ++ .die_density = 0x5, // encoded per spd byte 4, 0b101 = 8Gbit ++ .rank_density = 0x200000000, // 8GB ++ .capacity = 0x200000000, // 8GB ++ .primary_sdram_width = 64, ++ .ec_sdram_width = 8, // 8 bit ecc extension ++ .rdimm = 0, ++ .package_3ds = 0, ++ .device_width = 8, // 8 bit per sdram ++ .rc = 0, ++ ++ .n_row_addr = 16, ++ .n_col_addr = 10, ++ .edc_config = 2, // enable ecc ++ .bank_addr_bits = 0, // 4 banks ++ .bank_group_bits = 2, // 4 bank groups ++ .burst_lengths_bitmask = 0xc, // enable 4 & 8-bit burst (DDR4 spec) ++ ++ .mirrored_dimm = 0, ++ ++ // timings based on K4A8G085WC-BCTD (DDR4-2666), missing values for 3200 ++ .mtb_ps = 125, // MTB per SPD spec ++ .ftb_10th_ps = 10, // default value, unused by nxp ddr driver ++ .taa_ps = 13750, // min. 13.75ns ++ .tfaw_ps = 21000, // min: max(21ns or 20CK) (this 8Gbit sdram has 1KB pages) ++ ++ .tckmin_x_ps = 625, // 3200 (CK=1600) ++ .tckmax_ps = 1250, // 1600 (CK=800) ++ ++ .caslat_x = 0b00000001011111111111110000000000, // CL = [10-22,24] (1 << CL) ++ ++ .trcd_ps = 13750, // 13.75ns - CL22-22-22 ++ .trp_ps = 13750, // 13.75ns - CL22-22-22 ++ .tras_ps = 32000, // 32ns ++ ++ .trfc1_ps = 350000, // 350ns ++ .trfc2_ps = 260000, // 260ns ++ .trfc4_ps = 160000, // 160ns ++ .trrds_ps = 3300, // min: max(4CK or 3.3ns) ++ .trrdl_ps = 4900, // min: max(4CK or 6.4ns) ++ .tccdl_ps = 5000, // min: max(5CK or 5ns) ++ .trfc_slr_ps = 0, ++ ++ .trc_ps = 45750, // tras + trp 45.75ns ++ .twr_ps = 15000, // 15ns ++ ++ .refresh_rate_ps = 7800000, // 1x mode 7.8us for standard temperature range (TODO: pick correct range based on temperature?!) ++ // .extended_op_srt = 0, ++ ++ // .rcw = {}, // only for registered dimm ++ .dq_mapping = { ++ 0x16, // DQ[0:3]: lower nibble, bit order 3120 ++ 0x22, // DQ[4:7]: upper nibble, bit order 4576 ++ 0x0e, // DQ[8:11]: lower nibble, bit order 2031 ++ 0x30, // DQ[12:15]: upper nibble, bit order 6574 ++ 0x14, // DQ[16:19]: lower nibble, bit order 3021 ++ 0x36, // DQ[20:23]: upper nibble, bit order 7564 ++ 0x11, // DQ[24:27]: lower nibble, bit order 2301 ++ 0x2f, // DQ[28:31]: upper nibble, bit order 6547 ++ 0x03, // ECC[0:3]: lower nibble, bit order 0213 ++ 0x22, // ECC[4:7]: upper nibble, bit order 4576 ++ 0x10, // DQ[32:35]: lower nibble, bit order 2130 ++ 0x30, // DQ[36:39]: upper nibble, bit order 6574 ++ 0x0e, // DQ[40:43]: lower nibble, bit order 2031 ++ 0x34, // DQ[44:47]: upper nibble, bit order 7465 ++ 0x14, // DQ[48:51]: lower nibble, bit order 3021 ++ 0x36, // DQ[52:55]: upper nibble, bit order 7564 ++ 0x10, // DQ[56:59]: lower nibble, bit order 2130 ++ 0x2b, // DQ[60:63]: upper nibble, bit order 5746 ++ }, ++ .dq_mapping_ors = 1, ++}; ++#endif /* CONFIG_DDR_NODIMM == 1 */ ++ ++#if CONFIG_DDR_NODIMM == 2 ++/* ++ * SoM Revision 1.1: 9 x K4AAG085WA-BCWE (DDP, 16GB w/ ECC) ++ * ++ * Use in production for units with empty SPD, ++ * and development. ++ */ ++static const struct dimm_params static_dimm = { ++ .mpart = "Fixed DDR Config 2", ++ .n_ranks = 1, ++ .die_density = 0x6, // encoded per spd byte 4, 0b110 = 16Gbit ++ // TODO: for DDP memory should have 2 ranks per DIMM + correct density per die? ++ .rank_density = 0x400000000, // 16GB ++ .capacity = 0x400000000, // 16GB ++ .primary_sdram_width = 64, ++ .ec_sdram_width = 8, // 8 bit ecc extension ++ .rdimm = 0, ++ .package_3ds = 0, ++ .device_width = 8, // 8 bit per sdram ++ .rc = 0, ++ ++ .n_row_addr = 17, ++ .n_col_addr = 10, ++ .edc_config = 2, // enable ecc ++ .bank_addr_bits = 0, // 4 banks ++ .bank_group_bits = 2, // 4 bank groups ++ .burst_lengths_bitmask = 0xc, // enable 4 & 8-bit burst (DDR4 spec) ++ ++ .mirrored_dimm = 0, ++ ++ .mtb_ps = 125, // MTB per SPD spec ++ .ftb_10th_ps = 10, // default value, unused by nxp ddr driver ++ .taa_ps = 13750, // min. 13.75ns ++ .tfaw_ps = 30000, // min: max(30ns or 28CK) (this 16Gbit sdram has 2KB pages) ++ ++ .tckmin_x_ps = 625, // 3200 (CK=1600) ++ .tckmax_ps = 1250, // 1600 (CK=800) ++ ++ .caslat_x = 0b00000001011111111111110000000000, // CL = [10-22,24] (1 << CL) ++ ++ .trcd_ps = 13750, // 13.75ns ++ .trp_ps = 13750, // 13.75ns ++ .tras_ps = 32000, // 32ns ++ ++ .trfc1_ps = 350000, // 350ns, assumed same as 8Gbit SDP module ++ .trfc2_ps = 260000, // 260ns, assumed same as 8Gbit SDP module ++ .trfc4_ps = 160000, // 160ns, assumed same as 8Gbit SDP module ++ .trrds_ps = 5300, // min: max(4CK or 5.3ns) ++ .trrdl_ps = 6400, // min: max(4CK or 6.4ns) ++ .tccdl_ps = 5000, // min: max(5CK or 5ns) ++ .trfc_slr_ps = 0, ++ ++ .trc_ps = 45750, // tras + trp 45.75ns ++ .twr_ps = 15000, // 15ns ++ ++ .refresh_rate_ps = 7800000, // 1x mode 7.8us for standard temperature range (TODO: pick correct range based on temperature?!) ++ // .extended_op_srt = 0, ++ ++ // .rcw = {}, // only for registered dimm ++ .dq_mapping = { ++ 0x16, // DQ[0:3]: lower nibble, bit order 3120 ++ 0x22, // DQ[4:7]: upper nibble, bit order 4576 ++ 0x0e, // DQ[8:11]: lower nibble, bit order 2031 ++ 0x30, // DQ[12:15]: upper nibble, bit order 6574 ++ 0x14, // DQ[16:19]: lower nibble, bit order 3021 ++ 0x36, // DQ[20:23]: upper nibble, bit order 7564 ++ 0x11, // DQ[24:27]: lower nibble, bit order 2301 ++ 0x2f, // DQ[28:31]: upper nibble, bit order 6547 ++ 0x03, // ECC[0:3]: lower nibble, bit order 0213 ++ 0x22, // ECC[4:7]: upper nibble, bit order 4576 ++ 0x10, // DQ[32:35]: lower nibble, bit order 2130 ++ 0x30, // DQ[36:39]: upper nibble, bit order 6574 ++ 0x0e, // DQ[40:43]: lower nibble, bit order 2031 ++ 0x34, // DQ[44:47]: upper nibble, bit order 7465 ++ 0x14, // DQ[48:51]: lower nibble, bit order 3021 ++ 0x36, // DQ[52:55]: upper nibble, bit order 7564 ++ 0x10, // DQ[56:59]: lower nibble, bit order 2130 ++ 0x2b, // DQ[60:63]: upper nibble, bit order 5746 ++ }, ++ .dq_mapping_ors = 1, ++}; ++#endif /* CONFIG_DDR_NODIMM == 2 */ ++ ++int ddr_get_ddr_params(struct dimm_params *pdimm, ++ struct ddr_conf *conf) ++{ ++ // channel 1 ++ conf->dimm_in_use[0] = 1; ++ memcpy(&pdimm[0], &static_dimm, sizeof(struct dimm_params)); ++ ++ /* 1 module */ ++ return 0x1; ++} ++#endif /* defined(CONFIG_DDR_NODIMM) */ ++ ++int ddr_board_options(struct ddr_info *priv) ++{ ++ struct memctl_opt *popts = &priv->opt; ++ ++ popts->caslat_override = 0; ++ popts->caslat_override_value = 0; ++ popts->auto_self_refresh_en = 1; ++ popts->output_driver_impedance = 0; // 34 Ohm ++ popts->twot_en = 0; ++ popts->threet_en = 0; ++ popts->addt_lat_override = 0; ++ popts->addt_lat_override_value = 0; ++ popts->phy_atx_impedance = 30; ++ popts->skip2d = 0; ++ popts->vref_dimm = U(0x19); /* range 1, 83.4% */ ++ ++ popts->rtt_override = 0; ++ popts->rtt_park = 120U; ++ popts->otf_burst_chop_en = 0; ++ popts->burst_length = DDR_BL8; ++ popts->trwt_override = 1; ++ popts->bstopre = 0; /* auto precharge */ ++ popts->addr_hash = 1; ++ popts->trwt = 0x3; ++ popts->twrt = 0x3; ++ popts->trrt = 0x3; ++ popts->twwt = 0x3; ++ popts->vref_phy = U(0x5D); /* 72% */ ++ popts->odt = 60U; ++ popts->phy_tx_impedance = 28U; ++ ++ return 0; ++} ++ ++#ifdef NXP_WARM_BOOT ++long long init_ddr(uint32_t wrm_bt_flg) ++#else ++long long init_ddr(void) ++#endif ++{ ++ int spd_addr[] = { 0x51 }; ++ struct ddr_info info; ++ struct sysinfo sys; ++ long long dram_size; ++ ++ zeromem(&sys, sizeof(sys)); ++ if (get_clocks(&sys) != 0) { ++ ERROR("System clocks are not set\n"); ++ panic(); ++ } ++ debug("platform clock %lu\n", sys.freq_platform); ++ debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); ++ debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1); ++ ++ zeromem(&info, sizeof(info)); ++ ++ /* Set two DDRC. Unused DDRC will be removed automatically. */ ++ info.num_ctlrs = NUM_OF_DDRC; ++ info.spd_addr = spd_addr; ++ info.ddr[0] = (void *)NXP_DDR_ADDR; ++ info.ddr[1] = (void *)NXP_DDR2_ADDR; ++ info.phy[0] = (void *)NXP_DDR_PHY1_ADDR; ++ info.phy[1] = (void *)NXP_DDR_PHY2_ADDR; ++ info.clk = get_ddr_freq(&sys, 0); ++ info.img_loadr = load_img; ++ info.phy_gen2_fw_img_buf = PHY_GEN2_FW_IMAGE_BUFFER; ++ if (info.clk == 0) { ++ info.clk = get_ddr_freq(&sys, 1); ++ } ++ info.dimm_on_ctlr = DDRC_NUM_DIMM; ++ ++ info.warm_boot_flag = DDR_WRM_BOOT_NT_SUPPORTED; ++ ++ dram_size = dram_init(&info ++#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508) ++ , NXP_CCN_HN_F_0_ADDR ++#endif ++ ); ++ ++ ++ if (dram_size < 0) { ++ ERROR("DDR init failed.\n"); ++ } ++ ++ return dram_size; ++} +diff --git a/plat/nxp/soc-lx2160a/lx2162asom/plat_def.h b/plat/nxp/soc-lx2160a/lx2162asom/plat_def.h +new file mode 100644 +index 000000000..de2d2444a +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2162asom/plat_def.h +@@ -0,0 +1,105 @@ ++/* ++ * Copyright 2018-2021 NXP ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ */ ++ ++#ifndef PLAT_DEF_H ++#define PLAT_DEF_H ++ ++#include ++#include ++/* Required without TBBR. ++ * To include the defines for DDR PHY ++ * Images. ++ */ ++#include ++ ++#include ++#include ++ ++#if defined(IMAGE_BL31) ++#define LS_SYS_TIMCTL_BASE 0x2890000 ++#define PLAT_LS_NSTIMER_FRAME_ID 0 ++#define LS_CONFIG_CNTACR 1 ++#endif ++ ++#define NXP_SYSCLK_FREQ 100000000 ++#define NXP_DDRCLK_FREQ 100000000 ++ ++/* UART related definition */ ++#define NXP_CONSOLE_ADDR NXP_UART_ADDR ++#define NXP_CONSOLE_BAUDRATE 115200 ++ ++/* Size of cacheable stacks */ ++#if defined(IMAGE_BL2) ++#if defined(TRUSTED_BOARD_BOOT) ++#define PLATFORM_STACK_SIZE 0x2000 ++#else ++#define PLATFORM_STACK_SIZE 0x1000 ++#endif ++#elif defined(IMAGE_BL31) ++#define PLATFORM_STACK_SIZE 0x1000 ++#endif ++ ++/* SD block buffer */ ++#define NXP_SD_BLOCK_BUF_SIZE (0x8000) ++#define NXP_SD_BLOCK_BUF_ADDR (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \ ++ - NXP_SD_BLOCK_BUF_SIZE) ++ ++#ifdef SD_BOOT ++#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \ ++ - NXP_SD_BLOCK_BUF_SIZE) ++#else ++#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) ++#endif ++ ++/* IO defines as needed by IO driver framework */ ++#define MAX_IO_DEVICES 4 ++#define MAX_IO_BLOCK_DEVICES 1 ++#define MAX_IO_HANDLES 4 ++ ++#define PHY_GEN2_FW_IMAGE_BUFFER (NXP_OCRAM_ADDR + CSF_HDR_SZ) ++ ++/* ++ * FIP image defines - Offset at which FIP Image would be present ++ * Image would include Bl31 , Bl33 and Bl32 (optional) ++ */ ++#ifdef POLICY_FUSE_PROVISION ++#define MAX_FIP_DEVICES 3 ++#endif ++ ++#ifndef MAX_FIP_DEVICES ++#define MAX_FIP_DEVICES 2 ++#endif ++ ++/* ++ * ID of the secure physical generic timer interrupt used by the BL32. ++ */ ++#define BL32_IRQ_SEC_PHY_TIMER 29 ++ ++#define BL31_WDOG_SEC 89 ++ ++#define BL31_NS_WDOG_WS1 108 ++ ++/* ++ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 ++ * terminology. On a GICv2 system or mode, the lists will be merged and treated ++ * as Group 0 interrupts. ++ */ ++#define PLAT_LS_G1S_IRQ_PROPS(grp) \ ++ INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ ++ GIC_INTR_CFG_EDGE) ++ ++/* SGI 15 and Secure watchdog interrupts assigned to Group 0 */ ++#define NXP_IRQ_SEC_SGI_7 15 ++ ++#define PLAT_LS_G0_IRQ_PROPS(grp) \ ++ INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \ ++ GIC_INTR_CFG_EDGE), \ ++ INTR_PROP_DESC(BL31_NS_WDOG_WS1, GIC_HIGHEST_SEC_PRIORITY, grp, \ ++ GIC_INTR_CFG_EDGE), \ ++ INTR_PROP_DESC(NXP_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ ++ GIC_INTR_CFG_LEVEL) ++#endif +diff --git a/plat/nxp/soc-lx2160a/lx2162asom/platform.c b/plat/nxp/soc-lx2160a/lx2162asom/platform.c +new file mode 100644 +index 000000000..7622cf09a +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2162asom/platform.c +@@ -0,0 +1,29 @@ ++/* ++ * Copyright 2020 NXP ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ */ ++ ++#include ++ ++#pragma weak board_enable_povdd ++#pragma weak board_disable_povdd ++ ++bool board_enable_povdd(void) ++{ ++#ifdef CONFIG_POVDD_ENABLE ++ return true; ++#else ++ return false; ++#endif ++} ++ ++bool board_disable_povdd(void) ++{ ++#ifdef CONFIG_POVDD_ENABLE ++ return true; ++#else ++ return false; ++#endif ++} +diff --git a/plat/nxp/soc-lx2160a/lx2162asom/platform.mk b/plat/nxp/soc-lx2160a/lx2162asom/platform.mk +new file mode 100644 +index 000000000..c1ba077e9 +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2162asom/platform.mk +@@ -0,0 +1,61 @@ ++# ++# Copyright 2018-2020 NXP ++# ++# SPDX-License-Identifier: BSD-3-Clause ++# ++ ++# board-specific build parameters ++ ++BOOT_MODE ?= flexspi_nor ++BOARD ?= lx2162asom ++POVDD_ENABLE := no ++NXP_COINED_BB := no ++ ++ # DDR Compilation Configs ++NUM_OF_DDRC := 1 ++DDRC_NUM_DIMM := 1 ++DDRC_NUM_CS := 2 ++DDR_ECC_EN := yes ++ #enable address decoding feature ++DDR_ADDR_DEC := yes ++APPLY_MAX_CDD := yes ++ ++# Mock SPD: ++# - 0: disable mock spd ++# - 1: 9 x K4A8G085WC-BCWE SoM v1.1 8GB w/ ECC ++# - 2: 9 x K4AAG085WA-BCWE SoM v1.1 16GB w/ ECC ++CONFIG_DDR_NODIMM := 0 ++ ++# I2C Bus Flushing: IIC1 (SPD EEPROM) ++LX2160_FLUSH_IIC := 1, ++ ++# DDR Errata ++ERRATA_DDR_A011396 := 1 ++ERRATA_DDR_A050450 := 1 ++ ++# On-Board Flash Details ++FLASH_TYPE := MT35XU512A ++XSPI_FLASH_SZ := 0x10000000 ++NXP_XSPI_NOR_UNIT_SIZE := 0x20000 ++BL2_BIN_XSPI_NOR_END_ADDRESS := 0x100000 ++# CONFIG_FSPI_ERASE_4K is required to erase 4K sector sizes. This ++# config is enabled for future use cases. ++FSPI_ERASE_4K := 0 ++ ++# Platform specific features. ++WARM_BOOT := no ++ ++# Adding Platform files build files ++BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\ ++ ${BOARD_PATH}/platform.c ++ ++SUPPORTED_BOOT_MODE := flexspi_nor \ ++ sd \ ++ emmc \ ++ auto ++ ++# Adding platform board build info ++include plat/nxp/common/plat_make_helper/plat_common_def.mk ++ ++# Adding SoC build info ++include plat/nxp/soc-lx2160a/soc.mk +diff --git a/plat/nxp/soc-lx2160a/lx2162asom/platform_def.h b/plat/nxp/soc-lx2160a/lx2162asom/platform_def.h +new file mode 100644 +index 000000000..5fa774e90 +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2162asom/platform_def.h +@@ -0,0 +1,14 @@ ++/* ++ * Copyright 2018-2020 NXP ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ */ ++ ++#ifndef PLATFORM_DEF_H ++#define PLATFORM_DEF_H ++ ++#include "plat_def.h" ++#include "plat_default_def.h" ++ ++#endif +diff --git a/plat/nxp/soc-lx2160a/lx2162asom/policy.h b/plat/nxp/soc-lx2160a/lx2162asom/policy.h +new file mode 100644 +index 000000000..1095f3840 +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2162asom/policy.h +@@ -0,0 +1,38 @@ ++/* ++ * Copyright 2018-2020 NXP ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ */ ++ ++#ifndef POLICY_H ++#define POLICY_H ++ ++/* Following defines affect the PLATFORM SECURITY POLICY */ ++ ++/* set this to 0x0 if the platform is not using/responding to ECC errors ++ * set this to 0x1 if ECC is being used (we have to do some init) ++ */ ++#define POLICY_USING_ECC 0x0 ++ ++/* Set this to 0x0 to leave the default SMMU page size in sACR ++ * Set this to 0x1 to change the SMMU page size to 64K ++ */ ++#define POLICY_SMMU_PAGESZ_64K 0x1 ++ ++/* ++ * POLICY_PERF_WRIOP = 0 : No Performance enhancement for WRIOP RN-I ++ * POLICY_PERF_WRIOP = 1 : No Performance enhancement for WRIOP RN-I = 7 ++ * POLICY_PERF_WRIOP = 2 : No Performance enhancement for WRIOP RN-I = 23 ++ */ ++#define POLICY_PERF_WRIOP 0 ++ ++/* ++ * set this to '1' if the debug clocks need to remain enabled during ++ * system entry to low-power (LPM20) - this should only be necessary ++ * for testing and NEVER set for normal production ++ */ ++#define POLICY_DEBUG_ENABLE 0 ++ ++ ++#endif /* POLICY_H */ +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0015-lx2160acex6-add-ddr-configuration-for-pcb-v1.2-with-.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0015-lx2160acex6-add-ddr-configuration-for-pcb-v1.2-with-.patch new file mode 100644 index 000000000000..ef794f3c4413 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0015-lx2160acex6-add-ddr-configuration-for-pcb-v1.2-with-.patch @@ -0,0 +1,127 @@ +From 319f6d2f0cbbb54ac56926683c5e0dfefe984e64 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sun, 24 Nov 2024 12:38:17 +0100 +Subject: [PATCH] lx2160acex6: add ddr configuration for pcb v1.2 with ecc + +Tune DDR Configuration for v1.1 PCB with MIcron memory, and v1.2 PCB +resolving ECC issues. + +Signed-off-by: Josua Mayer +--- + plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c | 42 +++++++++++++------- + plat/nxp/soc-lx2160a/lx2160acex6/platform.mk | 3 +- + 2 files changed, 29 insertions(+), 16 deletions(-) + +diff --git a/plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c b/plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c +index 0b978e298..61acfd7ac 100644 +--- a/plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c ++++ b/plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c +@@ -31,21 +31,29 @@ + #error Not implemented. + #endif /* CONFIG_DDR_NODIMM == 1 */ + +-#if CONFIG_DDR_NODIMM == 2 ++#if CONFIG_DDR_NODIMM == 2 || CONFIG_DDR_NODIMM == 3 + /* +- * PCB Revision 1.1: 2 x 5 x K4A8G165WB-BCRC +- * +- * ECC disabled because of training failures. ++ * PCB Revision 1.1/1.2: 2 x 5 x MT40A1G16TB-062E IT:F + */ + #define CONFIG_DDR_NODIMM_CH2 ++ ++#if CONFIG_DDR_NODIMM == 3 ++/* PCB Revision 1.2 supports ECC */ ++#define CONFIG_DDR_NODIMM_ECC ++#endif /* CONFIG_DDR_NODIMM == 3 */ ++ + static const struct dimm_params static_dimm = { +- .mpart = "Fixed DDR Config 2", ++ .mpart = "Fixed DDR Config " __XSTRING(CONFIG_DDR_NODIMM), + .n_ranks = 1, + .die_density = 0x6, // encoded per spd byte 4, 0b110 = 16Gbit +- .rank_density = 0x200000000, // 16GB +- .capacity = 0x200000000, // 16GB ++ .rank_density = 0x200000000, // 16Gbit ++ .capacity = 0x200000000, // 16Gbit + .primary_sdram_width = 64, ++#ifdef CONFIG_DDR_NODIMM_ECC ++ .ec_sdram_width = 8, // 8 bit ecc extension ++#else + .ec_sdram_width = 0, // no ecc extension ++#endif + .rdimm = 0, + .package_3ds = 0, + .device_width = 16, // 16 bit per sdram +@@ -53,26 +61,30 @@ static const struct dimm_params static_dimm = { + + .n_row_addr = 17, + .n_col_addr = 10, ++#ifdef CONFIG_DDR_NODIMM_ECC ++ .edc_config = 2, // enable ecc ++#else + .edc_config = 0, // disable ecc ++#endif + .bank_addr_bits = 0, // 4 banks + .bank_group_bits = 1, // 2 bank groups + .burst_lengths_bitmask = 0xc, // enable 4 & 8-bit burst (DDR4 spec) + + .mirrored_dimm = 0, + +- // timings based on K4A8G085WC-BCTD (DDR4-2666), missing values for 3200 ++ // timings based on MT40A4G4 / MT40A2G8 / MT40A1G16 datasheet (DDR4-3200 22-22-22) + .mtb_ps = 125, // MTB per SPD spec + .ftb_10th_ps = 10, // default value, unused by nxp ddr driver + .taa_ps = 13750, // min. 13.75ns +- .tfaw_ps = 30000, // min: max(30ns or 28CK) (this 16Gbit sdram has 2KB pages) ++ .tfaw_ps = 30000, // min: max(30ns or 28CK) (this 8Gbit sdram has 2KB pages) + +- .tckmin_x_ps = 625, // 3200 (CK=1600) ++ .tckmin_x_ps = 625, // 2400 (CK=1600) + .tckmax_ps = 1250, // 1600 (CK=800) + +- .caslat_x = 0b00000001010101010101010000000000, // CL = [10,12,14,16,18,20,22,24] (1 << CL) ++ .caslat_x = 0b00000001011111111111110000000000, // CL = [10-22,24] (1 << CL) + +- .trcd_ps = 13750, // 13.75ns - CL22-22-22 +- .trp_ps = 13750, // 13.75ns - CL22-22-22 ++ .trcd_ps = 13750, // 13.75ns ++ .trp_ps = 13750, // 13.75ns + .tras_ps = 32000, // 32ns + + .trfc1_ps = 350000, // 350ns, +@@ -100,7 +112,7 @@ static const struct dimm_params static_dimm = { + 0x00, + 0x20, + 0x00, +- 0x00, ++ 0x02, + 0x00, + 0x20, + 0x00, +@@ -112,7 +124,7 @@ static const struct dimm_params static_dimm = { + }, + .dq_mapping_ors = 1, + }; +-#endif /* CONFIG_DDR_NODIMM == 2 */ ++#endif /* CONFIG_DDR_NODIMM == 2 || CONFIG_DDR_NODIMM == 3 */ + + int ddr_get_ddr_params(struct dimm_params *pdimm, + struct ddr_conf *conf) +diff --git a/plat/nxp/soc-lx2160a/lx2160acex6/platform.mk b/plat/nxp/soc-lx2160a/lx2160acex6/platform.mk +index 950207878..d01a41ea6 100644 +--- a/plat/nxp/soc-lx2160a/lx2160acex6/platform.mk ++++ b/plat/nxp/soc-lx2160a/lx2160acex6/platform.mk +@@ -22,7 +22,8 @@ APPLY_MAX_CDD := yes + + # Mock SPD: + # - 0: disable mock spd +-# - 2: 2 x 5 x K4A8G165WB-BCRC PCB v1.1 ++# - 2: 2 x 5 x MT40A1G16TB-062E IT:F PCB v1.1 ++# - 3: 2 x 5 x MT40A1G16TB-062E IT:F PCB v1.2 (with ECC) + CONFIG_DDR_NODIMM := 0 + + # S5 GPIO +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0016-nxp-ddr-add-debug-output-for-dimm-parameters-parsed-.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0016-nxp-ddr-add-debug-output-for-dimm-parameters-parsed-.patch new file mode 100644 index 000000000000..69280da6cf2d --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0016-nxp-ddr-add-debug-output-for-dimm-parameters-parsed-.patch @@ -0,0 +1,83 @@ +From 0591394c1257b79d9d49016476325533c1c2a14a Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Thu, 26 Sep 2024 16:35:40 +0200 +Subject: [PATCH 16/17] nxp: ddr: add debug output for dimm parameters parsed + from spd or static + +Add debug prints for all members of struct dimm_params, after either +parsing of SPD - or from static (no-dimm) configuration. + +This enables comparison of parameters derived from SPD with static +configuration. + +Signed-off-by: Josua Mayer +--- + drivers/nxp/ddr/nxp-ddr/ddr.c | 52 +++++++++++++++++++++++++++++++++++ + 1 file changed, 52 insertions(+) + +diff --git a/drivers/nxp/ddr/nxp-ddr/ddr.c b/drivers/nxp/ddr/nxp-ddr/ddr.c +index c051b3b25..91a6ef5dc 100644 +--- a/drivers/nxp/ddr/nxp-ddr/ddr.c ++++ b/drivers/nxp/ddr/nxp-ddr/ddr.c +@@ -616,6 +616,58 @@ static int parse_spd(struct ddr_info *priv) + /* now we have valid and identical DIMMs on controllers */ + #endif /* CONFIG_DDR_NODIMM */ + ++ debug("DIMM: n_ranks = %u\n", dimm->n_ranks); ++ debug("DIMM: die_density = %u\n", dimm->die_density); ++ debug("DIMM: rank_density = %llu\n", dimm->rank_density); ++ debug("DIMM: capacity = %llu\n", dimm->capacity); ++ debug("DIMM: primary_sdram_width = %u\n", dimm->primary_sdram_width); ++ debug("DIMM: ec_sdram_width = %u\n", dimm->ec_sdram_width); ++ debug("DIMM: rdimm = %u\n", dimm->rdimm); ++ debug("DIMM: package_3ds = %u\n", dimm->package_3ds); ++ debug("DIMM: device_width = %u\n", dimm->device_width); ++ debug("DIMM: rc = %u\n", dimm->rc); ++ ++ debug("DIMM: n_row_addr = %u\n", dimm->n_row_addr); ++ debug("DIMM: n_col_addr = %u\n", dimm->n_col_addr); ++ debug("DIMM: edc_config = %u\n", dimm->edc_config); ++ debug("DIMM: bank_addr_bits = %u\n", dimm->bank_addr_bits); ++ debug("DIMM: bank_group_bits = %u\n", dimm->bank_group_bits); ++ debug("DIMM: burst_lengths_bitmask = %u\n", dimm->burst_lengths_bitmask); ++ ++ debug("DIMM: mirrored_dimm = %u\n", dimm->mirrored_dimm); ++ ++ debug("DIMM: mtb_ps = %d\n", dimm->mtb_ps); ++ debug("DIMM: ftb_10th_ps = %d\n", dimm->ftb_10th_ps); ++ debug("DIMM: taa_ps = %d\n", dimm->taa_ps); ++ debug("DIMM: tfaw_ps = %d\n", dimm->tfaw_ps); ++ ++ debug("DIMM: tckmin_x_ps = %d\n", dimm->tckmin_x_ps); ++ debug("DIMM: tckmax_ps = %d\n", dimm->tckmax_ps); ++ ++ debug("DIMM: caslat_x = %u\n", dimm->caslat_x); ++ ++ debug("DIMM: trcd_ps = %d\n", dimm->trcd_ps); ++ debug("DIMM: trp_ps = %d\n", dimm->trp_ps); ++ debug("DIMM: tras_ps = %d\n", dimm->tras_ps); ++ ++ debug("DIMM: trfc1_ps = %d\n", dimm->trfc1_ps); ++ debug("DIMM: trfc2_ps = %d\n", dimm->trfc2_ps); ++ debug("DIMM: trfc4_ps = %d\n", dimm->trfc4_ps); ++ debug("DIMM: trrds_ps = %d\n", dimm->trrds_ps); ++ debug("DIMM: trrdl_ps = %d\n", dimm->trrdl_ps); ++ debug("DIMM: tccdl_ps = %d\n", dimm->tccdl_ps); ++ debug("DIMM: trfc_slr_ps = %d\n", dimm->trfc_slr_ps); ++ ++ debug("DIMM: trc_ps = %d\n", dimm->trc_ps); ++ debug("DIMM: twr_ps = %d\n", dimm->twr_ps); ++ ++ debug("DIMM: refresh_rate_ps = %u\n", dimm->refresh_rate_ps); ++ debug("DIMM: extended_op_srt = %u\n", dimm->extended_op_srt); ++ ++ debug("DIMM: rcw = [%u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u]\n", (unsigned int)dimm->rcw[0], (unsigned int)dimm->rcw[1], (unsigned int)dimm->rcw[2], (unsigned int)dimm->rcw[3], (unsigned int)dimm->rcw[4], (unsigned int)dimm->rcw[5], (unsigned int)dimm->rcw[6], (unsigned int)dimm->rcw[7], (unsigned int)dimm->rcw[8], (unsigned int)dimm->rcw[9], (unsigned int)dimm->rcw[10], (unsigned int)dimm->rcw[11], (unsigned int)dimm->rcw[12], (unsigned int)dimm->rcw[13], (unsigned int)dimm->rcw[14], (unsigned int)dimm->rcw[15]); ++ debug("DIMM: dq_mapping = [%u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u]\n", dimm->dq_mapping[0], dimm->dq_mapping[1], dimm->dq_mapping[2], dimm->dq_mapping[3], dimm->dq_mapping[4], dimm->dq_mapping[5], dimm->dq_mapping[6], dimm->dq_mapping[7], dimm->dq_mapping[8], dimm->dq_mapping[9], dimm->dq_mapping[10], dimm->dq_mapping[11], dimm->dq_mapping[12], dimm->dq_mapping[13], dimm->dq_mapping[14], dimm->dq_mapping[15], dimm->dq_mapping[16], dimm->dq_mapping[17]); ++ debug("DIMM: dq_mapping_ors = %u\n", dimm->dq_mapping_ors); ++ + debug("cal cs\n"); + conf->cs_in_use = 0; + for (j = 0; j < DDRC_NUM_DIMM; j++) { +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0017-lx2160acex6-fix-dq-mapping-and-remove-invalid-spd-ee.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0017-lx2160acex6-fix-dq-mapping-and-remove-invalid-spd-ee.patch new file mode 100644 index 000000000000..71beb94477d9 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0017-lx2160acex6-fix-dq-mapping-and-remove-invalid-spd-ee.patch @@ -0,0 +1,36 @@ +From 65eaf1b55184950c67cb07156477418e93fa9351 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Tue, 26 Nov 2024 14:37:27 +0100 +Subject: [PATCH 17/17] lx2160acex6: fix dq mapping and remove invalid spd + eeprom addresses + +Signed-off-by: Josua Mayer +--- + plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c b/plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c +index 61acfd7ac..95c0a13cf 100644 +--- a/plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c ++++ b/plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c +@@ -112,7 +112,7 @@ static const struct dimm_params static_dimm = { + 0x00, + 0x20, + 0x00, +- 0x02, ++ 0x20, + 0x00, + 0x20, + 0x00, +@@ -200,7 +200,7 @@ int ddr_board_options(struct ddr_info *priv) + + long long init_ddr(void) + { +- int spd_addr[] = { 0x51, 0x52, 0x53, 0x54 }; ++ int spd_addr[] = { 0x51, 0x00, 0x53, 0x00 }; + struct ddr_info info; + struct sysinfo sys; + long long dram_size; +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0018-feat-build-add-support-for-new-binutils-versions.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0018-feat-build-add-support-for-new-binutils-versions.patch new file mode 120000 index 000000000000..5ef794304fba --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0018-feat-build-add-support-for-new-binutils-versions.patch @@ -0,0 +1 @@ +../../../../freescale/common/patches/arm-trusted-firmware/0001-feat-build-add-support-for-new-binutils-versions.patch \ No newline at end of file From patchwork Sun Dec 8 14:37:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit 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h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8LVl6OunxM1gAN1SORJZ8GM8uoaCPncXnaEzhQvipnU=; b=IFgxs31YsFAzUJCSK7OmUaaQddx36qeoW09D56MfFv/za/ehmLwLzG9W6coARCWz6s PIjr7YDWQkAaHZhRXddxNP6RxwkyU6K1/Q/Z/v+JdOIdF2tXwQSlelWikIJfx76ZnoUb c+omp9Jk682e7F/48INlz0tN2w7lyijrbI5PbGw2YAkNdRuQq1nfv41ij02Y9MLKfnH2 6nEzZrX6EWFf/v8dgStATdKsvQwIAdNCi/dNmNuMOyv4A+B94X8Qs434tpFo1zfocuaw xFYIQY97mefVjIcf8FZ6AzcSlYIyuu2ETVlhlkNXqlApmYsiZQ8HFYCm81rV2BrORqW0 7jBA== X-Mailman-Original-Authentication-Results: smtp1.osuosl.org; dmarc=pass (p=none dis=none) header.from=gmail.com X-Mailman-Original-Authentication-Results: smtp1.osuosl.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=IFgxs31Y Subject: [Buildroot] [PATCH v2 08/11] board/lx2160acex7: Add qoriq-mc-utils patches X-BeenThere: buildroot@buildroot.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: buildroot-bounces@buildroot.org Sender: "buildroot" The DPL and DPC files are necessary for configuring the DPAA2 network objects. We include as-is all the Solidrun patches, but the defconfig only uses lx2160a/LX2160A-CEX7/clearfog-cx-s1_8-s2_0-{dpl,dpc}.dtb. Signed-off-by: Vladimir Oltean --- v1->v2: - split out from previous [PATCH 6/7] board/lx2160acex7: new platform ...x2160-cex7-based-clearfog-cx-dpl-dpc.patch | 937 +++++ ...160-cex6-based-evaluation-board-dpl-.patch | 1454 +++++++ ...n-for-lx2162a-som-and-clearfog-board.patch | 3622 +++++++++++++++++ ...som-clearfog-enable-dpni-connections.patch | 188 + ...rfog-cx-configure-qsfp-ports-type-ph.patch | 52 + 5 files changed, 6253 insertions(+) create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-mc-utils/0001-add-solidrun-lx2160-cex7-based-clearfog-cx-dpl-dpc.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-mc-utils/0002-add-solidrun-lx2160-cex6-based-evaluation-board-dpl-.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-mc-utils/0003-add-configuration-for-lx2162a-som-and-clearfog-board.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-mc-utils/0004-lx2162-som-clearfog-enable-dpni-connections.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-mc-utils/0005-lx2160acex7-clearfog-cx-configure-qsfp-ports-type-ph.patch diff --git a/board/solidrun/lx2160acex7/patches/qoriq-mc-utils/0001-add-solidrun-lx2160-cex7-based-clearfog-cx-dpl-dpc.patch b/board/solidrun/lx2160acex7/patches/qoriq-mc-utils/0001-add-solidrun-lx2160-cex7-based-clearfog-cx-dpl-dpc.patch new file mode 100644 index 000000000000..5dd2cd638d88 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-mc-utils/0001-add-solidrun-lx2160-cex7-based-clearfog-cx-dpl-dpc.patch @@ -0,0 +1,937 @@ +From 24334396edb16fbebe5f0b07a8264d53493dbff4 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Fri, 28 Jun 2024 19:16:57 +0200 +Subject: [PATCH] add solidrun lx2160 cex7 based clearfog-cx dpl/dpc + +Signed-off-by: Josua Mayer +--- + .../clearfog-cx-s1_8-s2_0-dpc.dts | 108 ++++ + .../clearfog-cx-s1_8-s2_0-dpl.dts | 556 ++++++++++++++++++ + .../LX2160A-CEX7/null-s1_0-s2_0-dpc.dts | 72 +++ + .../LX2160A-CEX7/null-s1_0-s2_0-dpl.dts | 157 +++++ + 4 files changed, 893 insertions(+) + create mode 100644 config/lx2160a/LX2160A-CEX7/clearfog-cx-s1_8-s2_0-dpc.dts + create mode 100644 config/lx2160a/LX2160A-CEX7/clearfog-cx-s1_8-s2_0-dpl.dts + create mode 100644 config/lx2160a/LX2160A-CEX7/null-s1_0-s2_0-dpc.dts + create mode 100644 config/lx2160a/LX2160A-CEX7/null-s1_0-s2_0-dpl.dts + +diff --git a/config/lx2160a/LX2160A-CEX7/clearfog-cx-s1_8-s2_0-dpc.dts b/config/lx2160a/LX2160A-CEX7/clearfog-cx-s1_8-s2_0-dpc.dts +new file mode 100644 +index 0000000..dcc376e +--- /dev/null ++++ b/config/lx2160a/LX2160A-CEX7/clearfog-cx-s1_8-s2_0-dpc.dts +@@ -0,0 +1,108 @@ ++/* ++ * Copyright 2018 NXP ++ * Copyright 2022 Josua Mayer ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of the above-listed copyright holders nor the ++ * names of any contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/* ++ * This DPC configures SolidRun Clearfog-CX with 8x10Gbps SerDes & 1Gbps RGMII ports. ++ */ ++ ++/dts-v1/; ++ ++/ { ++ resources { ++ icid_pools { ++ ++ icid_pool@1 { ++ num = <0x64>; ++ base_icid = <0x0>; ++ }; ++ }; ++ }; ++ ++ mc_general { ++ log { ++ mode = "LOG_MODE_ON"; ++ level = "LOG_LEVEL_WARNING"; ++ }; ++ ++ console { ++ mode = "CONSOLE_MODE_OFF"; ++ uart_id = <0x4>; ++ level = "LOG_LEVEL_WARNING"; ++ }; ++ }; ++ ++ controllers { ++ qbman { ++ /* Transform this number of 8-WQ channels into four times ++ * as many 2-WQ channels. This allows the creation of a ++ * larger number of DPCONs. ++ */ ++ wq_ch_conversion = <32>; ++ }; ++ }; ++ ++ board_info { ++ ports { ++ mac@3 { ++ link_type = "MAC_LINK_TYPE_FIXED"; ++ }; ++ ++ mac@4 { ++ link_type = "MAC_LINK_TYPE_FIXED"; ++ }; ++ ++ mac@5 { ++ link_type = "MAC_LINK_TYPE_FIXED"; ++ }; ++ ++ mac@6 { ++ link_type = "MAC_LINK_TYPE_FIXED"; ++ }; ++ ++ mac@7 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@8 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@9 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@10 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@17 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ }; ++ }; ++}; +diff --git a/config/lx2160a/LX2160A-CEX7/clearfog-cx-s1_8-s2_0-dpl.dts b/config/lx2160a/LX2160A-CEX7/clearfog-cx-s1_8-s2_0-dpl.dts +new file mode 100644 +index 0000000..e91f837 +--- /dev/null ++++ b/config/lx2160a/LX2160A-CEX7/clearfog-cx-s1_8-s2_0-dpl.dts +@@ -0,0 +1,556 @@ ++/* ++ * Copyright 2018 NXP ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of the above-listed copyright holders nor the ++ * names of any contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++/ { ++ dpl-version = <10>; ++ /***************************************************************** ++ * Containers ++ *****************************************************************/ ++ containers { ++ ++ dprc@1 { ++ compatible = "fsl,dprc"; ++ parent = "none"; ++ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_OBJ_CREATE_ALLOWED", "DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED"; ++ ++ objects { ++ ++ /* -------------- DPBPs --------------*/ ++ obj_set@dpbp { ++ type = "dpbp"; ++ ids = <0 >; ++ }; ++ ++ /* -------------- DPCONs --------------*/ ++ obj_set@dpcon { ++ type = "dpcon"; ++ ids = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >; ++ }; ++ ++ /* -------------- DPIOs --------------*/ ++ obj_set@dpio { ++ type = "dpio"; ++ ids = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >; ++ }; ++ ++ /* -------------- DPMACs --------------*/ ++ obj_set@dpmac { ++ type = "dpmac"; ++ ids = <3 4 5 6 7 8 9 10 17 >; ++ }; ++ ++ /* -------------- DPMCPs --------------*/ ++ obj_set@dpmcp { ++ type = "dpmcp"; ++ ids = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 >; ++ }; ++ ++ /* -------------- DPNIs --------------*/ ++ obj_set@dpni { ++ type = "dpni"; ++ ids = <0 >; ++ }; ++ ++ /* -------------- DPRTCs --------------*/ ++ obj_set@dprtc { ++ type = "dprtc"; ++ ids = <0 >; ++ }; ++ ++ /* -------------- DPSECIs --------------*/ ++ obj_set@dpseci { ++ type = "dpseci"; ++ ids = <0 >; ++ }; ++ }; ++ }; ++ }; ++ ++ /***************************************************************** ++ * Objects ++ *****************************************************************/ ++ objects { ++ ++ dpbp@0 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpcon@0 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@1 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@2 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@3 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@4 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@5 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@6 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@7 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@8 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@9 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@10 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@11 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@12 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@13 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@14 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@15 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpio@0 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@1 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@2 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@3 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@4 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@5 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@6 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@7 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@8 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@9 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@10 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@11 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@12 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@13 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@14 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@15 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpmac@3 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@4 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@5 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@6 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@7 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@8 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@9 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@10 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@17 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmcp@1 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@2 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@3 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@4 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@5 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@6 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@7 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@8 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@9 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@10 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@11 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@12 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@13 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@14 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@15 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@16 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@17 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@18 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@19 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@20 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@21 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@22 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@23 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@24 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@25 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@26 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@27 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@28 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@29 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@30 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@31 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@32 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@33 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@34 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@35 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@36 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@37 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@38 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@39 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@40 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@41 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@42 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@43 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@44 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@45 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@46 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@47 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@48 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@49 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@50 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@51 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@52 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpni@0 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ }; ++ ++ dprtc@0 { ++ compatible = "fsl,dprtc"; ++ }; ++ ++ dpseci@0 { ++ compatible = "fsl,dpseci"; ++ priorities = <1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1>; ++ }; ++ }; ++ ++ /***************************************************************** ++ * Connections ++ *****************************************************************/ ++ connections { ++ ++ connection@1{ ++ endpoint1 = "dpni@0"; ++ endpoint2 = "dpmac@17"; ++ }; ++ }; ++}; +diff --git a/config/lx2160a/LX2160A-CEX7/null-s1_0-s2_0-dpc.dts b/config/lx2160a/LX2160A-CEX7/null-s1_0-s2_0-dpc.dts +new file mode 100644 +index 0000000..ac707bc +--- /dev/null ++++ b/config/lx2160a/LX2160A-CEX7/null-s1_0-s2_0-dpc.dts +@@ -0,0 +1,72 @@ ++/* ++ * Copyright 2018 NXP ++ * Copyright 2022 Josua Mayer ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of the above-listed copyright holders nor the ++ * names of any contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/* ++* This DPC is a bare example without networking. ++*/ ++ ++/dts-v1/; ++ ++/ { ++ resources { ++ icid_pools { ++ icid_pool@1 { ++ num = <0x64>; ++ base_icid = <0x0>; ++ }; ++ }; ++ }; ++ ++ mc_general { ++ log { ++ mode = "LOG_MODE_ON"; ++ level = "LOG_LEVEL_WARNING"; ++ }; ++ ++ console { ++ mode = "CONSOLE_MODE_OFF"; ++ uart_id = <0x4>; ++ level = "LOG_LEVEL_WARNING"; ++ }; ++ }; ++ ++ controllers { ++ qbman { ++ /* Transform this number of 8-WQ channels into four times ++ * as many 2-WQ channels. This allows the creation of a ++ * larger number of DPCONs. ++ */ ++ wq_ch_conversion = <32>; ++ }; ++ }; ++ ++ board_info { ++ ports { ++ }; ++ }; ++}; +diff --git a/config/lx2160a/LX2160A-CEX7/null-s1_0-s2_0-dpl.dts b/config/lx2160a/LX2160A-CEX7/null-s1_0-s2_0-dpl.dts +new file mode 100644 +index 0000000..9847cc3 +--- /dev/null ++++ b/config/lx2160a/LX2160A-CEX7/null-s1_0-s2_0-dpl.dts +@@ -0,0 +1,157 @@ ++/* ++ * Copyright 2020 NXP ++ * Copyright 2022 Josua Mayer ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of the above-listed copyright holders nor the ++ * names of any contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++/ { ++ dpl-version = <10>; ++ ++ containers { ++ dprc@1 { ++ compatible = "fsl,dprc"; ++ parent = "none"; ++ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_OBJ_CREATE_ALLOWED", "DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED"; ++ ++ objects { ++ obj_set@dpmcp { ++ type = "dpmcp"; ++ ids = <0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23>; ++ }; ++ }; ++ }; ++ }; ++ ++ objects { ++ dpmcp@1 { ++ }; ++ ++ dpmcp@2 { ++ }; ++ ++ dpmcp@3 { ++ }; ++ ++ dpmcp@4 { ++ }; ++ ++ dpmcp@5 { ++ }; ++ ++ dpmcp@6 { ++ }; ++ ++ dpmcp@7 { ++ }; ++ ++ dpmcp@8 { ++ }; ++ ++ dpmcp@9 { ++ }; ++ ++ dpmcp@10 { ++ }; ++ ++ dpmcp@11 { ++ }; ++ ++ dpmcp@12 { ++ }; ++ ++ dpmcp@13 { ++ }; ++ ++ dpmcp@14 { ++ }; ++ ++ dpmcp@15 { ++ }; ++ ++ dpmcp@16 { ++ }; ++ ++ dpmcp@17 { ++ }; ++ ++ dpmcp@18 { ++ }; ++ ++ dpmcp@19 { ++ }; ++ ++ dpmcp@20 { ++ }; ++ ++ dpmcp@21 { ++ }; ++ ++ dpmcp@22 { ++ }; ++ ++ dpmcp@23 { ++ }; ++ ++ dpmcp@24 { ++ }; ++ ++ dpmcp@25 { ++ }; ++ ++ dpmcp@26 { ++ }; ++ ++ dpmcp@27 { ++ }; ++ ++ dpmcp@28 { ++ }; ++ ++ dpmcp@29 { ++ }; ++ ++ dpmcp@30 { ++ }; ++ ++ dpmcp@31 { ++ }; ++ ++ dpmcp@32 { ++ }; ++ ++ dpmcp@33 { ++ }; ++ ++ dpmcp@34 { ++ }; ++ ++ dpmcp@35 { ++ }; ++ }; ++ ++ connections { ++ }; ++}; +-- +2.35.3 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-mc-utils/0002-add-solidrun-lx2160-cex6-based-evaluation-board-dpl-.patch b/board/solidrun/lx2160acex7/patches/qoriq-mc-utils/0002-add-solidrun-lx2160-cex6-based-evaluation-board-dpl-.patch new file mode 100644 index 000000000000..195ee20851f3 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-mc-utils/0002-add-solidrun-lx2160-cex6-based-evaluation-board-dpl-.patch @@ -0,0 +1,1454 @@ +From 8933c2fac644bd9e4553bee466fab6d11a0b661a Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sun, 13 Oct 2024 11:59:53 +0200 +Subject: [PATCH] add solidrun lx2160 cex6 based evaluation board dpl/dpc + +Signed-off-by: Josua Mayer +--- + .../LX2160A-CEX6/evb-s1_3-s2_0-dpc.dts | 99 ++ + .../LX2160A-CEX6/evb-s1_3-s2_0-dpl.dts | 1327 +++++++++++++++++ + 2 files changed, 1426 insertions(+) + create mode 100644 config/lx2160a/LX2160A-CEX6/evb-s1_3-s2_0-dpc.dts + create mode 100644 config/lx2160a/LX2160A-CEX6/evb-s1_3-s2_0-dpl.dts + +diff --git a/config/lx2160a/LX2160A-CEX6/evb-s1_3-s2_0-dpc.dts b/config/lx2160a/LX2160A-CEX6/evb-s1_3-s2_0-dpc.dts +new file mode 100644 +index 0000000..46cdca1 +--- /dev/null ++++ b/config/lx2160a/LX2160A-CEX6/evb-s1_3-s2_0-dpc.dts +@@ -0,0 +1,99 @@ ++/* ++ * Copyright 2018 NXP ++ * Copyright 2024 Josua Mayer ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of the above-listed copyright holders nor the ++ * names of any contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++ ++/ { ++ resources { ++ icid_pools { ++ icid_pool@1 { ++ num = <0x64>; ++ base_icid = <0x0>; ++ }; ++ }; ++ }; ++ ++ mc_general { ++ log { ++ mode = "LOG_MODE_ON"; ++ level = "LOG_LEVEL_WARNING"; ++ }; ++ ++ console { ++ mode = "CONSOLE_MODE_OFF"; ++ uart_id = <0x4>; ++ level = "LOG_LEVEL_WARNING"; ++ }; ++ }; ++ ++ controllers { ++ qbman { ++ /* Transform this number of 8-WQ channels into four times ++ * as many 2-WQ channels. This allows the creation of a ++ * larger number of DPCONs. ++ */ ++ wq_ch_conversion = <64>; ++ }; ++ }; ++ ++ board_info { ++ recycle_ports { ++ recycle@1 { ++ max_rate = "1G"; ++ }; ++ ++ recycle@2 { ++ max_rate = "1G"; ++ }; ++ }; ++ ++ ports { ++ /* Serdes 1 */ ++ mac@3 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@4 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@5 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@6 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ /* WRIOP MAC */ ++ mac@17 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ }; ++ }; ++}; +diff --git a/config/lx2160a/LX2160A-CEX6/evb-s1_3-s2_0-dpl.dts b/config/lx2160a/LX2160A-CEX6/evb-s1_3-s2_0-dpl.dts +new file mode 100644 +index 0000000..1840af4 +--- /dev/null ++++ b/config/lx2160a/LX2160A-CEX6/evb-s1_3-s2_0-dpl.dts +@@ -0,0 +1,1327 @@ ++/* ++ * Copyright 2018 NXP ++ * Copyright 2024 Josua Mayer ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of the above-listed copyright holders nor the ++ * names of any contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++/ { ++ dpl-version = <10>; ++ /***************************************************************** ++ * Containers ++ *****************************************************************/ ++ containers { ++ ++ dprc@1 { ++ compatible = "fsl,dprc"; ++ parent = "none"; ++ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_OBJ_CREATE_ALLOWED", "DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED"; ++ ++ objects { ++ ++ /* -------------- DPBPs --------------*/ ++ obj_set@dpbp { ++ type = "dpbp"; ++ ids = <0 1 2 3 4 5 6 7 8 >; ++ }; ++ ++ /* -------------- DPCONs --------------*/ ++ obj_set@dpcon { ++ type = "dpcon"; ++ ids = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 >; ++ }; ++ ++ /* -------------- DPIOs --------------*/ ++ obj_set@dpio { ++ type = "dpio"; ++ ids = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >; ++ }; ++ ++ /* -------------- DPMACs --------------*/ ++ obj_set@dpmac { ++ type = "dpmac"; ++ ids = <3 4 5 6 17 >; ++ }; ++ ++ /* -------------- DPMCPs --------------*/ ++ obj_set@dpmcp { ++ type = "dpmcp"; ++ ids = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 >; ++ }; ++ ++ /* -------------- DPNIs --------------*/ ++ obj_set@dpni { ++ type = "dpni"; ++ ids = <0 1 2 3 4 >; ++ }; ++ ++ /* -------------- DPRTCs --------------*/ ++ obj_set@dprtc { ++ type = "dprtc"; ++ ids = <0 >; ++ }; ++ ++ /* -------------- DPSECIs --------------*/ ++ obj_set@dpseci { ++ type = "dpseci"; ++ ids = <0 >; ++ }; ++ }; ++ }; ++ }; ++ ++ /***************************************************************** ++ * Objects ++ *****************************************************************/ ++ objects { ++ ++ dpbp@0 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@1 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@2 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@3 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@4 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@5 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@6 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@7 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@8 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpcon@0 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@1 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@2 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@3 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@4 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@5 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@6 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@7 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@8 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@9 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@10 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@11 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@12 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@13 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@14 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@15 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@16 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@17 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@18 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@19 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@20 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@21 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@22 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@23 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@24 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@25 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@26 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@27 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@28 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@29 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@30 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@31 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@32 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@33 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@34 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@35 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@36 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@37 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@38 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@39 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@40 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@41 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@42 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@43 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@44 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@45 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@46 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@47 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@48 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@49 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@50 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@51 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@52 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@53 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@54 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@55 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@56 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@57 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@58 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@59 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@60 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@61 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@62 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@63 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@64 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@65 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@66 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@67 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@68 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@69 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@70 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@71 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@72 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@73 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@74 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@75 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@76 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@77 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@78 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@79 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@80 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@81 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@82 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@83 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@84 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@85 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@86 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@87 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@88 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@89 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@90 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@91 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@92 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@93 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@94 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@95 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@96 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@97 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@98 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@99 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@100 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@101 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@102 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@103 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@104 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@105 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@106 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@107 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@108 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@109 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@110 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@111 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@112 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@113 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@114 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@115 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@116 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@117 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@118 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@119 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@120 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@121 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@122 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@123 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@124 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@125 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@126 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@127 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@128 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@129 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@130 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@131 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@132 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@133 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@134 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@135 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@136 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@137 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@138 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@139 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@140 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@141 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@142 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@143 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpio@0 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@1 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@2 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@3 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@4 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@5 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@6 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@7 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@8 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@9 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@10 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@11 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@12 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@13 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@14 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@15 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpmac@3 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@4 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@5 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@6 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@17 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmcp@1 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@2 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@3 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@4 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@5 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@6 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@7 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@8 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@9 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@10 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@11 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@12 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@13 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@14 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@15 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@16 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@17 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@18 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@19 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@20 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@21 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@22 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@23 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@24 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@25 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@26 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@27 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@28 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@29 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@30 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@31 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@32 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@33 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@34 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@35 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@36 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@37 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@38 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@39 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@40 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@41 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@42 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@43 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@44 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@45 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@46 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@47 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@48 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@49 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@50 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@51 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@52 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@53 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@54 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@55 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@56 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@57 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@58 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@59 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@60 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpni@0 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@1 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@2 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@3 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@4 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dprtc@0 { ++ compatible = "fsl,dprtc"; ++ }; ++ ++ dpseci@0 { ++ compatible = "fsl,dpseci"; ++ priorities = <1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1>; ++ }; ++ }; ++ ++ /***************************************************************** ++ * Connections ++ *****************************************************************/ ++ connections { ++ ++ connection@1{ ++ endpoint1 = "dpni@4"; ++ endpoint2 = "dpmac@17"; ++ }; ++ ++ connection@2{ ++ endpoint1 = "dpni@3"; ++ endpoint2 = "dpmac@3"; ++ }; ++ ++ connection@3{ ++ endpoint1 = "dpni@2"; ++ endpoint2 = "dpmac@4"; ++ }; ++ ++ connection@4{ ++ endpoint1 = "dpni@1"; ++ endpoint2 = "dpmac@5"; ++ }; ++ ++ connection@5{ ++ endpoint1 = "dpni@0"; ++ endpoint2 = "dpmac@6"; ++ }; ++ }; ++}; +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-mc-utils/0003-add-configuration-for-lx2162a-som-and-clearfog-board.patch b/board/solidrun/lx2160acex7/patches/qoriq-mc-utils/0003-add-configuration-for-lx2162a-som-and-clearfog-board.patch new file mode 100644 index 000000000000..550d04be8b5b --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-mc-utils/0003-add-configuration-for-lx2162a-som-and-clearfog-board.patch @@ -0,0 +1,3622 @@ +From 6e7355c062f643227f7d80029bad46f8542048d2 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Mon, 28 Oct 2024 17:01:33 +0100 +Subject: [PATCH] add configuration for lx2162a som and clearfog board + +Signed-off-by: Josua Mayer +--- + .../LX2160A-CEX7/null-s1_0-s2_0-dpl.dts | 19 + + .../LX2162A-SOM/clearfog-s1_3-s2_7-dpc.dts | 119 ++ + .../LX2162A-SOM/clearfog-s1_3-s2_7-dpl.dts | 1535 ++++++++++++++ + .../LX2162A-SOM/clearfog-s1_3-s2_9-dpc.dts | 127 ++ + .../LX2162A-SOM/clearfog-s1_3-s2_9-dpl.dts | 1759 +++++++++++++++++ + 5 files changed, 3559 insertions(+) + create mode 100644 config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpc.dts + create mode 100644 config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpl.dts + create mode 100644 config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpc.dts + create mode 100644 config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpl.dts + +diff --git a/config/lx2160a/LX2160A-CEX7/null-s1_0-s2_0-dpl.dts b/config/lx2160a/LX2160A-CEX7/null-s1_0-s2_0-dpl.dts +index 9847cc3..8411680 100644 +--- a/config/lx2160a/LX2160A-CEX7/null-s1_0-s2_0-dpl.dts ++++ b/config/lx2160a/LX2160A-CEX7/null-s1_0-s2_0-dpl.dts +@@ -41,6 +41,16 @@ + type = "dpmcp"; + ids = <0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23>; + }; ++ ++ obj_set@dprtc { ++ type = "dprtc"; ++ ids = <0 >; ++ }; ++ ++ obj_set@dpseci { ++ type = "dpseci"; ++ ids = <0 >; ++ }; + }; + }; + }; +@@ -150,6 +160,15 @@ + + dpmcp@35 { + }; ++ ++ dprtc@0 { ++ compatible = "fsl,dprtc"; ++ }; ++ ++ dpseci@0 { ++ compatible = "fsl,dpseci"; ++ priorities = <1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1>; ++ }; + }; + + connections { +diff --git a/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpc.dts b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpc.dts +new file mode 100644 +index 0000000..0f0ec4b +--- /dev/null ++++ b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpc.dts +@@ -0,0 +1,119 @@ ++/* ++ * Copyright 2020 NXP ++ * Copyright 2022 Josua Mayer ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of the above-listed copyright holders nor the ++ * names of any contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++ ++/ { ++ resources { ++ icid_pools { ++ icid_pool@1 { ++ num = <0x64>; ++ base_icid = <0x0>; ++ }; ++ }; ++ }; ++ ++ mc_general { ++ log { ++ mode = "LOG_MODE_ON"; ++ level = "LOG_LEVEL_WARNING"; ++ }; ++ ++ console { ++ mode = "CONSOLE_MODE_OFF"; ++ uart_id = <0x4>; ++ level = "LOG_LEVEL_WARNING"; ++ }; ++ }; ++ ++ controllers { ++ qbman { ++ /* Transform this number of 8-WQ channels into four times ++ * as many 2-WQ channels. This allows the creation of a ++ * larger number of DPCONs. ++ */ ++ wq_ch_conversion = <64>; ++ }; ++ }; ++ ++ board_info { ++ recycle_ports { ++ recycle@1 { ++ max_rate = "1G"; ++ }; ++ ++ recycle@2 { ++ max_rate = "1G"; ++ }; ++ }; ++ ++ ports { ++ /* Serdes 1 */ ++ mac@3 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@4 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@5 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@6 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ /* Serdes 2 */ ++ mac@12 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@13 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@14 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@16 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@17 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@18 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ }; ++ }; ++}; +diff --git a/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpl.dts b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpl.dts +new file mode 100644 +index 0000000..35afac5 +--- /dev/null ++++ b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpl.dts +@@ -0,0 +1,1535 @@ ++/* ++ * Copyright 2020 NXP ++ * Copyright 2022 Josua Mayer ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of the above-listed copyright holders nor the ++ * names of any contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++/ { ++ dpl-version = <10>; ++ /***************************************************************** ++ * Containers ++ *****************************************************************/ ++ containers { ++ ++ dprc@1 { ++ compatible = "fsl,dprc"; ++ parent = "none"; ++ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_OBJ_CREATE_ALLOWED", "DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED"; ++ ++ objects { ++ ++ /* -------------- DPBPs --------------*/ ++ obj_set@dpbp { ++ type = "dpbp"; ++ ids = <0 1 2 3 4 5 6 7 8 9 >; ++ }; ++ ++ /* -------------- DPCONs --------------*/ ++ obj_set@dpcon { ++ type = "dpcon"; ++ ids = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 >; ++ }; ++ ++ /* -------------- DPIOs --------------*/ ++ obj_set@dpio { ++ type = "dpio"; ++ ids = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >; ++ }; ++ ++ /* -------------- DPMACs --------------*/ ++ obj_set@dpmac { ++ type = "dpmac"; ++ ids = <3 4 5 6 12 13 14 16 17 18 >; ++ }; ++ ++ /* -------------- DPMCPs --------------*/ ++ obj_set@dpmcp { ++ type = "dpmcp"; ++ ids = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 >; ++ }; ++ ++ /* -------------- DPNIs --------------*/ ++ obj_set@dpni { ++ type = "dpni"; ++ ids = <0 1 2 3 4 5 6 7 8 9 >; ++ }; ++ ++ /* -------------- DPRTCs --------------*/ ++ obj_set@dprtc { ++ type = "dprtc"; ++ ids = <0 >; ++ }; ++ ++ /* -------------- DPSECIs --------------*/ ++ obj_set@dpseci { ++ type = "dpseci"; ++ ids = <0 >; ++ }; ++ }; ++ }; ++ }; ++ ++ /***************************************************************** ++ * Objects ++ *****************************************************************/ ++ objects { ++ ++ dpbp@0 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@1 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@2 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@3 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@4 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@5 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@6 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@7 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@8 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@9 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpcon@0 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@1 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@2 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@3 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@4 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@5 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@6 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@7 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@8 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@9 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@10 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@11 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@12 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@13 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@14 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@15 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@16 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@17 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@18 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@19 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@20 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@21 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@22 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@23 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@24 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@25 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@26 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@27 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@28 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@29 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@30 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@31 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@32 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@33 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@34 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@35 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@36 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@37 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@38 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@39 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@40 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@41 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@42 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@43 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@44 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@45 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@46 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@47 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@48 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@49 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@50 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@51 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@52 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@53 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@54 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@55 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@56 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@57 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@58 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@59 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@60 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@61 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@62 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@63 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@64 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@65 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@66 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@67 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@68 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@69 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@70 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@71 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@72 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@73 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@74 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@75 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@76 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@77 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@78 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@79 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@80 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@81 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@82 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@83 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@84 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@85 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@86 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@87 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@88 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@89 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@90 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@91 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@92 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@93 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@94 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@95 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@96 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@97 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@98 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@99 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@100 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@101 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@102 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@103 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@104 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@105 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@106 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@107 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@108 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@109 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@110 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@111 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@112 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@113 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@114 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@115 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@116 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@117 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@118 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@119 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@120 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@121 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@122 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@123 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@124 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@125 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@126 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@127 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@128 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@129 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@130 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@131 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@132 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@133 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@134 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@135 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@136 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@137 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@138 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@139 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@140 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@141 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@142 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@143 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@144 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@145 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@146 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@147 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@148 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@149 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@150 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@151 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@152 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@153 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@154 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@155 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@156 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@157 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@158 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@159 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpio@0 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@1 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@2 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@3 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@4 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@5 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@6 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@7 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@8 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@9 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@10 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@11 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@12 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@13 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@14 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@15 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpmac@3 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@4 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@5 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@6 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@12 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@13 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@14 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@16 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@17 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@18 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmcp@1 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@2 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@3 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@4 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@5 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@6 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@7 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@8 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@9 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@10 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@11 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@12 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@13 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@14 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@15 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@16 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@17 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@18 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@19 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@20 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@21 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@22 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@23 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@24 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@25 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@26 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@27 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@28 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@29 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@30 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@31 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@32 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@33 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@34 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@35 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@36 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@37 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@38 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@39 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@40 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@41 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@42 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@43 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@44 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@45 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@46 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@47 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@48 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@49 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@50 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@51 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@52 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@53 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@54 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@55 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@56 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@57 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@58 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@59 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@60 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@61 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpni@0 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@1 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@2 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@3 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@4 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@5 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@6 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@7 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@8 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@9 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dprtc@0 { ++ compatible = "fsl,dprtc"; ++ }; ++ ++ dpseci@0 { ++ compatible = "fsl,dpseci"; ++ priorities = <1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1>; ++ }; ++ }; ++ ++ /***************************************************************** ++ * Connections ++ *****************************************************************/ ++ connections { ++ ++ /*connection@1{ ++ endpoint1 = "dpni@0"; ++ endpoint2 = "dpmac@3"; ++ }; ++ ++ connection@2{ ++ endpoint1 = "dpni@1"; ++ endpoint2 = "dpmac@4"; ++ }; ++ ++ connection@3{ ++ endpoint1 = "dpni@2"; ++ endpoint2 = "dpmac@5"; ++ }; ++ ++ connection@4{ ++ endpoint1 = "dpni@3"; ++ endpoint2 = "dpmac@6"; ++ }; ++ ++ connection@5{ ++ endpoint1 = "dpni@4"; ++ endpoint2 = "dpmac@12"; ++ }; ++ ++ connection@6{ ++ endpoint1 = "dpni@5"; ++ endpoint2 = "dpmac@13"; ++ }; ++ ++ connection@7{ ++ endpoint1 = "dpni@6"; ++ endpoint2 = "dpmac@14"; ++ }; ++ ++ connection@8{ ++ endpoint1 = "dpni@7"; ++ endpoint2 = "dpmac@16"; ++ }; ++ ++ connection@9{ ++ endpoint1 = "dpni@8"; ++ endpoint2 = "dpmac@17"; ++ }; ++ ++ connection@10{ ++ endpoint1 = "dpni@9"; ++ endpoint2 = "dpmac@18"; ++ };*/ ++ }; ++}; +diff --git a/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpc.dts b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpc.dts +new file mode 100644 +index 0000000..5aa4640 +--- /dev/null ++++ b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpc.dts +@@ -0,0 +1,127 @@ ++/* ++ * Copyright 2020 NXP ++ * Copyright 2022 Josua Mayer ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of the above-listed copyright holders nor the ++ * names of any contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++ ++/ { ++ resources { ++ icid_pools { ++ icid_pool@1 { ++ num = <0x64>; ++ base_icid = <0x0>; ++ }; ++ }; ++ }; ++ ++ mc_general { ++ log { ++ mode = "LOG_MODE_ON"; ++ level = "LOG_LEVEL_WARNING"; ++ }; ++ ++ console { ++ mode = "CONSOLE_MODE_OFF"; ++ uart_id = <0x4>; ++ level = "LOG_LEVEL_WARNING"; ++ }; ++ }; ++ ++ controllers { ++ qbman { ++ /* Transform this number of 8-WQ channels into four times ++ * as many 2-WQ channels. This allows the creation of a ++ * larger number of DPCONs. ++ */ ++ wq_ch_conversion = <64>; ++ }; ++ }; ++ ++ board_info { ++ recycle_ports { ++ recycle@1 { ++ max_rate = "1G"; ++ }; ++ ++ recycle@2 { ++ max_rate = "1G"; ++ }; ++ }; ++ ++ ports { ++ /* Serdes 1 */ ++ mac@3 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@4 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@5 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@6 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ /* Serdes 2 */ ++ mac@11 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@12 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@13 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@14 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@15 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@16 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@17 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@18 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ }; ++ }; ++}; +diff --git a/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpl.dts b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpl.dts +new file mode 100644 +index 0000000..1745da4 +--- /dev/null ++++ b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpl.dts +@@ -0,0 +1,1759 @@ ++/* ++ * Copyright 2020 NXP ++ * Copyright 2022 Josua Mayer ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of the above-listed copyright holders nor the ++ * names of any contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++/ { ++ dpl-version = <10>; ++ /***************************************************************** ++ * Containers ++ *****************************************************************/ ++ containers { ++ ++ dprc@1 { ++ compatible = "fsl,dprc"; ++ parent = "none"; ++ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_OBJ_CREATE_ALLOWED", "DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED"; ++ ++ objects { ++ ++ /* -------------- DPBPs --------------*/ ++ obj_set@dpbp { ++ type = "dpbp"; ++ ids = <0 1 2 3 4 5 6 7 8 9 10 11 >; ++ }; ++ ++ /* -------------- DPCONs --------------*/ ++ obj_set@dpcon { ++ type = "dpcon"; ++ ids = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 >; ++ }; ++ ++ /* -------------- DPIOs --------------*/ ++ obj_set@dpio { ++ type = "dpio"; ++ ids = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >; ++ }; ++ ++ /* -------------- DPMACs --------------*/ ++ obj_set@dpmac { ++ type = "dpmac"; ++ ids = <3 4 5 6 11 12 13 14 15 16 17 18 >; ++ }; ++ ++ /* -------------- DPMCPs --------------*/ ++ obj_set@dpmcp { ++ type = "dpmcp"; ++ ids = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 >; ++ }; ++ ++ /* -------------- DPNIs --------------*/ ++ obj_set@dpni { ++ type = "dpni"; ++ ids = <0 1 2 3 4 5 6 7 8 9 10 11 >; ++ }; ++ ++ /* -------------- DPRTCs --------------*/ ++ obj_set@dprtc { ++ type = "dprtc"; ++ ids = <0 >; ++ }; ++ ++ /* -------------- DPSECIs --------------*/ ++ obj_set@dpseci { ++ type = "dpseci"; ++ ids = <0 >; ++ }; ++ }; ++ }; ++ }; ++ ++ /***************************************************************** ++ * Objects ++ *****************************************************************/ ++ objects { ++ ++ dpbp@0 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@1 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@2 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@3 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@4 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@5 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@6 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@7 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@8 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@9 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@10 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@11 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpcon@0 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@1 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@2 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@3 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@4 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@5 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@6 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@7 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@8 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@9 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@10 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@11 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@12 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@13 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@14 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@15 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@16 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@17 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@18 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@19 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@20 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@21 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@22 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@23 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@24 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@25 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@26 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@27 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@28 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@29 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@30 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@31 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@32 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@33 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@34 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@35 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@36 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@37 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@38 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@39 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@40 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@41 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@42 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@43 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@44 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@45 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@46 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@47 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@48 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@49 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@50 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@51 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@52 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@53 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@54 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@55 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@56 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@57 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@58 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@59 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@60 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@61 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@62 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@63 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@64 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@65 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@66 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@67 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@68 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@69 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@70 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@71 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@72 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@73 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@74 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@75 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@76 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@77 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@78 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@79 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@80 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@81 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@82 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@83 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@84 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@85 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@86 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@87 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@88 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@89 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@90 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@91 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@92 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@93 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@94 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@95 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@96 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@97 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@98 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@99 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@100 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@101 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@102 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@103 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@104 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@105 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@106 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@107 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@108 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@109 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@110 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@111 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@112 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@113 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@114 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@115 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@116 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@117 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@118 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@119 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@120 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@121 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@122 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@123 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@124 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@125 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@126 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@127 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@128 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@129 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@130 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@131 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@132 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@133 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@134 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@135 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@136 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@137 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@138 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@139 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@140 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@141 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@142 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@143 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@144 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@145 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@146 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@147 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@148 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@149 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@150 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@151 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@152 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@153 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@154 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@155 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@156 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@157 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@158 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@159 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@160 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@161 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@162 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@163 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@164 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@165 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@166 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@167 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@168 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@169 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@170 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@171 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@172 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@173 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@174 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@175 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@176 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@177 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@178 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@179 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@180 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@181 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@182 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@183 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@184 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@185 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@186 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@187 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@188 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@189 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@190 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@191 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpio@0 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@1 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@2 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@3 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@4 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@5 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@6 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@7 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@8 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@9 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@10 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@11 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@12 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@13 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@14 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@15 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpmac@3 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@4 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@5 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@6 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@11 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@12 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@13 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@14 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@15 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@16 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@17 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@18 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmcp@1 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@2 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@3 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@4 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@5 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@6 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@7 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@8 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@9 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@10 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@11 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@12 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@13 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@14 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@15 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@16 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@17 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@18 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@19 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@20 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@21 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@22 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@23 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@24 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@25 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@26 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@27 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@28 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@29 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@30 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@31 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@32 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@33 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@34 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@35 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@36 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@37 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@38 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@39 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@40 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@41 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@42 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@43 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@44 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@45 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@46 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@47 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@48 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@49 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@50 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@51 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@52 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@53 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@54 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@55 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@56 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@57 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@58 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@59 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@60 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@61 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@62 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@63 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpni@0 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@1 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@2 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@3 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@4 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@5 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@6 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@7 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@8 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@9 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@10 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@11 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dprtc@0 { ++ compatible = "fsl,dprtc"; ++ }; ++ ++ dpseci@0 { ++ compatible = "fsl,dpseci"; ++ priorities = <1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1>; ++ }; ++ }; ++ ++ /***************************************************************** ++ * Connections ++ *****************************************************************/ ++ connections { ++ ++ /*connection@1{ ++ endpoint1 = "dpni@0"; ++ endpoint2 = "dpmac@3"; ++ }; ++ ++ connection@2{ ++ endpoint1 = "dpni@1"; ++ endpoint2 = "dpmac@4"; ++ }; ++ ++ connection@3{ ++ endpoint1 = "dpni@2"; ++ endpoint2 = "dpmac@5"; ++ }; ++ ++ connection@4{ ++ endpoint1 = "dpni@3"; ++ endpoint2 = "dpmac@6"; ++ }; ++ ++ connection@5{ ++ endpoint1 = "dpni@4"; ++ endpoint2 = "dpmac@11"; ++ }; ++ ++ connection@6{ ++ endpoint1 = "dpni@5"; ++ endpoint2 = "dpmac@12"; ++ }; ++ ++ connection@7{ ++ endpoint1 = "dpni@6"; ++ endpoint2 = "dpmac@13"; ++ }; ++ ++ connection@8{ ++ endpoint1 = "dpni@7"; ++ endpoint2 = "dpmac@14"; ++ }; ++ ++ connection@9{ ++ endpoint1 = "dpni@8"; ++ endpoint2 = "dpmac@15"; ++ }; ++ ++ connection@10{ ++ endpoint1 = "dpni@9"; ++ endpoint2 = "dpmac@16"; ++ }; ++ ++ connection@11{ ++ endpoint1 = "dpni@10"; ++ endpoint2 = "dpmac@17"; ++ }; ++ ++ connection@12{ ++ endpoint1 = "dpni@11"; ++ endpoint2 = "dpmac@18"; ++ };*/ ++ }; ++}; +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-mc-utils/0004-lx2162-som-clearfog-enable-dpni-connections.patch b/board/solidrun/lx2160acex7/patches/qoriq-mc-utils/0004-lx2162-som-clearfog-enable-dpni-connections.patch new file mode 100644 index 000000000000..3f8eb937081a --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-mc-utils/0004-lx2162-som-clearfog-enable-dpni-connections.patch @@ -0,0 +1,188 @@ +From 44dd1bb169ab73e5b4d2d27a441bc52b9295e930 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Wed, 30 Oct 2024 18:56:20 +0100 +Subject: [PATCH] lx2162: som: clearfog: enable dpni connections + +Enable the dpni connections so that interfaces are created automatically +during boot. Ordering ensures linux netdev numbers are sorted by dpmac +numbers, i.e. eth0 = dpmac3, eth1=dpmac4, ... + +Signed-off-by: Josua Mayer +--- + .../LX2162A-SOM/clearfog-s1_3-s2_7-dpl.dts | 26 ++++++++-------- + .../LX2162A-SOM/clearfog-s1_3-s2_9-dpl.dts | 30 +++++++++---------- + 2 files changed, 28 insertions(+), 28 deletions(-) + +diff --git a/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpl.dts b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpl.dts +index 35afac5..b6219e9 100644 +--- a/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpl.dts ++++ b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpl.dts +@@ -1,6 +1,6 @@ + /* + * Copyright 2020 NXP +- * Copyright 2022 Josua Mayer ++ * Copyright 2024 Josua Mayer + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: +@@ -1482,54 +1482,54 @@ + *****************************************************************/ + connections { + +- /*connection@1{ +- endpoint1 = "dpni@0"; ++ connection@1{ ++ endpoint1 = "dpni@9"; + endpoint2 = "dpmac@3"; + }; + + connection@2{ +- endpoint1 = "dpni@1"; ++ endpoint1 = "dpni@8"; + endpoint2 = "dpmac@4"; + }; + + connection@3{ +- endpoint1 = "dpni@2"; ++ endpoint1 = "dpni@7"; + endpoint2 = "dpmac@5"; + }; + + connection@4{ +- endpoint1 = "dpni@3"; ++ endpoint1 = "dpni@6"; + endpoint2 = "dpmac@6"; + }; + + connection@5{ +- endpoint1 = "dpni@4"; ++ endpoint1 = "dpni@5"; + endpoint2 = "dpmac@12"; + }; + + connection@6{ +- endpoint1 = "dpni@5"; ++ endpoint1 = "dpni@4"; + endpoint2 = "dpmac@13"; + }; + + connection@7{ +- endpoint1 = "dpni@6"; ++ endpoint1 = "dpni@3"; + endpoint2 = "dpmac@14"; + }; + + connection@8{ +- endpoint1 = "dpni@7"; ++ endpoint1 = "dpni@2"; + endpoint2 = "dpmac@16"; + }; + + connection@9{ +- endpoint1 = "dpni@8"; ++ endpoint1 = "dpni@1"; + endpoint2 = "dpmac@17"; + }; + + connection@10{ +- endpoint1 = "dpni@9"; ++ endpoint1 = "dpni@0"; + endpoint2 = "dpmac@18"; +- };*/ ++ }; + }; + }; +diff --git a/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpl.dts b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpl.dts +index 1745da4..7acb2e2 100644 +--- a/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpl.dts ++++ b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpl.dts +@@ -1,6 +1,6 @@ + /* + * Copyright 2020 NXP +- * Copyright 2022 Josua Mayer ++ * Copyright 2024 Josua Mayer + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: +@@ -1696,64 +1696,64 @@ + *****************************************************************/ + connections { + +- /*connection@1{ +- endpoint1 = "dpni@0"; ++ connection@1{ ++ endpoint1 = "dpni@11"; + endpoint2 = "dpmac@3"; + }; + + connection@2{ +- endpoint1 = "dpni@1"; ++ endpoint1 = "dpni@10"; + endpoint2 = "dpmac@4"; + }; + + connection@3{ +- endpoint1 = "dpni@2"; ++ endpoint1 = "dpni@9"; + endpoint2 = "dpmac@5"; + }; + + connection@4{ +- endpoint1 = "dpni@3"; ++ endpoint1 = "dpni@8"; + endpoint2 = "dpmac@6"; + }; + + connection@5{ +- endpoint1 = "dpni@4"; ++ endpoint1 = "dpni@7"; + endpoint2 = "dpmac@11"; + }; + + connection@6{ +- endpoint1 = "dpni@5"; ++ endpoint1 = "dpni@6"; + endpoint2 = "dpmac@12"; + }; + + connection@7{ +- endpoint1 = "dpni@6"; ++ endpoint1 = "dpni@5"; + endpoint2 = "dpmac@13"; + }; + + connection@8{ +- endpoint1 = "dpni@7"; ++ endpoint1 = "dpni@4"; + endpoint2 = "dpmac@14"; + }; + + connection@9{ +- endpoint1 = "dpni@8"; ++ endpoint1 = "dpni@3"; + endpoint2 = "dpmac@15"; + }; + + connection@10{ +- endpoint1 = "dpni@9"; ++ endpoint1 = "dpni@2"; + endpoint2 = "dpmac@16"; + }; + + connection@11{ +- endpoint1 = "dpni@10"; ++ endpoint1 = "dpni@1"; + endpoint2 = "dpmac@17"; + }; + + connection@12{ +- endpoint1 = "dpni@11"; ++ endpoint1 = "dpni@0"; + endpoint2 = "dpmac@18"; +- };*/ ++ }; + }; + }; +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-mc-utils/0005-lx2160acex7-clearfog-cx-configure-qsfp-ports-type-ph.patch b/board/solidrun/lx2160acex7/patches/qoriq-mc-utils/0005-lx2160acex7-clearfog-cx-configure-qsfp-ports-type-ph.patch new file mode 100644 index 000000000000..1f1cefc8e275 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-mc-utils/0005-lx2160acex7-clearfog-cx-configure-qsfp-ports-type-ph.patch @@ -0,0 +1,52 @@ +From 35dffd4f4a82a18897bf0b78df8f1402ef5e2d03 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Thu, 31 Oct 2024 17:35:21 +0100 +Subject: [PATCH] lx2160acex7: clearfog-cx: configure qsfp ports type phy + +Interface type PHY allows Linux to configure ethernet speed at runtime +for each port, rather than sticking to assignment from serdes protocols. + +This is particularly useful with SD1 protocol 18 which by default drives +just two ports at 25Gbps while QSFP connector has 4. +At protocol 18 Linux can switch any of the 8 ports between 10Gbps and +25Gbps as needed. + +Due to lack of software support, the QSFP ports need to define speed in +device-tree. + +Signed-off-by: Josua Mayer +--- + config/lx2160a/LX2160A-CEX7/clearfog-cx-s1_8-s2_0-dpc.dts | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/config/lx2160a/LX2160A-CEX7/clearfog-cx-s1_8-s2_0-dpc.dts b/config/lx2160a/LX2160A-CEX7/clearfog-cx-s1_8-s2_0-dpc.dts +index dcc376e..9a508d2 100644 +--- a/config/lx2160a/LX2160A-CEX7/clearfog-cx-s1_8-s2_0-dpc.dts ++++ b/config/lx2160a/LX2160A-CEX7/clearfog-cx-s1_8-s2_0-dpc.dts +@@ -69,19 +69,19 @@ + board_info { + ports { + mac@3 { +- link_type = "MAC_LINK_TYPE_FIXED"; ++ link_type = "MAC_LINK_TYPE_PHY"; + }; + + mac@4 { +- link_type = "MAC_LINK_TYPE_FIXED"; ++ link_type = "MAC_LINK_TYPE_PHY"; + }; + + mac@5 { +- link_type = "MAC_LINK_TYPE_FIXED"; ++ link_type = "MAC_LINK_TYPE_PHY"; + }; + + mac@6 { +- link_type = "MAC_LINK_TYPE_FIXED"; ++ link_type = "MAC_LINK_TYPE_PHY"; + }; + + mac@7 { +-- +2.43.0 + From patchwork Sun Dec 8 14:38:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 2019769 Return-Path: X-Original-To: incoming-buildroot@patchwork.ozlabs.org Delivered-To: patchwork-incoming-buildroot@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=buildroot.org (client-ip=2605:bc80:3010::137; helo=smtp4.osuosl.org; envelope-from=buildroot-bounces@buildroot.org; receiver=patchwork.ozlabs.org) Received: from smtp4.osuosl.org (smtp4.osuosl.org [IPv6:2605:bc80:3010::137]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Y5sL56Npgz1yRf for ; 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Sun, 08 Dec 2024 06:38:38 -0800 (PST) Received: from skbuf.lan ([86.127.124.81]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa666cf5743sm204660366b.65.2024.12.08.06.38.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Dec 2024 06:38:37 -0800 (PST) From: Vladimir Oltean To: buildroot@buildroot.org Cc: Brandon Maier , Rabeeh Khoury , Josua Mayer , Ioana Ciornei Date: Sun, 8 Dec 2024 16:38:00 +0200 Message-ID: <20241208143802.1048266-10-olteanv@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241208143802.1048266-1-olteanv@gmail.com> References: <20241208143802.1048266-1-olteanv@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Sun, 08 Dec 2024 17:24:03 +0000 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1733668720; x=1734273520; darn=buildroot.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jBjIG2ENw8o76UBtHFoQ/RF16EFJRog9Z35h6sZai+A=; b=kUN8Ybzr1UQKrBBWQecQWAXC0B/+GHpUX40TX0Vq+yHCBnb2S/fXtD1qy353oEbs7y YcPU6drZ1GdjIfOljZLKu1E6hw1WpZmBEOSrVqrUu43ZvdcZKGCaHzpHyQ7en7hsmVQl Oksa0vX7x8I3ab9d+s0X4VGma+AkdM9xV3uWSY62s3aezVDQDaHzaonqWXcX6wf4aYFo sfWF14sGcQdZ8HsDx15TBFiTdotkXqrl7Ma3CMIweJTjpUv7Y6pjUovUx8Rruv4W9SxC hIDuoEEDWtWaubt8/+Suby2ajS142+es0SlYzEQQfGXztL7V9770EMdPzq/rKYXc5NcM wvzw== X-Mailman-Original-Authentication-Results: smtp4.osuosl.org; dmarc=pass (p=none dis=none) header.from=gmail.com X-Mailman-Original-Authentication-Results: smtp4.osuosl.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=kUN8Ybzr Subject: [Buildroot] [PATCH v2 09/11] board/lx2160acex7: add qoriq-rcw patches X-BeenThere: buildroot@buildroot.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: buildroot-bounces@buildroot.org Sender: "buildroot" These come unmodified from SolidRun as of lx2160a_build commit 497e9ebf0e2a ("atf: update sdram configuration for internal cex6 evb revision 1.2"), and are needed to establish a bootable Reset Configuration Word for the platform. The Buildroot defconfig only uses lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw. Signed-off-by: Vladimir Oltean --- v1->v2: - split out from previous [PATCH 6/7] board/lx2160acex7: new platform - update to latest lx2160a_build HEAD ...n-solidrun-lx2160a-cex-7-on-clearfog.patch | 950 ++++++++ ...-MEM_PLL_CFG-into-ddr-speed-specific.patch | 112 + ...separate-configurations-for-flexspi-.patch | 894 ++++++++ ...me-sdhc1-config-to-generic-sdhc-for-.patch | 149 ++ ...c-jumpc-and-jump-to-pbi-instructions.patch | 55 + ...add-configuration-for-both-sdhc-xspi.patch | 836 +++++++ ...ootlocptr-reduce-size-of-pbi-section.patch | 90 + ...ge-2.2GHz-configuration-platform-clo.patch | 475 ++++ ...configuration-for-fraction-ddr-speed.patch | 420 ++++ ...n-solidrun-internal-lx2160a-cex6-eva.patch | 220 ++ ...le-A-050426-workaround-for-silicon-o.patch | 35 + ...le-pci-errata-workarounds-for-all-ac.patch | 87 + ...-configuration-for-2.2GHz-binned-soc.patch | 42 + .../0014-lx2162aqds-re-enable-dpmac11.patch | 27 + ...n-for-lx2162a-som-and-clearfog-evalu.patch | 532 +++++ ...rfog-cx-add-configuration-for-serdes.patch | 2000 +++++++++++++++++ ...configuration-for-serdes-1-protocol-.patch | 49 + ...ipt-generating-configs-from-template.patch | 1476 ++++++++++++ ...rfog-cx-add-configuration-for-serdes.patch | 1611 +++++++++++++ ...add-configuration-for-each-ddr-speed.patch | 285 +++ 20 files changed, 10345 insertions(+) create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0001-add-configuration-solidrun-lx2160a-cex-7-on-clearfog.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0002-lx2160acex7-move-MEM_PLL_CFG-into-ddr-speed-specific.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0003-lx2160acex7-add-separate-configurations-for-flexspi-.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0004-lx2160acex7-rename-sdhc1-config-to-generic-sdhc-for-.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0005-add-loadc-jumpc-and-jump-to-pbi-instructions.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0006-lx2160acex7-add-configuration-for-both-sdhc-xspi.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0007-bootlocptr-reduce-size-of-pbi-section.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0008-lx2160acex7-change-2.2GHz-configuration-platform-clo.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0009-lx2160acex7-add-configuration-for-fraction-ddr-speed.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0010-add-configuration-solidrun-internal-lx2160a-cex6-eva.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0011-lx2160acex7-enable-A-050426-workaround-for-silicon-o.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0012-lx2160acex6-enable-pci-errata-workarounds-for-all-ac.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0013-lx2160acex6-add-configuration-for-2.2GHz-binned-soc.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0014-lx2162aqds-re-enable-dpmac11.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0015-add-configuration-for-lx2162a-som-and-clearfog-evalu.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0016-lx2160acex7-clearfog-cx-add-configuration-for-serdes.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0017-lx2160acex7-add-configuration-for-serdes-1-protocol-.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0018-solidrun-add-script-generating-configs-from-template.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0019-lx2160acex7-clearfog-cx-add-configuration-for-serdes.patch create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0020-lx2160acex6-add-configuration-for-each-ddr-speed.patch diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0001-add-configuration-solidrun-lx2160a-cex-7-on-clearfog.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0001-add-configuration-solidrun-lx2160a-cex-7-on-clearfog.patch new file mode 100644 index 000000000000..f6af96404e07 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0001-add-configuration-solidrun-lx2160a-cex-7-on-clearfog.patch @@ -0,0 +1,950 @@ +From 5a5ec65c0eb53efbcb69894576d7d04f671a730e Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Wed, 12 Jun 2024 15:19:39 +0200 +Subject: [PATCH] add configuration solidrun lx2160a-cex-7 on clearfog-cx board + +Signed-off-by: Josua Mayer +--- + lx2160acex7/Makefile | 1 + + lx2160acex7/README | 0 + .../clearfog-cx/rcw_2000_700_2400_8_5_2.rcw | 23 +++++ + .../clearfog-cx/rcw_2000_700_2600_8_5_2.rcw | 23 +++++ + .../clearfog-cx/rcw_2000_700_2900_8_5_2.rcw | 23 +++++ + .../clearfog-cx/rcw_2000_700_3200_8_5_2.rcw | 23 +++++ + .../clearfog-cx/rcw_2200_700_2400_8_5_2.rcw | 23 +++++ + .../clearfog-cx/rcw_2200_700_2600_8_5_2.rcw | 23 +++++ + .../clearfog-cx/rcw_2200_700_2900_8_5_2.rcw | 23 +++++ + .../clearfog-cx/rcw_2200_700_3200_8_5_2.rcw | 23 +++++ + lx2160acex7/clearfog-cx/sd1_8_eq.rcwi | 39 ++++++++ + lx2160acex7/include/SD1_8.rcwi | 24 +++++ + lx2160acex7/include/SD2_5.rcwi | 27 ++++++ + lx2160acex7/include/SD3_2.rcwi | 27 ++++++ + lx2160acex7/include/common.rcwi | 90 +++++++++++++++++++ + lx2160acex7/include/common_pbi.rcwi | 55 ++++++++++++ + lx2160acex7/include/pll_2000_700_xxxx.rcwi | 14 +++ + lx2160acex7/include/pll_2200_700_xxxx.rcwi | 14 +++ + lx2160acex7/include/pll_xxxx_xxx_2400.rcwi | 7 ++ + lx2160acex7/include/pll_xxxx_xxx_2600.rcwi | 7 ++ + lx2160acex7/include/pll_xxxx_xxx_2900.rcwi | 7 ++ + lx2160acex7/include/pll_xxxx_xxx_3200.rcwi | 7 ++ + lx2160acex7_rev2/Makefile | 1 + + lx2160acex7_rev2/README | 0 + .../clearfog-cx/rcw_2000_700_2400_8_5_2.rcw | 23 +++++ + .../clearfog-cx/rcw_2000_700_2600_8_5_2.rcw | 23 +++++ + .../clearfog-cx/rcw_2000_700_2900_8_5_2.rcw | 23 +++++ + .../clearfog-cx/rcw_2000_700_3200_8_5_2.rcw | 23 +++++ + .../clearfog-cx/rcw_2200_700_2400_8_5_2.rcw | 23 +++++ + .../clearfog-cx/rcw_2200_700_2600_8_5_2.rcw | 23 +++++ + .../clearfog-cx/rcw_2200_700_2900_8_5_2.rcw | 23 +++++ + .../clearfog-cx/rcw_2200_700_3200_8_5_2.rcw | 23 +++++ + 32 files changed, 688 insertions(+) + create mode 100644 lx2160acex7/Makefile + create mode 100644 lx2160acex7/README + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2.rcw + create mode 100644 lx2160acex7/clearfog-cx/sd1_8_eq.rcwi + create mode 100644 lx2160acex7/include/SD1_8.rcwi + create mode 100644 lx2160acex7/include/SD2_5.rcwi + create mode 100644 lx2160acex7/include/SD3_2.rcwi + create mode 100644 lx2160acex7/include/common.rcwi + create mode 100644 lx2160acex7/include/common_pbi.rcwi + create mode 100644 lx2160acex7/include/pll_2000_700_xxxx.rcwi + create mode 100644 lx2160acex7/include/pll_2200_700_xxxx.rcwi + create mode 100644 lx2160acex7/include/pll_xxxx_xxx_2400.rcwi + create mode 100644 lx2160acex7/include/pll_xxxx_xxx_2600.rcwi + create mode 100644 lx2160acex7/include/pll_xxxx_xxx_2900.rcwi + create mode 100644 lx2160acex7/include/pll_xxxx_xxx_3200.rcwi + create mode 100644 lx2160acex7_rev2/Makefile + create mode 100644 lx2160acex7_rev2/README + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2.rcw + +diff --git a/lx2160acex7/Makefile b/lx2160acex7/Makefile +new file mode 100644 +index 0000000..f77e46b +--- /dev/null ++++ b/lx2160acex7/Makefile +@@ -0,0 +1 @@ ++include ../Makefile.inc +diff --git a/lx2160acex7/README b/lx2160acex7/README +new file mode 100644 +index 0000000..e69de29 +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2.rcw +new file mode 100644 +index 0000000..ba0f82c +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2.rcw +new file mode 100644 +index 0000000..b1723d3 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2.rcw +new file mode 100644 +index 0000000..fa59785 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2.rcw +new file mode 100644 +index 0000000..90ac8a4 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2.rcw +new file mode 100644 +index 0000000..464a285 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2.rcw +new file mode 100644 +index 0000000..1ef7db6 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2.rcw +new file mode 100644 +index 0000000..d021306 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2.rcw +new file mode 100644 +index 0000000..bfef1d4 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/sd1_8_eq.rcwi b/lx2160acex7/clearfog-cx/sd1_8_eq.rcwi +new file mode 100644 +index 0000000..44961c1 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/sd1_8_eq.rcwi +@@ -0,0 +1,39 @@ ++/* ++ * SERDES tuning based on the following hardware - ++ * - SolidRun COM express type 7 revision 1.7 and newer ++ * - SolidRun ClearFog CX revision 1.3 with TI retimers and EPT COM express headers ++ */ ++ ++.pbi ++/* Lane E (SD1 TX/RX 3) */ ++write 0x01EA0C28,0x00000000 ++write 0x01EA0C30,0x20818120 ++write 0x01EA0C34,0x23000000 ++write 0x01EA0C68,0x80000000 ++write 0x01EA0C74,0x00002020 ++write 0x01EA0C80,0x00008000 ++ ++/* Lane F (SD1 TX/RX 2)*/ ++write 0x01EA0D28,0x00000000 ++write 0x01EA0D30,0x20818120 ++write 0x01EA0D34,0x23000000 ++write 0x01EA0D68,0x80000000 ++write 0x01EA0D74,0x00002020 ++write 0x01EA0D80,0x00008000 ++ ++/* Lane G (SD1 TX/RX 1)*/ ++write 0x01EA0E28,0x00000000 ++write 0x01EA0E30,0x20818120 ++write 0x01EA0E34,0x23000000 ++write 0x01EA0E68,0x80000000 ++write 0x01EA0E74,0x00002020 ++write 0x01EA0E80,0x00008000 ++ ++/* Lane H (SD1 TX/RX 0)*/ ++write 0x01EA0F28,0x00000000 ++write 0x01EA0F30,0x20818120 ++write 0x01EA0F34,0x23000000 ++write 0x01EA0F68,0x80000000 ++write 0x01EA0F74,0x00002020 ++write 0x01EA0F80,0x00008000 ++.end +diff --git a/lx2160acex7/include/SD1_8.rcwi b/lx2160acex7/include/SD1_8.rcwi +new file mode 100644 +index 0000000..87ce260 +--- /dev/null ++++ b/lx2160acex7/include/SD1_8.rcwi +@@ -0,0 +1,24 @@ ++/* ++ * Serdes 1 Reference Clocks: ++ * - PLLF = 100MHz ++ * - PLLS = 161.1328125MHz ++ */ ++ ++/* Serdes 1 Protocol 8: 8x10Gbps */ ++SRDS_PRTCL_S1=8 ++ ++/* Disable PLLF */ ++SRDS_PLL_PD_PLL1=1 ++ ++/* Use PLLF for PLLS */ ++SRDS_INTRA_REF_CLK_S1=1 ++ ++/* Enable PLLS */ ++SRDS_PLL_PD_PLL2=0 ++ ++/* ++ * Select PLLF frequency 100MHz (don't care): Bit 0 = 0 ++ * Select PLLS frequency 161.1328125MHz: Bit 1 = 1 ++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933) ++ */ ++SRDS_PLL_REF_CLK_SEL_S1=2 +diff --git a/lx2160acex7/include/SD2_5.rcwi b/lx2160acex7/include/SD2_5.rcwi +new file mode 100644 +index 0000000..8fed5bd +--- /dev/null ++++ b/lx2160acex7/include/SD2_5.rcwi +@@ -0,0 +1,27 @@ ++/* ++ * Serdes 2 Reference Clocks: ++ * - PLLF = 100MHz ++ * - PLLS = 100MHz ++ */ ++ ++/* Serdes 2 Protocol 5: 1x PCI-e x4 Gen 3 + 4x SATA */ ++SRDS_PRTCL_S2=5 ++ ++/* Enable PLLF */ ++SRDS_PLL_PD_PLL3=0 ++ ++/* Don't use PLLF for PLLS */ ++SRDS_INTRA_REF_CLK_S2=0 ++ ++/* Enable PLLS */ ++SRDS_PLL_PD_PLL4=0 ++ ++/* ++ * Select PLLF frequency 100MHz: Bit 0 = 0 ++ * Select PLLS frequency 100MHz: Bit 1 = 0 ++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 934-935) ++ */ ++SRDS_PLL_REF_CLK_SEL_S2=0 ++ ++/* Support up to PCI-e Gen 3 */ ++SRDS_DIV_PEX_S2=1 +diff --git a/lx2160acex7/include/SD3_2.rcwi b/lx2160acex7/include/SD3_2.rcwi +new file mode 100644 +index 0000000..b0be701 +--- /dev/null ++++ b/lx2160acex7/include/SD3_2.rcwi +@@ -0,0 +1,27 @@ ++/* ++ * Serdes 3 Reference Clocks: ++ * - PLLF = 100MHz ++ * - PLLS = 100MHz ++ */ ++ ++/* Serdes 3 Protocol 2: 1x PCI-e x8 Gen 3 */ ++SRDS_PRTCL_S3=2 ++ ++/* Disable PLLF */ ++SRDS_PLL_PD_PLL5=1 ++ ++/* Don't use Serdes 3 PLLF for PLLS */ ++SRDS_INTRA_REF_CLK_S3=0 ++ ++/* Enable PLLS */ ++SRDS_PLL_PD_PLL6=0 ++ ++/* ++ * Select PLLF frequency 100MHz: Bit 0 = 0 ++ * Select PLLS frequency 100MHz: Bit 1 = 0 ++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 936-937) ++ */ ++SRDS_PLL_REF_CLK_SEL_S3=0 ++ ++/* Support up to PCI-e Gen 3 */ ++SRDS_DIV_PEX_S3=1 +diff --git a/lx2160acex7/include/common.rcwi b/lx2160acex7/include/common.rcwi +new file mode 100644 +index 0000000..e8a5660 +--- /dev/null ++++ b/lx2160acex7/include/common.rcwi +@@ -0,0 +1,90 @@ ++/* ++ * LX2160A COM-Express Type 7 Common Configuration ++ */ ++ ++/* DDR CGU PLL clk out div 4 */ ++MEM_PLL_CFG=3 ++MEM2_PLL_CFG=3 ++/* C[5:8]_PLL are CG[5:8] div 1 */ ++C5_PLL_SEL=0 ++C6_PLL_SEL=0 ++C7_PLL_SEL=0 ++C8_PLL_SEL=0 ++/* Cluster group A clock is PLL1 div 1 (unused on LX2160A) */ ++HWA_CGA_M1_CLK_SEL=1 ++/* Cluster group B clock is PLL2 div 2 (for DCE) */ ++HWA_CGB_M1_CLK_SEL=6 ++/* fall-back boot-mode is ocram, when DCFG bit location pointer registers are null */ ++BOOT_LOC=21 // TODO: test if SPI boot still functional ++/* SYSCLK is 100MHz */ ++SYSCLK_FREQ=600 ++/* USB-3.0 clock is 100MHz */ ++USB3_CLK_FSEL=39 ++ ++/* IIC1 is I2C */ ++IIC1_PMUX=0 ++/* IIC2 is SD Card-Detect */ ++IIC2_PMUX=6 ++/* IIC3 is I2C */ ++IIC3_PMUX=0 ++/* IIC4 is I2C (unused) */ ++IIC4_PMUX=0 ++/* IIC5 is I2C */ ++IIC5_PMUX=0 ++/* IIC6 is I2C (unused) */ ++IIC6_PMUX=0 ++/* ++ * SDHC1 CMD/CLK/VBUS/DAT[0:3] are SDHC ++ * SPI3_PCS0 is VSEL ++ */ ++SDHC1_BASE_PMUX=0 ++/* SDHC1_DS is GPIO (unused) */ ++SDHC1_DS_PMUX=1 ++/* SDHC1_CMD/DAT0/DAT1_DIR (SPI3_PCS[1:3]) are GPIO1[14:12] */ ++SDHC1_DIR_PMUX=1 ++/* USB[1:2]_DRVVBUS/PWRFAULT are GPIO4[28:25] (unused) */ ++USB_EXT_PMUX=1 ++/* XSPI1_A_DQS/SCK/CS0_B/CS1_B are SPI */ ++XSPI1_A_BASE_PMUX=0 ++/* XSPI1_A_DATA[3:0] are SPI */ ++XSPI1_A_DATA30_PMUX=0 ++/* XSPI1_A_DATA[7:4] are SPI */ ++XSPI1_A_DATA74_PMUX=0 ++/* ASLEEP is ASLEEP (unused) */ ++ASLEEP_PMUX=0 ++/* EVT[2:0] are GPIO3[14:12] */ ++EVT20_PMUX=1 ++/* EVT[4:3] are GPIO3[16:15] */ ++EVT43_PMUX=1 ++/* CLK_OUT is GPIO (unused) */ ++CLK_OUT_PMUX=1 ++/* IRQ[3:0] are GPIO3[3:0] */ ++IRQ03_00_PMUX=1 ++/* IRQ[7:4] are GPIO3[7:4] */ ++IRQ07_04_PMUX=1 ++/* IRQ[11:8] are GPIO3[11:8] */ ++IRQ11_08_PMUX=1 ++/* EC1_* are RGMII */ ++EC1_PMUX=0 ++/* EC2_* are PTP */ ++EC2_PMUX=2 ++/* EC_GTX_CLK125 is PTP */ ++GTX_CLK_PMUX=0 ++/* UART1_SOUT/SIN are UART1 */ ++UART1_SOUTSIN_PMUX=0 ++/* UART1_RTS/CTS_B are GPIO (unused) */ ++UART1_RTSCTS_PMUX=1 ++/* UART2_SOUT/SIN are UART2 */ ++UART2_SOUTSIN_PMUX=0 ++/* UART2_RTS/CTS_B are GPIO (unused) */ ++UART2_RTSCTS_PMUX=1 ++/* SDHC2_CMD/DAT[3:0]/DS/CLK are SDHC */ ++SDHC2_BASE_PMUX=0 ++/* SDHC2_DAT[7:4] are SDHC */ ++SDHC2_DAT74_PMUX=0 ++ ++/* ++ * Original SolidRun Settings in LSDK-21.08 ++ * ++ * HWA_CGB_M1_CLK_SEL=7 // Cluster Group B PLL 2 / 3 is clock ++ */ +diff --git a/lx2160acex7/include/common_pbi.rcwi b/lx2160acex7/include/common_pbi.rcwi +new file mode 100644 +index 0000000..0c28f92 +--- /dev/null ++++ b/lx2160acex7/include/common_pbi.rcwi +@@ -0,0 +1,55 @@ ++/* ++ * LX2160A COM-Express Type 7 Common Configuration ++ */ ++ ++/* Drive the fan full speed pin */ ++.pbi ++write 0x2320000,0x20000000 ++.end ++ ++/* Errata to write on scratch reg for validation */ ++#include <../lx2160asi/scratchrw1.rcw> ++ ++/* Boot Location Pointer */ ++#include <../lx2160asi/bootlocptr_sd.rcw> ++ ++/* Errata for SATA controller */ ++#include <../lx2160asi/a010554.rcw> ++ ++#if LX_SR == 1 ++/* Errata for PCIe controller */ ++#include <../lx2160asi/a011270.rcw> ++#include <../lx2160asi/a050234.rcw> ++#endif ++ ++/* common PBI commands */ ++#include <../lx2160asi/common.rcw> ++ ++#if LX_SR == 2 ++/*PCIe Errata A-009531*/ ++#include <../lx2160asi/a009531_PEX3.rcw> ++#include <../lx2160asi/a009531_PEX5.rcw> ++ ++/*PCIe Errata A-008851*/ ++#include <../lx2160asi/a008851_PEX3.rcw> ++#include <../lx2160asi/a008851_PEX5.rcw> ++ ++/*SerDes Errata A-050479*/ ++#include <../lx2160asi/a050479.rcw> ++ ++/* Errata A-050426 */ ++#include <../lx2160asi/a050426.rcw> ++#endif ++ ++/* ++ * FlexSPI controller supports modifcation of the FlexSPI Clock ++ * divisor value, default value of this is 80. ++ * For 700 MHz, FlexSPI clock runs with default value is ++ * (Platform Clock * 2) / (Divisor value) ++ * => 700 * 2 / 80 ==> 17MHz ++ * On Clearfog-CX bus speed is limited to 20MHz by a mux on carrier board. ++ * Explicitly set the default value again, in case it was modified elsewhere. ++ */ ++.pbi ++write 0x1e00900,0x00000014 ++.end +diff --git a/lx2160acex7/include/pll_2000_700_xxxx.rcwi b/lx2160acex7/include/pll_2000_700_xxxx.rcwi +new file mode 100644 +index 0000000..2a3725f +--- /dev/null ++++ b/lx2160acex7/include/pll_2000_700_xxxx.rcwi +@@ -0,0 +1,14 @@ ++/* ++ * Core and Platform Clocks: ++ * - Platform: 700MHz ++ * - Core: 2000MHz ++ */ ++ ++/* platform clock is system clock mul 14 div 2 = 700 */ ++SYS_PLL_RAT=14 ++ ++/* core clocks are 2000 */ ++CGA_PLL1_RAT=20 ++CGA_PLL2_RAT=20 ++CGB_PLL1_RAT=20 ++CGB_PLL2_RAT=7 +diff --git a/lx2160acex7/include/pll_2200_700_xxxx.rcwi b/lx2160acex7/include/pll_2200_700_xxxx.rcwi +new file mode 100644 +index 0000000..91d1a9b +--- /dev/null ++++ b/lx2160acex7/include/pll_2200_700_xxxx.rcwi +@@ -0,0 +1,14 @@ ++/* ++ * Core and Platform Clocks: ++ * - Platform: 700MHz ++ * - Core: 2200MHz ++ */ ++ ++/* platform clock is system clock mul 14 div 2 = 700 */ ++SYS_PLL_RAT=14 ++ ++/* core clocks are 2200 */ ++CGA_PLL1_RAT=22 ++CGA_PLL2_RAT=22 ++CGB_PLL1_RAT=22 ++CGB_PLL2_RAT=7 +diff --git a/lx2160acex7/include/pll_xxxx_xxx_2400.rcwi b/lx2160acex7/include/pll_xxxx_xxx_2400.rcwi +new file mode 100644 +index 0000000..9c79664 +--- /dev/null ++++ b/lx2160acex7/include/pll_xxxx_xxx_2400.rcwi +@@ -0,0 +1,7 @@ ++/* ++ * DDR Rate: 2400MHz ++ */ ++ ++/* data rate is reference clock mul 24 = 2400 */ ++MEM_PLL_RAT=24 ++MEM2_PLL_RAT=24 +diff --git a/lx2160acex7/include/pll_xxxx_xxx_2600.rcwi b/lx2160acex7/include/pll_xxxx_xxx_2600.rcwi +new file mode 100644 +index 0000000..404d52a +--- /dev/null ++++ b/lx2160acex7/include/pll_xxxx_xxx_2600.rcwi +@@ -0,0 +1,7 @@ ++/* ++ * DDR Rate: 2600MHz ++ */ ++ ++/* data rate is reference clock mul 26 = 2600 */ ++MEM_PLL_RAT=26 ++MEM2_PLL_RAT=26 +diff --git a/lx2160acex7/include/pll_xxxx_xxx_2900.rcwi b/lx2160acex7/include/pll_xxxx_xxx_2900.rcwi +new file mode 100644 +index 0000000..2ba2426 +--- /dev/null ++++ b/lx2160acex7/include/pll_xxxx_xxx_2900.rcwi +@@ -0,0 +1,7 @@ ++/* ++ * DDR Rate: 2900MHz ++ */ ++ ++/* data rate is reference clock mul 29 = 2900 */ ++MEM_PLL_RAT=29 ++MEM2_PLL_RAT=29 +diff --git a/lx2160acex7/include/pll_xxxx_xxx_3200.rcwi b/lx2160acex7/include/pll_xxxx_xxx_3200.rcwi +new file mode 100644 +index 0000000..cbc2cf4 +--- /dev/null ++++ b/lx2160acex7/include/pll_xxxx_xxx_3200.rcwi +@@ -0,0 +1,7 @@ ++/* ++ * DDR Rate: 3200MHz ++ */ ++ ++/* data rate is reference clock mul 32 = 3200 */ ++MEM_PLL_RAT=32 ++MEM2_PLL_RAT=32 +diff --git a/lx2160acex7_rev2/Makefile b/lx2160acex7_rev2/Makefile +new file mode 100644 +index 0000000..f77e46b +--- /dev/null ++++ b/lx2160acex7_rev2/Makefile +@@ -0,0 +1 @@ ++include ../Makefile.inc +diff --git a/lx2160acex7_rev2/README b/lx2160acex7_rev2/README +new file mode 100644 +index 0000000..e69de29 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2.rcw +new file mode 100644 +index 0000000..1c23c5c +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2.rcw +new file mode 100644 +index 0000000..87391ab +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2.rcw +new file mode 100644 +index 0000000..9114f36 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2.rcw +new file mode 100644 +index 0000000..7e97984 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2.rcw +new file mode 100644 +index 0000000..d59ceed +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2.rcw +new file mode 100644 +index 0000000..1bf815b +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2.rcw +new file mode 100644 +index 0000000..01138dc +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2.rcw +new file mode 100644 +index 0000000..e99a12b +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +-- +2.35.3 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0002-lx2160acex7-move-MEM_PLL_CFG-into-ddr-speed-specific.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0002-lx2160acex7-move-MEM_PLL_CFG-into-ddr-speed-specific.patch new file mode 100644 index 000000000000..1c3097827584 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0002-lx2160acex7-move-MEM_PLL_CFG-into-ddr-speed-specific.patch @@ -0,0 +1,112 @@ +From 9d49cf46a3fde08abd3ba48169c7688dfeed74bb Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Fri, 27 Sep 2024 17:58:11 +0200 +Subject: [PATCH] lx2160acex7: move MEM_PLL_CFG into ddr-speed-specific + includes + +Both MEM_PLL_RAT and MEM_PLL_CFG together create the final ddr clock +speed, move the latter from common.rcwi into each speed-specific +include. + +Signed-off-by: Josua Mayer +--- + lx2160acex7/include/common.rcwi | 3 --- + lx2160acex7/include/pll_xxxx_xxx_2400.rcwi | 9 +++++++-- + lx2160acex7/include/pll_xxxx_xxx_2600.rcwi | 9 +++++++-- + lx2160acex7/include/pll_xxxx_xxx_2900.rcwi | 9 +++++++-- + lx2160acex7/include/pll_xxxx_xxx_3200.rcwi | 9 +++++++-- + 5 files changed, 28 insertions(+), 11 deletions(-) + +diff --git a/lx2160acex7/include/common.rcwi b/lx2160acex7/include/common.rcwi +index e8a5660..5523318 100644 +--- a/lx2160acex7/include/common.rcwi ++++ b/lx2160acex7/include/common.rcwi +@@ -2,9 +2,6 @@ + * LX2160A COM-Express Type 7 Common Configuration + */ + +-/* DDR CGU PLL clk out div 4 */ +-MEM_PLL_CFG=3 +-MEM2_PLL_CFG=3 + /* C[5:8]_PLL are CG[5:8] div 1 */ + C5_PLL_SEL=0 + C6_PLL_SEL=0 +diff --git a/lx2160acex7/include/pll_xxxx_xxx_2400.rcwi b/lx2160acex7/include/pll_xxxx_xxx_2400.rcwi +index 9c79664..6356b36 100644 +--- a/lx2160acex7/include/pll_xxxx_xxx_2400.rcwi ++++ b/lx2160acex7/include/pll_xxxx_xxx_2400.rcwi +@@ -1,7 +1,12 @@ + /* + * DDR Rate: 2400MHz ++ * ++ * DDR PHY Clock (half ddr clock, quarter mts rate) ++ * multiplier = 24 (24) ++ * divider = 4 (3) ++ * 100MHz x 24 / 4 = 600MHz (MTS = 4 x 600 = 2400MHz) + */ +- +-/* data rate is reference clock mul 24 = 2400 */ + MEM_PLL_RAT=24 ++MEM_PLL_CFG=3 + MEM2_PLL_RAT=24 ++MEM2_PLL_CFG=3 +diff --git a/lx2160acex7/include/pll_xxxx_xxx_2600.rcwi b/lx2160acex7/include/pll_xxxx_xxx_2600.rcwi +index 404d52a..d72047d 100644 +--- a/lx2160acex7/include/pll_xxxx_xxx_2600.rcwi ++++ b/lx2160acex7/include/pll_xxxx_xxx_2600.rcwi +@@ -1,7 +1,12 @@ + /* + * DDR Rate: 2600MHz ++ * ++ * DDR PHY Clock (half ddr clock, quarter mts rate) ++ * multiplier = 26 (26) ++ * divider = 4 (3) ++ * 100MHz x 26 / 4 = 650MHz (MTS = 4 x 650 = 2600MHz) + */ +- +-/* data rate is reference clock mul 26 = 2600 */ + MEM_PLL_RAT=26 ++MEM_PLL_CFG=3 + MEM2_PLL_RAT=26 ++MEM2_PLL_CFG=3 +diff --git a/lx2160acex7/include/pll_xxxx_xxx_2900.rcwi b/lx2160acex7/include/pll_xxxx_xxx_2900.rcwi +index 2ba2426..9ad274f 100644 +--- a/lx2160acex7/include/pll_xxxx_xxx_2900.rcwi ++++ b/lx2160acex7/include/pll_xxxx_xxx_2900.rcwi +@@ -1,7 +1,12 @@ + /* + * DDR Rate: 2900MHz ++ * ++ * DDR PHY Clock (half ddr clock, quarter mts rate) ++ * multiplier = 29 (29) ++ * divider = 4 (3) ++ * 100MHz x 29 / 4 = 725MHz (MTS = 4 x 725 = 2900MHz) + */ +- +-/* data rate is reference clock mul 29 = 2900 */ + MEM_PLL_RAT=29 ++MEM_PLL_CFG=3 + MEM2_PLL_RAT=29 ++MEM2_PLL_CFG=3 +diff --git a/lx2160acex7/include/pll_xxxx_xxx_3200.rcwi b/lx2160acex7/include/pll_xxxx_xxx_3200.rcwi +index cbc2cf4..abf7e9d 100644 +--- a/lx2160acex7/include/pll_xxxx_xxx_3200.rcwi ++++ b/lx2160acex7/include/pll_xxxx_xxx_3200.rcwi +@@ -1,7 +1,12 @@ + /* + * DDR Rate: 3200MHz ++ * ++ * DDR PHY Clock (half ddr clock, quarter mts rate) ++ * multiplier = 32 (32) ++ * divider = 4 (3) ++ * 100MHz x 32 / 4 = 800MHz (MTS = 4 x 800 = 3200MHz) + */ +- +-/* data rate is reference clock mul 32 = 3200 */ + MEM_PLL_RAT=32 ++MEM_PLL_CFG=3 + MEM2_PLL_RAT=32 ++MEM2_PLL_CFG=3 +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0003-lx2160acex7-add-separate-configurations-for-flexspi-.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0003-lx2160acex7-add-separate-configurations-for-flexspi-.patch new file mode 100644 index 000000000000..58c4f6e6c8d5 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0003-lx2160acex7-add-separate-configurations-for-flexspi-.patch @@ -0,0 +1,894 @@ +From 229c609e139b5f95ea96c03dc084ba53b4f09d5e Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sat, 28 Sep 2024 12:24:13 +0200 +Subject: [PATCH] lx2160acex7: add separate configurations for flexspi and + sdhc1 boot + +Signed-off-by: Josua Mayer +--- + .../rcw_2000_700_2400_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2000_700_2400_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2000_700_2600_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2000_700_2600_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2000_700_2900_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2000_700_2900_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2000_700_3200_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2000_700_3200_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2200_700_2400_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2200_700_2400_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2200_700_2600_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2200_700_2600_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2200_700_2900_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2200_700_2900_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2200_700_3200_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2200_700_3200_8_5_2_xspi.rcw} | 2 ++ + lx2160acex7/include/common_pbi.rcwi | 4 +++ + .../rcw_2000_700_2400_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2000_700_2400_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2000_700_2600_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2000_700_2600_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2000_700_2900_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2000_700_2900_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2000_700_3200_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2000_700_3200_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2200_700_2400_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2200_700_2400_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2200_700_2600_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2200_700_2600_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2200_700_2900_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2200_700_2900_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2200_700_3200_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2200_700_3200_8_5_2_xspi.rcw} | 2 ++ + 33 files changed, 436 insertions(+) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw + rename lx2160acex7/clearfog-cx/{rcw_2000_700_2400_8_5_2.rcw => rcw_2000_700_2400_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw + rename lx2160acex7/clearfog-cx/{rcw_2000_700_2600_8_5_2.rcw => rcw_2000_700_2600_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw + rename lx2160acex7/clearfog-cx/{rcw_2000_700_2900_8_5_2.rcw => rcw_2000_700_2900_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw + rename lx2160acex7/clearfog-cx/{rcw_2000_700_3200_8_5_2.rcw => rcw_2000_700_3200_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2400_8_5_2.rcw => rcw_2200_700_2400_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2600_8_5_2.rcw => rcw_2200_700_2600_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2900_8_5_2.rcw => rcw_2200_700_2900_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw + rename lx2160acex7/clearfog-cx/{rcw_2200_700_3200_8_5_2.rcw => rcw_2200_700_3200_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw + rename lx2160acex7_rev2/clearfog-cx/{rcw_2000_700_2400_8_5_2.rcw => rcw_2000_700_2400_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw + rename lx2160acex7_rev2/clearfog-cx/{rcw_2000_700_2600_8_5_2.rcw => rcw_2000_700_2600_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw + rename lx2160acex7_rev2/clearfog-cx/{rcw_2000_700_2900_8_5_2.rcw => rcw_2000_700_2900_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw + rename lx2160acex7_rev2/clearfog-cx/{rcw_2000_700_3200_8_5_2.rcw => rcw_2000_700_3200_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2400_8_5_2.rcw => rcw_2200_700_2400_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2600_8_5_2.rcw => rcw_2200_700_2600_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2900_8_5_2.rcw => rcw_2200_700_2900_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_3200_8_5_2.rcw => rcw_2200_700_3200_8_5_2_xspi.rcw} (93%) + +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..0299002 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2.rcw +rename to lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_xspi.rcw +index ba0f82c..9cb1229 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2400 MT/s + * + * Silicon 1.0 ++ * Boot from XSPI + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..90a27ac +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2.rcw +rename to lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_xspi.rcw +index b1723d3..5a3f820 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2600 MT/s + * + * Silicon 1.0 ++ * Boot from XSPI + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..3a08744 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2.rcw +rename to lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_xspi.rcw +index fa59785..ace0f0a 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2900 MT/s + * + * Silicon 1.0 ++ * Boot from XSPI + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..19a3af1 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2.rcw +rename to lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_xspi.rcw +index 90ac8a4..2c7bbed 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 3200 MT/s + * + * Silicon 1.0 ++ * Boot from XSPI + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..bf7af38 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw +index 464a285..f23be28 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2400 MT/s + * + * Silicon 1.0 ++ * Boot from XSPI + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..ff778ec +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw +index 1ef7db6..62cf89e 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2600 MT/s + * + * Silicon 1.0 ++ * Boot from XSPI + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..90cd09c +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw +index d021306..13ec066 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2900 MT/s + * + * Silicon 1.0 ++ * Boot from XSPI + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..88731fa +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw +index bfef1d4..b80f8cb 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 3200 MT/s + * + * Silicon 1.0 ++ * Boot from XSPI + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +diff --git a/lx2160acex7/include/common_pbi.rcwi b/lx2160acex7/include/common_pbi.rcwi +index 0c28f92..848d48b 100644 +--- a/lx2160acex7/include/common_pbi.rcwi ++++ b/lx2160acex7/include/common_pbi.rcwi +@@ -11,7 +11,11 @@ write 0x2320000,0x20000000 + #include <../lx2160asi/scratchrw1.rcw> + + /* Boot Location Pointer */ ++#if defined(LX_BOOTSOURCE_SDHC1) + #include <../lx2160asi/bootlocptr_sd.rcw> ++#elif defined(LX_BOOTSOURCE_XSPI) ++#include <../lx2160asi/bootlocptr_nor.rcw> ++#endif + + /* Errata for SATA controller */ + #include <../lx2160asi/a010554.rcw> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..b77ed2c +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_xspi.rcw +index 1c23c5c..5c11864 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2400 MT/s + * + * Silicon 2.0 ++ * Boot from XSPI + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..2d19602 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_xspi.rcw +index 87391ab..21df735 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2600 MT/s + * + * Silicon 2.0 ++ * Boot from XSPI + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..d141116 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_xspi.rcw +index 9114f36..d128916 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2900 MT/s + * + * Silicon 2.0 ++ * Boot from XSPI + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..8b5ec8d +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_xspi.rcw +index 7e97984..55d8bc1 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 3200 MT/s + * + * Silicon 2.0 ++ * Boot from XSPI + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..7763a4a +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw +index d59ceed..9643b52 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2400 MT/s + * + * Silicon 2.0 ++ * Boot from XSPI + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..b238680 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw +index 1bf815b..79cea0d 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2600 MT/s + * + * Silicon 2.0 ++ * Boot from XSPI + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..46b16ab +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw +index 01138dc..b12898a 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2900 MT/s + * + * Silicon 2.0 ++ * Boot from XSPI + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..dc9180f +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw +index e99a12b..c2ff13a 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 3200 MT/s + * + * Silicon 2.0 ++ * Boot from XSPI + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0004-lx2160acex7-rename-sdhc1-config-to-generic-sdhc-for-.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0004-lx2160acex7-rename-sdhc1-config-to-generic-sdhc-for-.patch new file mode 100644 index 000000000000..dfdd0b2232b0 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0004-lx2160acex7-rename-sdhc1-config-to-generic-sdhc-for-.patch @@ -0,0 +1,149 @@ +From 8756b34d63f7357f7309bfa27fd175b198285bae Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sat, 28 Sep 2024 14:54:36 +0200 +Subject: [PATCH] lx2160acex7: rename sdhc1 config to generic sdhc, for both + sd & emmc + +Both sdhc1 and sdhc2 boot can share same rcw. +They use identical boot location pointer values, differences were only +in old rcw with explicit block-copy from boot media to ocram. + +This block-copy is not required for either spi, emmc or sd boot. + +Signed-off-by: Josua Mayer +--- + ...0_8_5_2_sdhc1.rcw => rcw_2000_700_2400_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2000_700_2600_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2000_700_2900_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2000_700_3200_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2200_700_2400_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2200_700_2600_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2200_700_2900_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2200_700_3200_8_5_2_sdhc.rcw} | 0 + lx2160acex7/include/common.rcwi | 8 ++++++-- + lx2160acex7/include/common_pbi.rcwi | 2 +- + ...0_8_5_2_sdhc1.rcw => rcw_2000_700_2400_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2000_700_2600_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2000_700_2900_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2000_700_3200_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2200_700_2400_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2200_700_2600_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2200_700_2900_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2200_700_3200_8_5_2_sdhc.rcw} | 0 + 18 files changed, 7 insertions(+), 3 deletions(-) + rename lx2160acex7/clearfog-cx/{rcw_2000_700_2400_8_5_2_sdhc1.rcw => rcw_2000_700_2400_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7/clearfog-cx/{rcw_2000_700_2600_8_5_2_sdhc1.rcw => rcw_2000_700_2600_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7/clearfog-cx/{rcw_2000_700_2900_8_5_2_sdhc1.rcw => rcw_2000_700_2900_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7/clearfog-cx/{rcw_2000_700_3200_8_5_2_sdhc1.rcw => rcw_2000_700_3200_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2400_8_5_2_sdhc1.rcw => rcw_2200_700_2400_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2600_8_5_2_sdhc1.rcw => rcw_2200_700_2600_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2900_8_5_2_sdhc1.rcw => rcw_2200_700_2900_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_3200_8_5_2_sdhc1.rcw => rcw_2200_700_3200_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2000_700_2400_8_5_2_sdhc1.rcw => rcw_2000_700_2400_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2000_700_2600_8_5_2_sdhc1.rcw => rcw_2000_700_2600_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2000_700_2900_8_5_2_sdhc1.rcw => rcw_2000_700_2900_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2000_700_3200_8_5_2_sdhc1.rcw => rcw_2000_700_3200_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2400_8_5_2_sdhc1.rcw => rcw_2200_700_2400_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2600_8_5_2_sdhc1.rcw => rcw_2200_700_2600_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2900_8_5_2_sdhc1.rcw => rcw_2200_700_2900_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_3200_8_5_2_sdhc1.rcw => rcw_2200_700_3200_8_5_2_sdhc.rcw} (100%) + +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw +rename to lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw +rename to lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw +rename to lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw +rename to lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw +diff --git a/lx2160acex7/include/common.rcwi b/lx2160acex7/include/common.rcwi +index 5523318..c76b174 100644 +--- a/lx2160acex7/include/common.rcwi ++++ b/lx2160acex7/include/common.rcwi +@@ -11,8 +11,12 @@ C8_PLL_SEL=0 + HWA_CGA_M1_CLK_SEL=1 + /* Cluster group B clock is PLL2 div 2 (for DCE) */ + HWA_CGB_M1_CLK_SEL=6 +-/* fall-back boot-mode is ocram, when DCFG bit location pointer registers are null */ +-BOOT_LOC=21 // TODO: test if SPI boot still functional ++/* ++ * fall-back boot-mode when DCFG boot location pointer registers are null ++ * - 0b10101 (21): OCRAM ++ * - 0b11010 (26): XSPI ++ */ ++BOOT_LOC=21 + /* SYSCLK is 100MHz */ + SYSCLK_FREQ=600 + /* USB-3.0 clock is 100MHz */ +diff --git a/lx2160acex7/include/common_pbi.rcwi b/lx2160acex7/include/common_pbi.rcwi +index 848d48b..36b723d 100644 +--- a/lx2160acex7/include/common_pbi.rcwi ++++ b/lx2160acex7/include/common_pbi.rcwi +@@ -10,7 +10,7 @@ write 0x2320000,0x20000000 + /* Errata to write on scratch reg for validation */ + #include <../lx2160asi/scratchrw1.rcw> + +-/* Boot Location Pointer */ ++/* Set Boot Location Pointer (Fall-back when unset is BOOT_LOC) */ + #if defined(LX_BOOTSOURCE_SDHC1) + #include <../lx2160asi/bootlocptr_sd.rcw> + #elif defined(LX_BOOTSOURCE_XSPI) +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0005-add-loadc-jumpc-and-jump-to-pbi-instructions.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0005-add-loadc-jumpc-and-jump-to-pbi-instructions.patch new file mode 100644 index 000000000000..207a4e723dea --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0005-add-loadc-jumpc-and-jump-to-pbi-instructions.patch @@ -0,0 +1,55 @@ +From 22e16d5c3969a2fdfdb23423a8d28d5e80eea987 Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury +Date: Mon, 23 Mar 2020 12:16:13 +0200 +Subject: [PATCH 5/6] add loadc, jumpc and jump to pbi instructions + +Add 'load conditional', 'jump condidional' and 'jump' to PBI +instructions. + +Signed-off-by: Rabeeh Khoury +--- + rcw.py | 28 ++++++++++++++++++++++++++++ + 1 file changed, 28 insertions(+) + +diff --git a/rcw.py b/rcw.py +index e7d3795..bcd088d 100755 +--- a/rcw.py ++++ b/rcw.py +@@ -330,6 +330,34 @@ def build_pbi(lines): + v2 = struct.pack(endianess + 'L', p2) + subsection += v1 + subsection += v2 ++ elif op == 'loadc': ++ if p1 == None or p2 == None: ++ print('Error: "loadc" instruction requires two parameters') ++ return '' ++ v1 = struct.pack(endianess + 'L', 0x80140000) ++ v2 = struct.pack(endianess + 'L', p1) ++ v3 = struct.pack(endianess + 'L', p2) ++ subsection += v1 ++ subsection += v2 ++ subsection += v3 ++ elif op == 'jumpc': ++ if p1 == None or p2 == None: ++ print('Error: "jumpc" instruction requires two parameters') ++ return '' ++ v1 = struct.pack(endianess + 'L', 0x80850000) ++ v2 = struct.pack(endianess + 'L', p1) ++ v3 = struct.pack(endianess + 'L', p2) ++ subsection += v1 ++ subsection += v2 ++ subsection += v3 ++ elif op == 'jump': ++ if p1 == None: ++ print('Error: "jump" instruction requires a parameter') ++ return '' ++ v1 = struct.pack(endianess + 'L', 0x80840000) ++ v2 = struct.pack(endianess + 'L', p1) ++ subsection += v1 ++ subsection += v2 + elif op == 'awrite': + if opsize == '.b5': + # altconfig write with B=5 (16 bytes) +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0006-lx2160acex7-add-configuration-for-both-sdhc-xspi.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0006-lx2160acex7-add-configuration-for-both-sdhc-xspi.patch new file mode 100644 index 000000000000..9c79a8050a4d --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0006-lx2160acex7-add-configuration-for-both-sdhc-xspi.patch @@ -0,0 +1,836 @@ +From ac13e12390764b8770227c0032f62994ece7e17b Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sat, 28 Sep 2024 17:40:04 +0200 +Subject: [PATCH 6/6] lx2160acex7: add configuration for both sdhc & xspi + +Add "auto" configuration supporting both sdhc and xspi boot sources. +A special pbi section is added setting boot location pointer according +to rcw source. + +Signed-off-by: Josua Mayer +--- + .../rcw_2000_700_2400_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2000_700_2400_8_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_2600_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2000_700_2600_8_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_2900_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2000_700_2900_8_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_3200_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2000_700_3200_8_5_2_sdhc.rcw | 2 +- + .../rcw_2200_700_2400_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2200_700_2400_8_5_2_sdhc.rcw | 2 +- + .../rcw_2200_700_2600_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2200_700_2600_8_5_2_sdhc.rcw | 2 +- + .../rcw_2200_700_2900_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2200_700_2900_8_5_2_sdhc.rcw | 2 +- + .../rcw_2200_700_3200_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2200_700_3200_8_5_2_sdhc.rcw | 2 +- + lx2160acex7/include/common_pbi.rcwi | 16 ++--- + .../rcw_2000_700_2400_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2000_700_2400_8_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_2600_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2000_700_2600_8_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_2900_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2000_700_2900_8_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_3200_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2000_700_3200_8_5_2_sdhc.rcw | 2 +- + .../rcw_2200_700_2400_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2200_700_2400_8_5_2_sdhc.rcw | 2 +- + .../rcw_2200_700_2600_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2200_700_2600_8_5_2_sdhc.rcw | 2 +- + .../rcw_2200_700_2900_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2200_700_2900_8_5_2_sdhc.rcw | 2 +- + .../rcw_2200_700_3200_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2200_700_3200_8_5_2_sdhc.rcw | 2 +- + lx2160asi/bootlocptr_auto.rcw | 60 +++++++++++++++++++ + 34 files changed, 453 insertions(+), 23 deletions(-) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw + create mode 100644 lx2160asi/bootlocptr_auto.rcw + +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw +new file mode 100644 +index 0000000..ba0f82c +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw +index 0299002..4d67915 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 1 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw +new file mode 100644 +index 0000000..b1723d3 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw +index 90a27ac..0424418 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 1 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw +new file mode 100644 +index 0000000..fa59785 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw +index 3a08744..be0d219 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 1 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw +new file mode 100644 +index 0000000..90ac8a4 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw +index 19a3af1..e1f9092 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 1 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw +new file mode 100644 +index 0000000..464a285 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw +index bf7af38..6f696f5 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 1 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw +new file mode 100644 +index 0000000..1ef7db6 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw +index ff778ec..46d84cb 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 1 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw +new file mode 100644 +index 0000000..d021306 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw +index 90cd09c..55e6b2b 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 1 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw +new file mode 100644 +index 0000000..bfef1d4 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw +index 88731fa..2978d72 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 1 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +diff --git a/lx2160acex7/include/common_pbi.rcwi b/lx2160acex7/include/common_pbi.rcwi +index 36b723d..7dd4be7 100644 +--- a/lx2160acex7/include/common_pbi.rcwi ++++ b/lx2160acex7/include/common_pbi.rcwi +@@ -10,13 +10,6 @@ write 0x2320000,0x20000000 + /* Errata to write on scratch reg for validation */ + #include <../lx2160asi/scratchrw1.rcw> + +-/* Set Boot Location Pointer (Fall-back when unset is BOOT_LOC) */ +-#if defined(LX_BOOTSOURCE_SDHC1) +-#include <../lx2160asi/bootlocptr_sd.rcw> +-#elif defined(LX_BOOTSOURCE_XSPI) +-#include <../lx2160asi/bootlocptr_nor.rcw> +-#endif +- + /* Errata for SATA controller */ + #include <../lx2160asi/a010554.rcw> + +@@ -57,3 +50,12 @@ write 0x2320000,0x20000000 + .pbi + write 0x1e00900,0x00000014 + .end ++ ++/* Set Boot Location Pointer (Fall-back when unset is BOOT_LOC) */ ++#if defined(LX_BOOTSOURCE_SDHC) ++#include <../lx2160asi/bootlocptr_sd.rcw> ++#elif defined(LX_BOOTSOURCE_XSPI) ++#include <../lx2160asi/bootlocptr_nor.rcw> ++#else ++#include <../lx2160asi/bootlocptr_auto.rcw> ++#endif +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw +new file mode 100644 +index 0000000..1c23c5c +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw +index b77ed2c..c7b307e 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 2 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw +new file mode 100644 +index 0000000..87391ab +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw +index 2d19602..a4c254c 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 2 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw +new file mode 100644 +index 0000000..9114f36 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw +index d141116..88ea5f2 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 2 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw +new file mode 100644 +index 0000000..7e97984 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw +index 8b5ec8d..486ade8 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 2 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw +new file mode 100644 +index 0000000..d59ceed +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw +index 7763a4a..20f7d58 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 2 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw +new file mode 100644 +index 0000000..1bf815b +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw +index b238680..0f93cf2 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 2 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw +new file mode 100644 +index 0000000..01138dc +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw +index 46b16ab..a06759e 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 2 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw +new file mode 100644 +index 0000000..e99a12b +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw +index dc9180f..dbc0a91 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 2 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +diff --git a/lx2160asi/bootlocptr_auto.rcw b/lx2160asi/bootlocptr_auto.rcw +new file mode 100644 +index 0000000..24c7286 +--- /dev/null ++++ b/lx2160asi/bootlocptr_auto.rcw +@@ -0,0 +1,60 @@ ++/* ++ * Generic code for auto booting. ++ * ++ * For each boot source test rcw source, and set bootlocl/h accordingly. ++ * ++ * For single boot-source atf create_pbl adds block copy commands ++ * and sets boot location pointer. ++ * Automatic boot relies on rcw to include those commands; ++ * create_pbl merely replaces their arguments. ++ * ++ * Copyright 2020 Rabeeh Khoury ++ * Copyright 2024 Josua Mayer ++ * ++ * Changelog: ++ * - 28/09/2024: changed formatting and comments ++ */ ++.pbi ++/* Load condition PORSR1 and mask RCW_SRC */ ++loadc 0x01e00000,0x07800000 ++ ++/* If it is 0x8 << 23 (SDHC1) then skip the following jump command */ ++jumpc 0x00000014,0x04000000 ++ ++/* skip sdhc1 boot */ ++jump 0x28 /* this jump + blockcopy + write = (4+4+4+4)+(4+4)+2x(4+4)=40 bytes */ ++/* copy blocks from sdhc1 (atf create_pbl will fixup arguments) */ ++blockcopy 0x08,0x0000a000,0x1800d000,0x00020000 ++ ++/* set boot location pointer for sdhc */ ++write 0x01e00400,0x1800d000 ++write 0x01e00404,0x00000000 ++ ++/* If it is 0x9 << 23 (SDHC2) then skip the following jump command */ ++loadc 0x01e00000,0x07800000 ++jumpc 0x00000014,0x04800000 ++ ++/* skip sdhc2 boot */ ++jump 0x28 /* this jump + blockcopy + write = (4+4+4+4)+(4+4)+2x(4+4)=40 bytes */ ++ ++/* copy blocks from sdhc1 (atf create_pbl will fixup arguments) */ ++blockcopy 0x09,0x0000a000,0x1800d000,0x00020000 ++ ++/* set boot location pointer for sdhc */ ++write 0x01e00400,0x1800d000 ++write 0x01e00404,0x00000000 ++ ++/* If it is 0xf << 23 (XSPI) then skip the following jump command */ ++loadc 0x01e00000,0x07800000 ++jumpc 0x00000014,0x07800000 ++ ++/* skip xspi boot */ ++jump 0x28 /* this jump + blockcopy + write = (4+4+4+4)+(4+4)+2x(4+4)=40 bytes */ ++ ++/* copy blocks from xspi (atf create_pbl will fixup arguments) */ ++blockcopy 0x0f,0x20009000,0x1800d000,0x00020000 ++ ++/* set boot location pointer for xspi */ ++write 0x01e00400,0x20100000 ++write 0x01e00404,0x00000000 ++.end +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0007-bootlocptr-reduce-size-of-pbi-section.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0007-bootlocptr-reduce-size-of-pbi-section.patch new file mode 100644 index 000000000000..7ca4db49763d --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0007-bootlocptr-reduce-size-of-pbi-section.patch @@ -0,0 +1,90 @@ +From 86b80b4442027c2fa4f22bb3aa602abb0e15ff85 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Mon, 7 Oct 2024 14:37:13 +0200 +Subject: [PATCH] bootlocptr: reduce size of pbi section + +- Remove duplicate 'loadc' commands, the condition register value is not + affected by 'jump' and 'jumpc'. Saves 6 words. +- Remove 'write' command for bootlocptr high byte, its value zero is + shared by all boot sources and implicitly initialised. Saves 6 words. + +Signed-off-by: Josua Mayer +--- + lx2160asi/bootlocptr_auto.rcw | 31 +++++++++++-------------------- + 1 file changed, 11 insertions(+), 20 deletions(-) + +diff --git a/lx2160asi/bootlocptr_auto.rcw b/lx2160asi/bootlocptr_auto.rcw +index 24c7286..08e7916 100644 +--- a/lx2160asi/bootlocptr_auto.rcw ++++ b/lx2160asi/bootlocptr_auto.rcw +@@ -5,56 +5,47 @@ + * + * For single boot-source atf create_pbl adds block copy commands + * and sets boot location pointer. +- * Automatic boot relies on rcw to include those commands; +- * create_pbl merely replaces their arguments. ++ * Automatic boot relies on rcw to include the blockcopy and bootlocptr ++ * commands, create_pbl then replaces their arguments. + * + * Copyright 2020 Rabeeh Khoury + * Copyright 2024 Josua Mayer + * + * Changelog: + * - 28/09/2024: changed formatting and comments ++ * - 07/10/2024: removed unnecessary commands to reduce size + */ + .pbi + /* Load condition PORSR1 and mask RCW_SRC */ + loadc 0x01e00000,0x07800000 + +-/* If it is 0x8 << 23 (SDHC1) then skip the following jump command */ ++/* If condition is 0x8 << 23 (SDHC1) then skip the following jump command */ + jumpc 0x00000014,0x04000000 + + /* skip sdhc1 boot */ +-jump 0x28 /* this jump + blockcopy + write = (4+4+4+4)+(4+4)+2x(4+4)=40 bytes */ ++jump 0x20 /* this jump + blockcopy = (4+4+4+4)+(4+4)=24 bytes */ ++ + /* copy blocks from sdhc1 (atf create_pbl will fixup arguments) */ + blockcopy 0x08,0x0000a000,0x1800d000,0x00020000 +- +-/* set boot location pointer for sdhc */ + write 0x01e00400,0x1800d000 +-write 0x01e00404,0x00000000 + +-/* If it is 0x9 << 23 (SDHC2) then skip the following jump command */ +-loadc 0x01e00000,0x07800000 ++/* If condition is 0x9 << 23 (SDHC2) then skip the following jump command */ + jumpc 0x00000014,0x04800000 + + /* skip sdhc2 boot */ +-jump 0x28 /* this jump + blockcopy + write = (4+4+4+4)+(4+4)+2x(4+4)=40 bytes */ ++jump 0x20 /* this jump + blockcopy = (4+4+4+4)+(4+4)=24 bytes */ + + /* copy blocks from sdhc1 (atf create_pbl will fixup arguments) */ + blockcopy 0x09,0x0000a000,0x1800d000,0x00020000 +- +-/* set boot location pointer for sdhc */ + write 0x01e00400,0x1800d000 +-write 0x01e00404,0x00000000 + +-/* If it is 0xf << 23 (XSPI) then skip the following jump command */ +-loadc 0x01e00000,0x07800000 ++/* If condition is 0xf << 23 (XSPI) then skip the following jump command */ + jumpc 0x00000014,0x07800000 + + /* skip xspi boot */ +-jump 0x28 /* this jump + blockcopy + write = (4+4+4+4)+(4+4)+2x(4+4)=40 bytes */ ++jump 0x20 /* this jump + blockcopy = (4+4+4+4)+(4+4)=24 bytes */ + + /* copy blocks from xspi (atf create_pbl will fixup arguments) */ + blockcopy 0x0f,0x20009000,0x1800d000,0x00020000 +- +-/* set boot location pointer for xspi */ +-write 0x01e00400,0x20100000 +-write 0x01e00404,0x00000000 ++write 0x01e00400,0x1800d000 + .end +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0008-lx2160acex7-change-2.2GHz-configuration-platform-clo.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0008-lx2160acex7-change-2.2GHz-configuration-platform-clo.patch new file mode 100644 index 000000000000..fbbbdffc2876 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0008-lx2160acex7-change-2.2GHz-configuration-platform-clo.patch @@ -0,0 +1,475 @@ +From 7ef0c57ae7c852bb8f35310b0bd5708bb2a98c4a Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Tue, 8 Oct 2024 12:30:42 +0200 +Subject: [PATCH 8/9] lx2160acex7: change 2.2GHz configuration platform clock + to 750MHz + +2.2GHz cpu clock is only for accordingly binned part number from NXP. +These parts support platform clock up to 750MHz. + +Update the configuration accordingly to 2200_750_xxxx and drop the +combination with 2200_700. + +Signed-off-by: Josua Mayer +--- + ...2400_8_5_2_auto.rcw => rcw_2200_750_2400_8_5_2_auto.rcw} | 2 +- + ...2400_8_5_2_sdhc.rcw => rcw_2200_750_2400_8_5_2_sdhc.rcw} | 2 +- + ...2400_8_5_2_xspi.rcw => rcw_2200_750_2400_8_5_2_xspi.rcw} | 2 +- + ...2600_8_5_2_auto.rcw => rcw_2200_750_2600_8_5_2_auto.rcw} | 2 +- + ...2600_8_5_2_sdhc.rcw => rcw_2200_750_2600_8_5_2_sdhc.rcw} | 2 +- + ...2600_8_5_2_xspi.rcw => rcw_2200_750_2600_8_5_2_xspi.rcw} | 2 +- + ...2900_8_5_2_auto.rcw => rcw_2200_750_2900_8_5_2_auto.rcw} | 2 +- + ...2900_8_5_2_sdhc.rcw => rcw_2200_750_2900_8_5_2_sdhc.rcw} | 2 +- + ...2900_8_5_2_xspi.rcw => rcw_2200_750_2900_8_5_2_xspi.rcw} | 2 +- + ...3200_8_5_2_auto.rcw => rcw_2200_750_3200_8_5_2_auto.rcw} | 2 +- + ...3200_8_5_2_sdhc.rcw => rcw_2200_750_3200_8_5_2_sdhc.rcw} | 2 +- + ...3200_8_5_2_xspi.rcw => rcw_2200_750_3200_8_5_2_xspi.rcw} | 2 +- + .../{pll_2200_700_xxxx.rcwi => pll_2200_750_xxxx.rcwi} | 6 +++--- + ...2400_8_5_2_auto.rcw => rcw_2200_750_2400_8_5_2_auto.rcw} | 2 +- + ...2400_8_5_2_sdhc.rcw => rcw_2200_750_2400_8_5_2_sdhc.rcw} | 2 +- + ...2400_8_5_2_xspi.rcw => rcw_2200_750_2400_8_5_2_xspi.rcw} | 2 +- + ...2600_8_5_2_auto.rcw => rcw_2200_750_2600_8_5_2_auto.rcw} | 2 +- + ...2600_8_5_2_sdhc.rcw => rcw_2200_750_2600_8_5_2_sdhc.rcw} | 2 +- + ...2600_8_5_2_xspi.rcw => rcw_2200_750_2600_8_5_2_xspi.rcw} | 2 +- + ...2900_8_5_2_auto.rcw => rcw_2200_750_2900_8_5_2_auto.rcw} | 2 +- + ...2900_8_5_2_sdhc.rcw => rcw_2200_750_2900_8_5_2_sdhc.rcw} | 2 +- + ...2900_8_5_2_xspi.rcw => rcw_2200_750_2900_8_5_2_xspi.rcw} | 2 +- + ...3200_8_5_2_auto.rcw => rcw_2200_750_3200_8_5_2_auto.rcw} | 2 +- + ...3200_8_5_2_sdhc.rcw => rcw_2200_750_3200_8_5_2_sdhc.rcw} | 2 +- + ...3200_8_5_2_xspi.rcw => rcw_2200_750_3200_8_5_2_xspi.rcw} | 2 +- + 25 files changed, 27 insertions(+), 27 deletions(-) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2400_8_5_2_auto.rcw => rcw_2200_750_2400_8_5_2_auto.rcw} (91%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2400_8_5_2_sdhc.rcw => rcw_2200_750_2400_8_5_2_sdhc.rcw} (91%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2400_8_5_2_xspi.rcw => rcw_2200_750_2400_8_5_2_xspi.rcw} (91%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2600_8_5_2_auto.rcw => rcw_2200_750_2600_8_5_2_auto.rcw} (91%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2600_8_5_2_sdhc.rcw => rcw_2200_750_2600_8_5_2_sdhc.rcw} (91%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2600_8_5_2_xspi.rcw => rcw_2200_750_2600_8_5_2_xspi.rcw} (91%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2900_8_5_2_auto.rcw => rcw_2200_750_2900_8_5_2_auto.rcw} (91%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2900_8_5_2_sdhc.rcw => rcw_2200_750_2900_8_5_2_sdhc.rcw} (91%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2900_8_5_2_xspi.rcw => rcw_2200_750_2900_8_5_2_xspi.rcw} (91%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_3200_8_5_2_auto.rcw => rcw_2200_750_3200_8_5_2_auto.rcw} (91%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_3200_8_5_2_sdhc.rcw => rcw_2200_750_3200_8_5_2_sdhc.rcw} (91%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_3200_8_5_2_xspi.rcw => rcw_2200_750_3200_8_5_2_xspi.rcw} (91%) + rename lx2160acex7/include/{pll_2200_700_xxxx.rcwi => pll_2200_750_xxxx.rcwi} (61%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2400_8_5_2_auto.rcw => rcw_2200_750_2400_8_5_2_auto.rcw} (91%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2400_8_5_2_sdhc.rcw => rcw_2200_750_2400_8_5_2_sdhc.rcw} (91%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2400_8_5_2_xspi.rcw => rcw_2200_750_2400_8_5_2_xspi.rcw} (91%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2600_8_5_2_auto.rcw => rcw_2200_750_2600_8_5_2_auto.rcw} (91%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2600_8_5_2_sdhc.rcw => rcw_2200_750_2600_8_5_2_sdhc.rcw} (91%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2600_8_5_2_xspi.rcw => rcw_2200_750_2600_8_5_2_xspi.rcw} (91%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2900_8_5_2_auto.rcw => rcw_2200_750_2900_8_5_2_auto.rcw} (91%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2900_8_5_2_sdhc.rcw => rcw_2200_750_2900_8_5_2_sdhc.rcw} (91%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2900_8_5_2_xspi.rcw => rcw_2200_750_2900_8_5_2_xspi.rcw} (91%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_3200_8_5_2_auto.rcw => rcw_2200_750_3200_8_5_2_auto.rcw} (91%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_3200_8_5_2_sdhc.rcw => rcw_2200_750_3200_8_5_2_sdhc.rcw} (91%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_3200_8_5_2_xspi.rcw => rcw_2200_750_3200_8_5_2_xspi.rcw} (91%) + +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw +index 464a285..533fba1 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw +@@ -13,7 +13,7 @@ + + #define LX_SR 1 + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw +index 6f696f5..845ab35 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 1 + #define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw +index f23be28..765758e 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 1 + #define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw +index 1ef7db6..c09807c 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw +@@ -13,7 +13,7 @@ + + #define LX_SR 1 + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw +index 46d84cb..7808b12 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 1 + #define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw +index 62cf89e..33bef8b 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 1 + #define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw +index d021306..0f3d8a3 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw +@@ -13,7 +13,7 @@ + + #define LX_SR 1 + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw +index 55e6b2b..68452e0 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 1 + #define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw +index 13ec066..0069109 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 1 + #define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw +index bfef1d4..aa2fb4b 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw +@@ -13,7 +13,7 @@ + + #define LX_SR 1 + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw +index 2978d72..6f06730 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 1 + #define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw +index b80f8cb..94dcc9b 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 1 + #define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/include/pll_2200_700_xxxx.rcwi b/lx2160acex7/include/pll_2200_750_xxxx.rcwi +similarity index 61% +rename from lx2160acex7/include/pll_2200_700_xxxx.rcwi +rename to lx2160acex7/include/pll_2200_750_xxxx.rcwi +index 91d1a9b..0f57b67 100644 +--- a/lx2160acex7/include/pll_2200_700_xxxx.rcwi ++++ b/lx2160acex7/include/pll_2200_750_xxxx.rcwi +@@ -1,11 +1,11 @@ + /* + * Core and Platform Clocks: +- * - Platform: 700MHz ++ * - Platform: 750MHz + * - Core: 2200MHz + */ + +-/* platform clock is system clock mul 14 div 2 = 700 */ +-SYS_PLL_RAT=14 ++/* platform clock is system clock mul 15 div 2 = 750 */ ++SYS_PLL_RAT=15 + + /* core clocks are 2200 */ + CGA_PLL1_RAT=22 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw +index d59ceed..4185ea6 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw +@@ -13,7 +13,7 @@ + + #define LX_SR 2 + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw +index 20f7d58..93b10d2 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 2 + #define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw +index 9643b52..feb3e42 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 2 + #define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw +index 1bf815b..e04fcfb 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw +@@ -13,7 +13,7 @@ + + #define LX_SR 2 + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw +index 0f93cf2..32225fe 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 2 + #define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw +index 79cea0d..6fbba40 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 2 + #define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw +index 01138dc..b9797ca 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw +@@ -13,7 +13,7 @@ + + #define LX_SR 2 + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw +index a06759e..a7b5bd2 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 2 + #define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw +index b12898a..273d91c 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 2 + #define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw +index e99a12b..046adc8 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw +@@ -13,7 +13,7 @@ + + #define LX_SR 2 + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw +index dbc0a91..9798b74 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 2 + #define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw +index c2ff13a..6b875e7 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 2 + #define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0009-lx2160acex7-add-configuration-for-fraction-ddr-speed.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0009-lx2160acex7-add-configuration-for-fraction-ddr-speed.patch new file mode 100644 index 000000000000..0e680661f350 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0009-lx2160acex7-add-configuration-for-fraction-ddr-speed.patch @@ -0,0 +1,420 @@ +From 51af4e2a98e234e27a0127b2455b6049ce8097e2 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Tue, 8 Oct 2024 12:44:10 +0200 +Subject: [PATCH] lx2160acex7: add configuration for fraction ddr speed 2666 + +Signed-off-by: Josua Mayer +--- + .../rcw_2000_700_2666_8_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_2666_8_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2666_8_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2666_8_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_2666_8_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2666_8_5_2_xspi.rcw | 25 +++++++++++++++++++ + lx2160acex7/include/pll_xxxx_xxx_2666.rcwi | 12 +++++++++ + .../rcw_2000_700_2666_8_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_2666_8_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2666_8_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2666_8_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_2666_8_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2666_8_5_2_xspi.rcw | 25 +++++++++++++++++++ + 13 files changed, 304 insertions(+) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw + create mode 100644 lx2160acex7/include/pll_xxxx_xxx_2666.rcwi + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw + +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw +new file mode 100644 +index 0000000..8178257 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw +new file mode 100644 +index 0000000..6f362cf +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw +new file mode 100644 +index 0000000..cb6614a +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw +new file mode 100644 +index 0000000..6822342 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw +new file mode 100644 +index 0000000..f111731 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw +new file mode 100644 +index 0000000..112f017 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/include/pll_xxxx_xxx_2666.rcwi b/lx2160acex7/include/pll_xxxx_xxx_2666.rcwi +new file mode 100644 +index 0000000..06d3da1 +--- /dev/null ++++ b/lx2160acex7/include/pll_xxxx_xxx_2666.rcwi +@@ -0,0 +1,12 @@ ++/* ++ * DDR Rate: 2666MHz ++ * ++ * DDR PHY Clock (half ddr clock, quarter mts rate) ++ * multiplier = 20 (20) ++ * divider = 3 (2) ++ * 100MHz x 20 / 3 = 666MHz (MTS = 4 x 666 = 2666MHz) ++ */ ++MEM_PLL_RAT=20 ++MEM_PLL_CFG=2 ++MEM2_PLL_RAT=20 ++MEM2_PLL_CFG=2 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw +new file mode 100644 +index 0000000..73efdfa +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw +new file mode 100644 +index 0000000..5ac0305 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw +new file mode 100644 +index 0000000..ffc7388 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw +new file mode 100644 +index 0000000..0206680 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw +new file mode 100644 +index 0000000..0213f6c +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw +new file mode 100644 +index 0000000..d31d063 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0010-add-configuration-solidrun-internal-lx2160a-cex6-eva.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0010-add-configuration-solidrun-internal-lx2160a-cex6-eva.patch new file mode 100644 index 000000000000..e246e2741a25 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0010-add-configuration-solidrun-internal-lx2160a-cex6-eva.patch @@ -0,0 +1,220 @@ +From 19067dac1cea330e12cf3594cf6ca2a7a3d257be Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Fri, 11 Oct 2024 16:39:12 +0200 +Subject: [PATCH] add configuration solidrun internal lx2160a-cex6 evaluation + board + +Signed-off-by: Josua Mayer +--- + lx2160acex6_rev2/Makefile | 1 + + lx2160acex6_rev2/README | 0 + .../evb/rcw_2000_700_2900_3_3_2_auto.rcw | 22 +++++ + lx2160acex6_rev2/include/common.rcwi | 88 +++++++++++++++++++ + lx2160acex7/include/SD1_3.rcwi | 27 ++++++ + lx2160acex7/include/SD2_3.rcwi | 24 +++++ + 6 files changed, 162 insertions(+) + create mode 100644 lx2160acex6_rev2/Makefile + create mode 100644 lx2160acex6_rev2/README + create mode 100644 lx2160acex6_rev2/evb/rcw_2000_700_2900_3_3_2_auto.rcw + create mode 100644 lx2160acex6_rev2/include/common.rcwi + create mode 100644 lx2160acex7/include/SD1_3.rcwi + create mode 100644 lx2160acex7/include/SD2_3.rcwi + +diff --git a/lx2160acex6_rev2/Makefile b/lx2160acex6_rev2/Makefile +new file mode 100644 +index 0000000..f77e46b +--- /dev/null ++++ b/lx2160acex6_rev2/Makefile +@@ -0,0 +1 @@ ++include ../Makefile.inc +diff --git a/lx2160acex6_rev2/README b/lx2160acex6_rev2/README +new file mode 100644 +index 0000000..e69de29 +diff --git a/lx2160acex6_rev2/evb/rcw_2000_700_2900_3_3_2_auto.rcw b/lx2160acex6_rev2/evb/rcw_2000_700_2900_3_3_2_auto.rcw +new file mode 100644 +index 0000000..8d14387 +--- /dev/null ++++ b/lx2160acex6_rev2/evb/rcw_2000_700_2900_3_3_2_auto.rcw +@@ -0,0 +1,22 @@ ++/* ++ * SerDes Protocol 1 - 3 ++ * SerDes Protocol 2 - 3 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex6_rev2/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_3.rcwi> ++#include <../lx2160acex7/include/SD2_3.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> +diff --git a/lx2160acex6_rev2/include/common.rcwi b/lx2160acex6_rev2/include/common.rcwi +new file mode 100644 +index 0000000..8cc5ec7 +--- /dev/null ++++ b/lx2160acex6_rev2/include/common.rcwi +@@ -0,0 +1,88 @@ ++/* ++ * LX2160A COM-Express Type 6 Common Configuration ++ */ ++ ++/* C[5:8]_PLL are CG[5:8] div 1 */ ++C5_PLL_SEL=0 ++C6_PLL_SEL=0 ++C7_PLL_SEL=0 ++C8_PLL_SEL=0 ++/* Cluster group A clock is PLL1 div 1 (unused on LX2160A) */ ++HWA_CGA_M1_CLK_SEL=1 ++/* Cluster group B clock is PLL2 div 2 (for DCE) */ ++HWA_CGB_M1_CLK_SEL=6 ++/* ++ * fall-back boot-mode when DCFG boot location pointer registers are null ++ * - 0b10101 (21): OCRAM ++ * - 0b11010 (26): XSPI ++ */ ++BOOT_LOC=21 ++/* SYSCLK is 100MHz */ ++SYSCLK_FREQ=600 ++/* USB-3.0 clock is 100MHz */ ++USB3_CLK_FSEL=39 ++ ++/* IIC1 is I2C */ ++IIC1_PMUX=0 ++/* IIC2 is SD Card-Detect */ ++IIC2_PMUX=6 ++/* IIC3 is I2C */ ++IIC3_PMUX=0 ++/* IIC4 is I2C */ ++IIC4_PMUX=0 ++/* IIC5 SCL/SDA are SPI3_SOUT/SPI3_SIN */ ++IIC5_PMUX=3 ++/* IIC6 is PHY reset gpio */ ++IIC6_PMUX=1 ++/* SDHC1 CMD/CLK/DAT[0:3]/VSEL are SDHC1 CMD/CLK/DAT[0:3]/SPI3_PCS0 */ ++SDHC1_BASE_PMUX=3 ++/* SDHC1_DS is SPI3_SCK */ ++SDHC1_DS_PMUX=2 ++/* SDHC1_CMD_DIR (A4) / SDHC1_DAT0_DIR (B3) / SDHC1_DAT123_DIR (C3) are SPI3_PCS[1:3] */ ++SDHC1_DIR_PMUX=3 ++/* USB[1:2]_DRVVBUS/PWRFAULT are GPIO4[28:25] (unused) */ ++USB_EXT_PMUX=1 ++/* XSPI1_A_DQS/SCK/CS0_B/CS1_B are SPI */ ++XSPI1_A_BASE_PMUX=0 ++/* XSPI1_A_DATA[3:0] are SPI */ ++XSPI1_A_DATA30_PMUX=0 ++/* XSPI1_A_DATA[7:4] are SPI */ ++XSPI1_A_DATA74_PMUX=0 ++/* ASLEEP is ASLEEP (unused, bootstrap) */ ++ASLEEP_PMUX=0 ++/* EVT[2:0] are GPIO3[14:12] */ ++EVT20_PMUX=1 ++/* EVT[4:3] are GPIO3[16:15] */ ++EVT43_PMUX=1 ++/* CLK_OUT is GPIO (unused) */ ++CLK_OUT_PMUX=1 ++/* IRQ[3:0] are GPIO3[3:0] */ ++IRQ03_00_PMUX=1 ++/* IRQ[7:4] are GPIO3[7:4] */ ++IRQ07_04_PMUX=1 ++/* IRQ[11:8] are GPIO3[11:8] */ ++IRQ11_08_PMUX=1 ++/* EC1_* are RGMII */ ++EC1_PMUX=0 ++/* EC2_* are GPIO4[23:12] */ ++EC2_PMUX=1 ++/* EC_GTX_CLK125 is PTP */ ++GTX_CLK_PMUX=0 ++/* UART1_SOUT/SIN are UART1 */ ++UART1_SOUTSIN_PMUX=0 ++/* UART1_RTS/CTS_B are UART3_SOUT/SIN */ ++UART1_RTSCTS_PMUX=2 ++/* UART2_SOUT/SIN are UART2 */ ++UART2_SOUTSIN_PMUX=0 ++/* UART2_RTS/CTS_B are UART4_SOUT/SIN */ ++UART2_RTSCTS_PMUX=2 ++/* SDHC2_CMD/DAT[3:0]/DS/CLK are SDHC */ ++SDHC2_BASE_PMUX=0 ++/* SDHC2_DAT[7:4] are SDHC */ ++SDHC2_DAT74_PMUX=0 ++ ++/* ++ * Original SolidRun Settings in LSDK-21.08 ++ * ++ * HWA_CGB_M1_CLK_SEL=7 // Cluster Group B PLL 2 / 3 is clock ++ */ +diff --git a/lx2160acex7/include/SD1_3.rcwi b/lx2160acex7/include/SD1_3.rcwi +new file mode 100644 +index 0000000..a49adb3 +--- /dev/null ++++ b/lx2160acex7/include/SD1_3.rcwi +@@ -0,0 +1,27 @@ ++/* ++ * Serdes 1 Reference Clocks: ++ * - PLLF = 100MHz ++ * - PLLS = 161.1328125MHz ++ */ ++ ++/* Serdes 1 Protocol 3: 4x10Gbps + 1xPCI-e-x4 */ ++SRDS_PRTCL_S1=3 ++ ++/* Enable Serdes 1 PLLF */ ++SRDS_PLL_PD_PLL1=0 ++ ++/* Don't use Serdes 1 PLLF for PLLS */ ++SRDS_INTRA_REF_CLK_S1=0 ++ ++/* Enable Serdes 1 PLLS */ ++SRDS_PLL_PD_PLL2=0 ++ ++/* ++ * Select Serdes 1 PLLF frequency 100MHz for pcie: Bit 0 = 0 ++ * Select Serdes 1 PLLS frequency 161.1328125MHz (not documented in RM) for usxgmii: Bit 1 = 1 ++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933) ++ */ ++SRDS_PLL_REF_CLK_SEL_S1=2 ++ ++/* Support up to PCI-e Gen 3 */ ++SRDS_DIV_PEX_S1=1 +diff --git a/lx2160acex7/include/SD2_3.rcwi b/lx2160acex7/include/SD2_3.rcwi +new file mode 100644 +index 0000000..724ed9f +--- /dev/null ++++ b/lx2160acex7/include/SD2_3.rcwi +@@ -0,0 +1,24 @@ ++/* ++ * Serdes 2 Reference Clocks: ++ * - PLLF = 100MHz ++ * - PLLS = 100MHz ++ */ ++ ++/* Serdes 2 Protocol 3: 2xPCI-e-x4 */ ++SRDS_PRTCL_S2=3 ++ ++/* Enable Serdes 2 PLLF */ ++SRDS_PLL_PD_PLL3=0 ++ ++/* Enable Serdes 2 PLLS */ ++SRDS_PLL_PD_PLL4=0 ++ ++/* Don't use Serdes 2 PLLF for PLLS */ ++SRDS_INTRA_REF_CLK_S2=0 ++ ++/* ++ * Select Serdes 2 PLLF frequency 100MHz (Bit 0) ++ * Select Serdes 2 PLLS frequency 100MHz (Bit 1) ++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933) ++ */ ++SRDS_PLL_REF_CLK_SEL_S2=0 +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0011-lx2160acex7-enable-A-050426-workaround-for-silicon-o.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0011-lx2160acex7-enable-A-050426-workaround-for-silicon-o.patch new file mode 100644 index 000000000000..2134c7c146d9 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0011-lx2160acex7-enable-A-050426-workaround-for-silicon-o.patch @@ -0,0 +1,35 @@ +From e42d8bf470388b16c4addb47b17669a6967bebe2 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sun, 20 Oct 2024 15:39:21 +0200 +Subject: [PATCH] lx2160acex7: enable A-050426 workaround for silicon one + +A-050426 affects both Silicon revisions 1 and 2, enable for 1 as well. + +Note this significantly increases size of PBI and currently leads to +issues with autoboot support. Plain sdhc or xspi builds continue to +work. + +Signed-off-by: Josua Mayer +--- + lx2160acex7/include/common_pbi.rcwi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/lx2160acex7/include/common_pbi.rcwi b/lx2160acex7/include/common_pbi.rcwi +index 7dd4be7..bb0f8bc 100644 +--- a/lx2160acex7/include/common_pbi.rcwi ++++ b/lx2160acex7/include/common_pbi.rcwi +@@ -33,10 +33,10 @@ write 0x2320000,0x20000000 + + /*SerDes Errata A-050479*/ + #include <../lx2160asi/a050479.rcw> ++#endif + + /* Errata A-050426 */ + #include <../lx2160asi/a050426.rcw> +-#endif + + /* + * FlexSPI controller supports modifcation of the FlexSPI Clock +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0012-lx2160acex6-enable-pci-errata-workarounds-for-all-ac.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0012-lx2160acex6-enable-pci-errata-workarounds-for-all-ac.patch new file mode 100644 index 000000000000..157747f84391 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0012-lx2160acex6-enable-pci-errata-workarounds-for-all-ac.patch @@ -0,0 +1,87 @@ +From 30773f1070b4a315bcaa041e85ee2bdf8e04bf5b Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sun, 20 Oct 2024 15:45:00 +0200 +Subject: [PATCH 12/13] lx2160acex6: enable pci errata workarounds for all + active ports + +SolidRun internal cex6 evaluation baord uses PEX2, PEX3, PEX4 and PEX5. +Include workarounds for A-008851 and A-009531 for all available ports. + +Signed-off-by: Josua Mayer +--- + .../evb/rcw_2000_700_2900_3_3_2_auto.rcw | 2 +- + lx2160acex6_rev2/include/common_pbi.rcwi | 52 +++++++++++++++++++ + 2 files changed, 53 insertions(+), 1 deletion(-) + create mode 100644 lx2160acex6_rev2/include/common_pbi.rcwi + +diff --git a/lx2160acex6_rev2/evb/rcw_2000_700_2900_3_3_2_auto.rcw b/lx2160acex6_rev2/evb/rcw_2000_700_2900_3_3_2_auto.rcw +index 8d14387..6ae1090 100644 +--- a/lx2160acex6_rev2/evb/rcw_2000_700_2900_3_3_2_auto.rcw ++++ b/lx2160acex6_rev2/evb/rcw_2000_700_2900_3_3_2_auto.rcw +@@ -19,4 +19,4 @@ + #include <../lx2160acex7/include/SD1_3.rcwi> + #include <../lx2160acex7/include/SD2_3.rcwi> + #include <../lx2160acex7/include/SD3_2.rcwi> +-#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex6_rev2/include/common_pbi.rcwi> +diff --git a/lx2160acex6_rev2/include/common_pbi.rcwi b/lx2160acex6_rev2/include/common_pbi.rcwi +new file mode 100644 +index 0000000..aaadeb2 +--- /dev/null ++++ b/lx2160acex6_rev2/include/common_pbi.rcwi +@@ -0,0 +1,52 @@ ++/* ++ * LX2160A COM-Express Type 6 Common Configuration ++ */ ++ ++/* Drive the fan full speed pin */ ++.pbi ++write 0x2320000,0x20000000 ++.end ++ ++/* Errata to write on scratch reg for validation */ ++#include <../lx2160asi/scratchrw1.rcw> ++ ++/* Errata for SATA controller */ ++#include <../lx2160asi/a010554.rcw> ++ ++#if LX_SR == 1 ++/* Errata for PCIe controller */ ++#include <../lx2160asi/a011270.rcw> ++#include <../lx2160asi/a050234.rcw> ++#endif ++ ++/* common PBI commands */ ++#include <../lx2160asi/common.rcw> ++ ++#if LX_SR == 2 ++/*PCIe Errata A-009531*/ ++#include <../lx2160asi/a009531_PEX2.rcw> ++#include <../lx2160asi/a009531_PEX3.rcw> ++#include <../lx2160asi/a009531_PEX4.rcw> ++#include <../lx2160asi/a009531_PEX5.rcw> ++ ++/*PCIe Errata A-008851*/ ++#include <../lx2160asi/a008851_PEX2.rcw> ++#include <../lx2160asi/a008851_PEX3.rcw> ++#include <../lx2160asi/a008851_PEX4.rcw> ++#include <../lx2160asi/a008851_PEX5.rcw> ++ ++/*SerDes Errata A-050479*/ ++#include <../lx2160asi/a050479.rcw> ++#endif ++ ++/* Errata A-050426 */ ++#include <../lx2160asi/a050426.rcw> ++ ++/* Set Boot Location Pointer (Fall-back when unset is BOOT_LOC) */ ++#if defined(LX_BOOTSOURCE_SDHC) ++#include <../lx2160asi/bootlocptr_sd.rcw> ++#elif defined(LX_BOOTSOURCE_XSPI) ++#include <../lx2160asi/bootlocptr_nor.rcw> ++#else ++#include <../lx2160asi/bootlocptr_auto.rcw> ++#endif +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0013-lx2160acex6-add-configuration-for-2.2GHz-binned-soc.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0013-lx2160acex6-add-configuration-for-2.2GHz-binned-soc.patch new file mode 100644 index 000000000000..e8ab196a20bd --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0013-lx2160acex6-add-configuration-for-2.2GHz-binned-soc.patch @@ -0,0 +1,42 @@ +From 4cd3955a69be423a48eefccc27442c148ece8ffd Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sun, 20 Oct 2024 15:51:12 +0200 +Subject: [PATCH 13/13] lx2160acex6: add configuration for 2.2GHz binned soc + +Signed-off-by: Josua Mayer +--- + .../evb/rcw_2200_750_3200_3_3_2_auto.rcw | 22 +++++++++++++++++++ + 1 file changed, 22 insertions(+) + create mode 100644 lx2160acex6_rev2/evb/rcw_2200_750_3200_3_3_2_auto.rcw + +diff --git a/lx2160acex6_rev2/evb/rcw_2200_750_3200_3_3_2_auto.rcw b/lx2160acex6_rev2/evb/rcw_2200_750_3200_3_3_2_auto.rcw +new file mode 100644 +index 0000000..a66d4ec +--- /dev/null ++++ b/lx2160acex6_rev2/evb/rcw_2200_750_3200_3_3_2_auto.rcw +@@ -0,0 +1,22 @@ ++/* ++ * SerDes Protocol 1 - 3 ++ * SerDes Protocol 2 - 3 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex6_rev2/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_3.rcwi> ++#include <../lx2160acex7/include/SD2_3.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex6_rev2/include/common_pbi.rcwi> +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0014-lx2162aqds-re-enable-dpmac11.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0014-lx2162aqds-re-enable-dpmac11.patch new file mode 100644 index 000000000000..a7d81aeb668c --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0014-lx2162aqds-re-enable-dpmac11.patch @@ -0,0 +1,27 @@ +From 40ea49cde613dad5f63d157f40180ebe4f07f7f9 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sat, 27 May 2023 17:20:22 +0300 +Subject: [PATCH 14/15] lx2162aqds: re-enable dpmac11 + +dpmac11 was unintentionally disabled along with dpmac7-10. +Fix the initializer value of DEVDISR2 to only disable dpmac7-10. + +Signed-off-by: Josua Mayer +--- + lx2162aqds/disable_mac7_10.rcw | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/lx2162aqds/disable_mac7_10.rcw b/lx2162aqds/disable_mac7_10.rcw +index ef3edba..d52589c 100644 +--- a/lx2162aqds/disable_mac7_10.rcw ++++ b/lx2162aqds/disable_mac7_10.rcw +@@ -11,5 +11,5 @@ + */ + + .pbi +-write 0x1e00074,0x00007c0 ++write 0x1e00074,0x00003c0 + .end +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0015-add-configuration-for-lx2162a-som-and-clearfog-evalu.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0015-add-configuration-for-lx2162a-som-and-clearfog-evalu.patch new file mode 100644 index 000000000000..83c6caea771a --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0015-add-configuration-for-lx2162a-som-and-clearfog-evalu.patch @@ -0,0 +1,532 @@ +From 8aa66ef6694c03231f6432f0d62e40dffa88d3e4 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sun, 27 Oct 2024 18:26:26 +0100 +Subject: [PATCH] add configuration for lx2162a som and clearfog evaluation + board + +Signed-off-by: Josua Mayer +--- + lx2160acex7/include/SD1_0.rcwi | 17 +++ + lx2160acex7/include/SD2_0.rcwi | 17 +++ + lx2160acex7/include/SD3_0.rcwi | 20 +++ + lx2160acex7/include/pll_2000_650_xxxx.rcwi | 15 ++ + lx2162asom_rev2/Makefile | 1 + + lx2162asom_rev2/README | 0 + .../rcw_2000_650_2900_18_11_0_auto.rcw | 22 +++ + .../rcw_2000_650_2900_18_7_0_auto.rcw | 22 +++ + .../rcw_2000_650_2900_18_9_0_auto.rcw | 19 +++ + lx2162asom_rev2/include/SD1_18.rcwi | 18 +++ + lx2162asom_rev2/include/SD2_11.rcwi | 25 ++++ + lx2162asom_rev2/include/SD2_7.rcwi | 25 ++++ + lx2162asom_rev2/include/SD2_9.rcwi | 22 +++ + lx2162asom_rev2/include/common.rcwi | 128 ++++++++++++++++++ + lx2162asom_rev2/include/common_pbi.rcwi | 51 +++++++ + 15 files changed, 402 insertions(+) + create mode 100644 lx2160acex7/include/SD1_0.rcwi + create mode 100644 lx2160acex7/include/SD2_0.rcwi + create mode 100644 lx2160acex7/include/SD3_0.rcwi + create mode 100644 lx2160acex7/include/pll_2000_650_xxxx.rcwi + create mode 100644 lx2162asom_rev2/Makefile + create mode 100644 lx2162asom_rev2/README + create mode 100644 lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_11_0_auto.rcw + create mode 100644 lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_7_0_auto.rcw + create mode 100644 lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_9_0_auto.rcw + create mode 100644 lx2162asom_rev2/include/SD1_18.rcwi + create mode 100644 lx2162asom_rev2/include/SD2_11.rcwi + create mode 100644 lx2162asom_rev2/include/SD2_7.rcwi + create mode 100644 lx2162asom_rev2/include/SD2_9.rcwi + create mode 100644 lx2162asom_rev2/include/common.rcwi + create mode 100644 lx2162asom_rev2/include/common_pbi.rcwi + +diff --git a/lx2160acex7/include/SD1_0.rcwi b/lx2160acex7/include/SD1_0.rcwi +new file mode 100644 +index 0000000..718a441 +--- /dev/null ++++ b/lx2160acex7/include/SD1_0.rcwi +@@ -0,0 +1,17 @@ ++/* Serdes 1 Protocol 0: Disabled */ ++SRDS_PRTCL_S1=0 ++ ++/* Disable Serdes 1 PLLF */ ++SRDS_PLL_PD_PLL1=1 ++ ++/* Disable Serdes 1 PLLF reference clock */ ++SRDS_REFCLKF_DIS_S2=1 ++ ++/* Don't use Serdes 1 PLLF as reference for PLLS */ ++SRDS_INTRA_REF_CLK_S1=0 ++ ++/* Disable Serdes 1 PLLS */ ++SRDS_PLL_PD_PLL2=1 ++ ++/* Select Serdes 1 PLL Default Fequencies (don't care) */ ++SRDS_PLL_REF_CLK_SEL_S1=0 +diff --git a/lx2160acex7/include/SD2_0.rcwi b/lx2160acex7/include/SD2_0.rcwi +new file mode 100644 +index 0000000..6af65a3 +--- /dev/null ++++ b/lx2160acex7/include/SD2_0.rcwi +@@ -0,0 +1,17 @@ ++/* Serdes 2 Protocol 0: Disabled */ ++SRDS_PRTCL_S2=0 ++ ++/* Disable Serdes 2 PLLF */ ++SRDS_PLL_PD_PLL3=1 ++ ++/* Disable Serdes 2 PLLF reference clock */ ++SRDS_REFCLKF_DIS_S2=1 ++ ++/* Don't use Serdes 2 PLLF as reference for PLLS */ ++SRDS_INTRA_REF_CLK_S2=0 ++ ++/* Disable Serdes 2 PLLS */ ++SRDS_PLL_PD_PLL4=1 ++ ++/* Select Serdes 2 PLL Default Fequencies (don't care) */ ++SRDS_PLL_REF_CLK_SEL_S2=0 +diff --git a/lx2160acex7/include/SD3_0.rcwi b/lx2160acex7/include/SD3_0.rcwi +new file mode 100644 +index 0000000..250437c +--- /dev/null ++++ b/lx2160acex7/include/SD3_0.rcwi +@@ -0,0 +1,20 @@ ++/* Serdes 3 Protocol 0: Disabled */ ++SRDS_PRTCL_S3=0 ++ ++/* Disable Serdes 3 PLLF */ ++SRDS_PLL_PD_PLL5=1 ++ ++/* Disable Serdes 3 PLLF reference clock */ ++SRDS_REFCLKF_DIS_S3=1 ++ ++/* Don't use Serdes 3 PLLF as reference for PLLS */ ++SRDS_INTRA_REF_CLK_S3=0 ++ ++/* Disable Serdes 3 PLLS */ ++SRDS_PLL_PD_PLL6=1 ++ ++/* ++ * Select Serdes 3 PLL Default Fequencies (don't care) ++ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 936-937) ++ */ ++SRDS_PLL_REF_CLK_SEL_S3=0 +diff --git a/lx2160acex7/include/pll_2000_650_xxxx.rcwi b/lx2160acex7/include/pll_2000_650_xxxx.rcwi +new file mode 100644 +index 0000000..0bc7e8b +--- /dev/null ++++ b/lx2160acex7/include/pll_2000_650_xxxx.rcwi +@@ -0,0 +1,15 @@ ++/* ++ * Core and Platform Clocks: ++ * - Platform: 650MHz ++ * - Core: 2000MHz ++ */ ++ ++/* platform clock is system clock mul 13 div 2 = 650 */ ++SYS_PLL_RAT=13 ++ ++/* core clocks are 2000 */ ++CGA_PLL1_RAT=20 ++CGA_PLL2_RAT=20 ++CGB_PLL1_RAT=20 ++/* same as all nxp 2000_650_* */ ++CGB_PLL2_RAT=8 +diff --git a/lx2162asom_rev2/Makefile b/lx2162asom_rev2/Makefile +new file mode 100644 +index 0000000..f77e46b +--- /dev/null ++++ b/lx2162asom_rev2/Makefile +@@ -0,0 +1 @@ ++include ../Makefile.inc +diff --git a/lx2162asom_rev2/README b/lx2162asom_rev2/README +new file mode 100644 +index 0000000..e69de29 +diff --git a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_11_0_auto.rcw b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_11_0_auto.rcw +new file mode 100644 +index 0000000..cc1b0e5 +--- /dev/null ++++ b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_11_0_auto.rcw +@@ -0,0 +1,22 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 11 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 650 MHz ++ * DDR -- 2900 MT/s ++ * ++ */ ++ ++#define HAVE_PEX3 ++#define HAVE_PEX4 ++ ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_650_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2162asom_rev2/include/common.rcwi> ++#include <../lx2162asom_rev2/include/SD1_18.rcwi> ++#include <../lx2162asom_rev2/include/SD2_11.rcwi> ++#include <../lx2160acex7/include/SD3_0.rcwi> ++#include <../lx2162asom_rev2/include/common_pbi.rcwi> +diff --git a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_7_0_auto.rcw b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_7_0_auto.rcw +new file mode 100644 +index 0000000..475abbb +--- /dev/null ++++ b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_7_0_auto.rcw +@@ -0,0 +1,22 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 7 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 650 MHz ++ * DDR -- 2900 MT/s ++ * ++ */ ++ ++#define HAVE_PEX3 ++#define HAVE_PEX4 ++ ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_650_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2162asom_rev2/include/common.rcwi> ++#include <../lx2162asom_rev2/include/SD1_18.rcwi> ++#include <../lx2162asom_rev2/include/SD2_7.rcwi> ++#include <../lx2160acex7/include/SD3_0.rcwi> ++#include <../lx2162asom_rev2/include/common_pbi.rcwi> +diff --git a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_9_0_auto.rcw b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_9_0_auto.rcw +new file mode 100644 +index 0000000..4425597 +--- /dev/null ++++ b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_9_0_auto.rcw +@@ -0,0 +1,19 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 9 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 650 MHz ++ * DDR -- 2900 MT/s ++ * ++ */ ++ ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_650_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2162asom_rev2/include/common.rcwi> ++#include <../lx2162asom_rev2/include/SD1_18.rcwi> ++#include <../lx2162asom_rev2/include/SD2_9.rcwi> ++#include <../lx2160acex7/include/SD3_0.rcwi> ++#include <../lx2162asom_rev2/include/common_pbi.rcwi> +diff --git a/lx2162asom_rev2/include/SD1_18.rcwi b/lx2162asom_rev2/include/SD1_18.rcwi +new file mode 100644 +index 0000000..34c5be3 +--- /dev/null ++++ b/lx2162asom_rev2/include/SD1_18.rcwi +@@ -0,0 +1,18 @@ ++/* Serdes 1 Protocol 18: 2x10Gbps + 2x25Gbps */ ++SRDS_PRTCL_S1=18 ++ ++/* Enable Serdes 1 PLLF */ ++SRDS_PLL_PD_PLL1=0 ++ ++/* Enable Serdes 1 PLLS */ ++SRDS_PLL_PD_PLL2=0 ++ ++/* Use Serdes 1 PLLF for PLLS (LX2162A has no physical input for PLLS) */ ++SRDS_INTRA_REF_CLK_S1=1 ++ ++/* ++ * Select Serdes 1 PLLF frequency 161.1328125MHz for 25GE mode (lanes 2+3): Bit 0 = 0 ++ * Select Serdes 1 PLLS frequency 161.1328125MHz for 10GE mode (not documented in RM): Bit 1 = 1 ++ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932) ++ */ ++SRDS_PLL_REF_CLK_SEL_S1=2 +diff --git a/lx2162asom_rev2/include/SD2_11.rcwi b/lx2162asom_rev2/include/SD2_11.rcwi +new file mode 100644 +index 0000000..9434b7b +--- /dev/null ++++ b/lx2162asom_rev2/include/SD2_11.rcwi +@@ -0,0 +1,25 @@ ++/* Serdes 2 Protocol 11: 6x1Gbps & 2x PCI-e x1 Gen 3 */ ++SRDS_PRTCL_S2=11 ++ ++/* Enable Serdes 2 PLLF */ ++SRDS_PLL_PD_PLL3=0 ++ ++/* Enable Serdes 2 PLLS */ ++SRDS_PLL_PD_PLL4=0 ++ ++/* Use Serdes 2 PLLF for PLLS (to share PLLF 100MHz reference clock) */ ++SRDS_INTRA_REF_CLK_S2=1 ++ ++/* ++ * Select Serdes 2 PLLF frequency 100MHz for PCI: Bit 0 = 0 ++ * Select Serdes 2 PLLS frequency 100MHz for 1G mode: Bit 1 = 0 ++ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 934-935) ++ */ ++SRDS_PLL_REF_CLK_SEL_S2=0 ++ ++/* Support up to PCI-e Gen 3 */ ++SRDS_DIV_PEX_S2=1 ++ ++/* Configure Ethernet Controllers 1+2 Pins as GPIOs to avoid competing for WRIO MACs 17+18 */ ++EC1_PMUX=1 ++EC2_PMUX=1 +diff --git a/lx2162asom_rev2/include/SD2_7.rcwi b/lx2162asom_rev2/include/SD2_7.rcwi +new file mode 100644 +index 0000000..eb25a86 +--- /dev/null ++++ b/lx2162asom_rev2/include/SD2_7.rcwi +@@ -0,0 +1,25 @@ ++/* Serdes 2 Protocol 7: 2x10Gbps 4x1Gbps & 2x PCI-e x1 Gen 2 */ ++SRDS_PRTCL_S2=7 ++ ++/* Enable Serdes 2 PLLF */ ++SRDS_PLL_PD_PLL3=0 ++ ++/* Enable Serdes 2 PLLS */ ++SRDS_PLL_PD_PLL4=0 ++ ++/* Don't use Serdes 2 PLLF for PLLS */ ++SRDS_INTRA_REF_CLK_S2=0 ++ ++/* ++ * Select Serdes 2 PLLF frequency 100MHz for 1G (and pcie): Bit 0 = 0 ++ * Select Serdes 2 PLLS frequency 156.25MHz for 10G mode: Bit 1 = 0 ++ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 934-935) ++ */ ++SRDS_PLL_REF_CLK_SEL_S2=0 ++ ++/* Support up to PCI-e Gen 2 */ ++SRDS_DIV_PEX_S2=2 ++ ++/* Configure Ethernet Controllers 1+2 Pins as GPIOs to avoid competing for WRIO MACs 17+18 */ ++EC1_PMUX=1 ++EC2_PMUX=1 +diff --git a/lx2162asom_rev2/include/SD2_9.rcwi b/lx2162asom_rev2/include/SD2_9.rcwi +new file mode 100644 +index 0000000..68728ba +--- /dev/null ++++ b/lx2162asom_rev2/include/SD2_9.rcwi +@@ -0,0 +1,22 @@ ++/* Serdes 2 Protocol 9: 8x1Gbps */ ++SRDS_PRTCL_S2=9 ++ ++/* Disable Serdes 2 PLLF */ ++SRDS_PLL_PD_PLL3=1 ++ ++/* Enable Serdes 2 PLLS */ ++SRDS_PLL_PD_PLL4=0 ++ ++/* Use Serdes 2 PLLF for PLLS (to share PLLF 100MHz reference clock) */ ++SRDS_INTRA_REF_CLK_S2=1 ++ ++/* ++ * Select Serdes 2 PLLF frequency 100MHz (don't care): Bit 0 = 0 ++ * Select Serdes 2 PLLS frequency 100MHz for 1G mode: Bit 1 = 0 ++ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 934-935) ++ */ ++SRDS_PLL_REF_CLK_SEL_S2=0 ++ ++/* Configure Ethernet Controllers 1+2 Pins as GPIOs to avoid competing for WRIO MACs 17+18 */ ++EC1_PMUX=1 ++EC2_PMUX=1 +diff --git a/lx2162asom_rev2/include/common.rcwi b/lx2162asom_rev2/include/common.rcwi +new file mode 100644 +index 0000000..35a6db6 +--- /dev/null ++++ b/lx2162asom_rev2/include/common.rcwi +@@ -0,0 +1,128 @@ ++/* ++ * LX2162A SoM Common Configuration ++ */ ++ ++/* C[5:8]_PLL are CG[5:8] div 1 */ ++C5_PLL_SEL=0 ++C6_PLL_SEL=0 ++C7_PLL_SEL=0 ++C8_PLL_SEL=0 ++/* Cluster group A clock is PLL1 div 1 (unused on LX2160A) */ ++HWA_CGA_M1_CLK_SEL=1 ++/* Cluster group B clock is PLL2 div 2 (for DCE) */ ++HWA_CGB_M1_CLK_SEL=6 ++/* ++ * fall-back boot-mode when DCFG boot location pointer registers are null ++ * - 0b10101 (21): OCRAM ++ * - 0b11010 (26): XSPI ++ */ ++BOOT_LOC=21 ++/* SYSCLK is 100MHz */ ++SYSCLK_FREQ=600 ++/* USB-3.0 clock is 100MHz */ ++USB3_CLK_FSEL=39 ++ ++/* IIC1 is I2C */ ++IIC1_PMUX=0 ++/* IIC2 is SD Card-Detect */ ++IIC2_PMUX=6 ++/* IIC3 is I2C */ ++IIC3_PMUX=0 ++/* IIC4 is I2C (unused) */ ++IIC4_PMUX=0 ++/* IIC5 is I2C */ ++IIC5_PMUX=0 ++/* IIC6 is I2C (unused) */ ++IIC6_PMUX=0 ++/* ++ * SDHC1 CMD/CLK/VBUS/DAT[0:3] are SDHC ++ * SPI3_PCS0 is VSEL ++ */ ++SDHC1_BASE_PMUX=0 ++/* SDHC1_DS is GPIO (unused) */ ++SDHC1_DS_PMUX=1 ++/* SDHC1_CMD/DAT0/DAT1_DIR (SPI3_PCS[1:3]) are GPIO1[14:12] */ ++SDHC1_DIR_PMUX=1 ++/* USB[1:2]_DRVVBUS/PWRFAULT are GPIO4[28:25] (unused) */ ++USB_EXT_PMUX=1 ++/* XSPI1_A_DQS/SCK/CS0_B/CS1_B are SPI */ ++XSPI1_A_BASE_PMUX=0 ++/* XSPI1_A_DATA[3:0] are SPI */ ++XSPI1_A_DATA30_PMUX=0 ++/* XSPI1_A_DATA[7:4] are SPI */ ++XSPI1_A_DATA74_PMUX=0 ++/* ASLEEP is ASLEEP (unused) */ ++ASLEEP_PMUX=0 ++/* EVT[2:0] are GPIO3[14:12] */ ++EVT20_PMUX=1 ++/* EVT[4:3] are GPIO3[16:15] */ ++EVT43_PMUX=1 ++/* CLK_OUT is GPIO (unused) */ ++CLK_OUT_PMUX=1 ++/* IRQ[3:0] are GPIO3[3:0] */ ++IRQ03_00_PMUX=1 ++/* IRQ[7:4] are GPIO3[7:4] */ ++IRQ07_04_PMUX=1 ++/* IRQ[11:8] are GPIO3[11:8] */ ++IRQ11_08_PMUX=1 ++/* EC1_* are RGMII */ ++EC1_PMUX=0 ++/* EC2_* are PTP */ ++EC2_PMUX=2 ++/* EC_GTX_CLK125 is PTP */ ++GTX_CLK_PMUX=0 ++/* UART1_SOUT/SIN are UART1 */ ++UART1_SOUTSIN_PMUX=0 ++/* UART1_RTS/CTS_B are GPIO (unused) */ ++UART1_RTSCTS_PMUX=1 ++/* UART2_SOUT/SIN are UART2 */ ++UART2_SOUTSIN_PMUX=0 ++/* UART2_RTS/CTS_B are GPIO (unused) */ ++UART2_RTSCTS_PMUX=1 ++/* SDHC2_CMD/DAT[3:0]/DS/CLK are SDHC */ ++SDHC2_BASE_PMUX=0 ++/* SDHC2_DAT[7:4] are SDHC */ ++SDHC2_DAT74_PMUX=0 ++ ++ ++/* configure IIC1, IIC3, IIC5, IIC6 pins for i2c */ ++IIC1_PMUX=0 ++IIC3_PMUX=0 ++IIC5_PMUX=0 ++IIC6_PMUX=0 ++ ++/* ++ * Configure GPIOs: ++ * EVT0_B: GPIO3_DAT12 ++ * EVT1_B: GPIO3_DAT13 (SFP 25 upper LED) ++ * EVT2_B: GPIO3_DAT14 (SFP 25 lower LED) ++ * EVT3_B: GPIO3_DAT15 (SFP 25 lower MODABS) ++ * EVT4_B: GPIO3_DAT16 (SFP 10 upper MODABS) ++ * PROC_IRQ0: GPIO3_DAT00 ++ * PROC_IRQ1: GPIO3_DAT01 (SFP 10 lower MODABS) ++ * PROC_IRQ2: GPIO3_DAT02 ++ * PROC_IRQ3: GPIO3_DAT03 ++ * PROC_IRQ4: GPIO3_DAT04 ++ * PROC_IRQ5: GPIO3_DAT05 (SFP 10 upper LED) ++ * PROC_IRQ6: GPIO3_DAT06 ++ * PROC_IRQ7: GPIO3_DAT07 ++ * PROC_IRQ8: GPIO3_DAT08 ++ * PROC_IRQ9: GPIO3_DAT09 ++ * PROC_IRQ10: GPIO3_DAT10 (SFP 25 upper MODABS) ++ * PROC_IRQ11: GPIO3_DAT11 (SFP 10 lower LED) ++ */ ++EVT20_PMUX=1 ++EVT43_PMUX=1 ++IRQ03_00_PMUX=1 ++IRQ07_04_PMUX=1 ++IRQ11_08_PMUX=1 ++ ++/* Configure USB1 Pins for USB */ ++USB_EXT_PMUX=0 ++ ++ ++/* ++ * Original SolidRun Settings in LSDK-21.08 ++ * ++ * HWA_CGB_M1_CLK_SEL=7 // Cluster Group B PLL 2 / 3 is clock ++ */ +diff --git a/lx2162asom_rev2/include/common_pbi.rcwi b/lx2162asom_rev2/include/common_pbi.rcwi +new file mode 100644 +index 0000000..05f19fc +--- /dev/null ++++ b/lx2162asom_rev2/include/common_pbi.rcwi +@@ -0,0 +1,51 @@ ++/* ++ * LX2162A SoM Common Configuration ++ */ ++ ++/* Errata to write on scratch reg for validation */ ++#include <../lx2160asi/scratchrw1.rcw> ++ ++/* common PBI commands */ ++#include <../lx2160asi/common.rcw> ++ ++/* PCIe Errata A-009531, A-008851 */ ++#ifdef HAVE_PEX1 ++#include <../lx2160asi/a009531_PEX1.rcw> ++#include <../lx2160asi/a008851_PEX1.rcw> ++#endif ++#ifdef HAVE_PEX3 ++#include <../lx2160asi/a009531_PEX3.rcw> ++#include <../lx2160asi/a008851_PEX3.rcw> ++#endif ++#ifdef HAVE_PEX4 ++#include <../lx2160asi/a009531_PEX4.rcw> ++#include <../lx2160asi/a008851_PEX4.rcw> ++#endif ++ ++/* SerDes Errata A-050479 */ ++#include <../lx2160asi/a050479.rcw> ++ ++/* PEX2/5/6 clock disable (not available on LX2162) */ ++#include <../lx2162aqds/disable_pci2_5_6.rcw> ++ ++/* USB2 clock disable (not available on LX2162) */ ++#include <../lx2162aqds/disable_usb2.rcw> ++ ++/* MAC7 to MAC10 clock disable (not available on LX2162) */ ++#include <../lx2162aqds/disable_mac7_10.rcw> ++ ++/* DDR2 clock disable*/ ++#include <../lx2162aqds/disable_ddr2.rcw> ++ ++/* Errata A-050426 */ ++#include <../lx2160asi/a050426.rcw> ++ ++/* Set Boot Location Pointer (Fall-back when unset is BOOT_LOC) */ ++#if defined(LX_BOOTSOURCE_SDHC) ++#include <../lx2160asi/bootlocptr_sd.rcw> ++#elif defined(LX_BOOTSOURCE_XSPI) ++#include <../lx2160asi/bootlocptr_nor.rcw> ++#else ++#include <../lx2160asi/bootlocptr_auto.rcw> ++#endif ++ +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0016-lx2160acex7-clearfog-cx-add-configuration-for-serdes.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0016-lx2160acex7-clearfog-cx-add-configuration-for-serdes.patch new file mode 100644 index 000000000000..fb6688f50ac4 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0016-lx2160acex7-clearfog-cx-add-configuration-for-serdes.patch @@ -0,0 +1,2000 @@ +From c9c51751856fabca518d364ef344f5e1470f6669 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Thu, 31 Oct 2024 16:01:27 +0100 +Subject: [PATCH] lx2160acex7: clearfog-cx: add configuration for serdes 1 + protocol 18 + +Signed-off-by: Josua Mayer +--- + .../rcw_2000_700_2400_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_2400_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2400_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2600_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_2600_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2600_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2666_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_2666_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2666_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2900_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_2900_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2900_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_3200_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_3200_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_3200_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2400_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_2400_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2400_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2600_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_2600_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2600_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2666_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_2666_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2666_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2900_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_2900_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2900_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_3200_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_3200_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_3200_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + lx2160acex7/include/SD1_18.rcwi | 24 ++++++++++++++++++ + lx2160acex7/include/SD1_8.rcwi | 4 +-- + .../rcw_2000_700_2400_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_2400_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2400_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2600_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_2600_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2600_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2666_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_2666_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2666_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2900_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_2900_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2900_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_3200_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_3200_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_3200_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2400_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_2400_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2400_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2600_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_2600_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2600_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2666_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_2666_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2666_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2900_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_2900_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2900_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_3200_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_3200_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_3200_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + 62 files changed, 1486 insertions(+), 2 deletions(-) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw + create mode 100644 lx2160acex7/include/SD1_18.rcwi + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw + +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw +new file mode 100644 +index 0000000..9e95ac8 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..470237f +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..a13d207 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw +new file mode 100644 +index 0000000..ff8a674 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..8d73b20 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..c6595d2 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw +new file mode 100644 +index 0000000..3c2f588 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..4671e9a +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..91e4908 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw +new file mode 100644 +index 0000000..978d3a6 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..1d1a869 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..3f96225 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw +new file mode 100644 +index 0000000..732ca38 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..de60fca +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..1b44c27 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw +new file mode 100644 +index 0000000..f69abb1 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..09c62dc +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..f1c0c96 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw +new file mode 100644 +index 0000000..2b75335 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..7839ab2 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..901b323 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw +new file mode 100644 +index 0000000..951a9eb +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..4d6aec0 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..eb909ee +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw +new file mode 100644 +index 0000000..b430f80 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..c935b09 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..b1f39b4 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw +new file mode 100644 +index 0000000..d0736c2 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..6410353 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..daa99df +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/include/SD1_18.rcwi b/lx2160acex7/include/SD1_18.rcwi +new file mode 100644 +index 0000000..cf67395 +--- /dev/null ++++ b/lx2160acex7/include/SD1_18.rcwi +@@ -0,0 +1,24 @@ ++/* ++ * Serdes 1 Reference Clocks: ++ * - PLLF = 161.1328125MHz ++ * - PLLS = 100MHz ++ */ ++ ++/* Serdes 1 Protocol 18: 6x10Gbps + 2x25Gbps */ ++SRDS_PRTCL_S1=18 ++ ++/* Enable PLLF */ ++SRDS_PLL_PD_PLL1=0 ++ ++/* Use PLLF for PLLS */ ++SRDS_INTRA_REF_CLK_S1=1 ++ ++/* Enable PLLS */ ++SRDS_PLL_PD_PLL2=0 ++ ++/* ++ * Select PLLF frequency 161.1328125MH for 25G mode: Bit 0 = 0 ++ * Select PLLS frequency 161.1328125MHz for 10G mode: Bit 1 = 1 ++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933) ++ */ ++SRDS_PLL_REF_CLK_SEL_S1=2 +diff --git a/lx2160acex7/include/SD1_8.rcwi b/lx2160acex7/include/SD1_8.rcwi +index 87ce260..1646de8 100644 +--- a/lx2160acex7/include/SD1_8.rcwi ++++ b/lx2160acex7/include/SD1_8.rcwi +@@ -1,7 +1,7 @@ + /* + * Serdes 1 Reference Clocks: +- * - PLLF = 100MHz +- * - PLLS = 161.1328125MHz ++ * - PLLF = 161.1328125MHz ++ * - PLLS = 100MHz + */ + + /* Serdes 1 Protocol 8: 8x10Gbps */ +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw +new file mode 100644 +index 0000000..6f454ad +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..a3bc9c9 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..144f54b +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw +new file mode 100644 +index 0000000..2a11587 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..bb3437e +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..90eacf6 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw +new file mode 100644 +index 0000000..af17640 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..4dd1b96 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..d9c8671 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw +new file mode 100644 +index 0000000..2a23f78 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..cf44444 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..f93ef7f +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw +new file mode 100644 +index 0000000..0067b24 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..290ebb1 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..e9e5e99 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw +new file mode 100644 +index 0000000..02b2961 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..1fa9e1f +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..12f62c1 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw +new file mode 100644 +index 0000000..f951e53 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..227510c +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..4a30d7f +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw +new file mode 100644 +index 0000000..86b272d +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..03d233f +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..8321f14 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw +new file mode 100644 +index 0000000..4444769 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..fc1ad2d +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..311d2df +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw +new file mode 100644 +index 0000000..3665618 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..49b4d42 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..bdfe337 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0017-lx2160acex7-add-configuration-for-serdes-1-protocol-.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0017-lx2160acex7-add-configuration-for-serdes-1-protocol-.patch new file mode 100644 index 000000000000..238d1943f929 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0017-lx2160acex7-add-configuration-for-serdes-1-protocol-.patch @@ -0,0 +1,49 @@ +From cbb5b8743e3790dd9172a6b9146e60dfaec221ac Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Wed, 6 Nov 2024 11:18:12 +0100 +Subject: [PATCH] lx2160acex7: add configuration for serdes 1 protocol 4 + +This configuration can boot, but currently leads to issues on +clearfog-cx in linux. +Therefore no board configuration has been added beyond the include. + +Signed-off-by: Josua Mayer +--- + lx2160acex7/include/SD1_4.rcwi | 25 +++++++++++++++++++++++++ + 1 file changed, 25 insertions(+) + create mode 100644 lx2160acex7/include/SD1_4.rcwi + +diff --git a/lx2160acex7/include/SD1_4.rcwi b/lx2160acex7/include/SD1_4.rcwi +new file mode 100644 +index 0000000..3c6023a +--- /dev/null ++++ b/lx2160acex7/include/SD1_4.rcwi +@@ -0,0 +1,25 @@ ++/* ++ * Serdes 1 Reference Clocks: ++ * - PLLF = 161.1328125MHz ++ * - PLLS = 100MHz ++ */ ++ ++/* Serdes 1 Protocol 4: 8x1Gbps */ ++SRDS_PRTCL_S1=4 ++ ++/* Disable PLLF */ ++SRDS_PLL_PD_PLL1=1 ++SRDS_REFCLKF_DIS_S1=1 ++ ++/* Don't use PLLF for PLLS */ ++SRDS_INTRA_REF_CLK_S1=0 ++ ++/* Enable PLLS */ ++SRDS_PLL_PD_PLL2=0 ++ ++/* ++ * Select PLLF frequency 100MHz (don't care): Bit 0 = 0 ++ * Select PLLS frequency 100MHz: Bit 1 = 0 ++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933) ++ */ ++SRDS_PLL_REF_CLK_SEL_S1=0 +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0018-solidrun-add-script-generating-configs-from-template.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0018-solidrun-add-script-generating-configs-from-template.patch new file mode 100644 index 000000000000..f13293f32fbe --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0018-solidrun-add-script-generating-configs-from-template.patch @@ -0,0 +1,1476 @@ +From b189c0e2b7e4e73d293874ac2fea3176c1a1f652 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Thu, 7 Nov 2024 13:26:49 +0100 +Subject: [PATCH 18/19] solidrun: add script generating configs from template + +Signed-off-by: Josua Mayer +--- + GenerateSRConfigs.sh | 47 +++++++++++++++++++ + .../rcw_2000_700_2400_18_5_2_auto.rcw | 2 + + .../rcw_2000_700_2400_18_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_2400_8_5_2_auto.rcw | 2 + + .../rcw_2000_700_2400_8_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_2600_18_5_2_auto.rcw | 2 + + .../rcw_2000_700_2600_18_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_2600_8_5_2_auto.rcw | 2 + + .../rcw_2000_700_2600_8_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_2900_18_5_2_auto.rcw | 2 + + .../rcw_2000_700_2900_18_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_2900_8_5_2_auto.rcw | 2 + + .../rcw_2000_700_2900_8_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_3200_18_5_2_auto.rcw | 2 + + .../rcw_2000_700_3200_18_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_3200_8_5_2_auto.rcw | 2 + + .../rcw_2000_700_3200_8_5_2_sdhc.rcw | 2 +- + .../rcw_2200_750_2400_18_5_2_auto.rcw | 4 +- + .../rcw_2200_750_2400_18_5_2_sdhc.rcw | 4 +- + .../rcw_2200_750_2400_18_5_2_xspi.rcw | 2 +- + .../rcw_2200_750_2400_8_5_2_auto.rcw | 4 +- + .../rcw_2200_750_2400_8_5_2_sdhc.rcw | 4 +- + .../rcw_2200_750_2400_8_5_2_xspi.rcw | 2 +- + .../rcw_2200_750_2600_18_5_2_auto.rcw | 4 +- + .../rcw_2200_750_2600_18_5_2_sdhc.rcw | 4 +- + .../rcw_2200_750_2600_18_5_2_xspi.rcw | 2 +- + .../rcw_2200_750_2600_8_5_2_auto.rcw | 4 +- + .../rcw_2200_750_2600_8_5_2_sdhc.rcw | 4 +- + .../rcw_2200_750_2600_8_5_2_xspi.rcw | 2 +- + .../rcw_2200_750_2900_18_5_2_auto.rcw | 4 +- + .../rcw_2200_750_2900_18_5_2_sdhc.rcw | 4 +- + .../rcw_2200_750_2900_18_5_2_xspi.rcw | 2 +- + .../rcw_2200_750_2900_8_5_2_auto.rcw | 4 +- + .../rcw_2200_750_2900_8_5_2_sdhc.rcw | 4 +- + .../rcw_2200_750_2900_8_5_2_xspi.rcw | 2 +- + .../rcw_2200_750_3200_18_5_2_auto.rcw | 4 +- + .../rcw_2200_750_3200_18_5_2_sdhc.rcw | 4 +- + .../rcw_2200_750_3200_18_5_2_xspi.rcw | 2 +- + .../rcw_2200_750_3200_8_5_2_auto.rcw | 4 +- + .../rcw_2200_750_3200_8_5_2_sdhc.rcw | 4 +- + .../rcw_2200_750_3200_8_5_2_xspi.rcw | 2 +- + lx2160acex7_clearfog-cx.tmpl | 25 ++++++++++ + .../rcw_2000_700_2400_18_5_2_auto.rcw | 2 + + .../rcw_2000_700_2400_18_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_2400_8_5_2_auto.rcw | 2 + + .../rcw_2000_700_2400_8_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_2600_18_5_2_auto.rcw | 2 + + .../rcw_2000_700_2600_18_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_2600_8_5_2_auto.rcw | 2 + + .../rcw_2000_700_2600_8_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_2900_18_5_2_auto.rcw | 2 + + .../rcw_2000_700_2900_18_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_2900_8_5_2_auto.rcw | 2 + + .../rcw_2000_700_2900_8_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_3200_18_5_2_auto.rcw | 2 + + .../rcw_2000_700_3200_18_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_3200_8_5_2_auto.rcw | 2 + + .../rcw_2000_700_3200_8_5_2_sdhc.rcw | 2 +- + .../rcw_2200_750_2400_18_5_2_auto.rcw | 4 +- + .../rcw_2200_750_2400_18_5_2_sdhc.rcw | 4 +- + .../rcw_2200_750_2400_18_5_2_xspi.rcw | 2 +- + .../rcw_2200_750_2400_8_5_2_auto.rcw | 4 +- + .../rcw_2200_750_2400_8_5_2_sdhc.rcw | 4 +- + .../rcw_2200_750_2400_8_5_2_xspi.rcw | 2 +- + .../rcw_2200_750_2600_18_5_2_auto.rcw | 4 +- + .../rcw_2200_750_2600_18_5_2_sdhc.rcw | 4 +- + .../rcw_2200_750_2600_18_5_2_xspi.rcw | 2 +- + .../rcw_2200_750_2600_8_5_2_auto.rcw | 4 +- + .../rcw_2200_750_2600_8_5_2_sdhc.rcw | 4 +- + .../rcw_2200_750_2600_8_5_2_xspi.rcw | 2 +- + .../rcw_2200_750_2900_18_5_2_auto.rcw | 4 +- + .../rcw_2200_750_2900_18_5_2_sdhc.rcw | 4 +- + .../rcw_2200_750_2900_18_5_2_xspi.rcw | 2 +- + .../rcw_2200_750_2900_8_5_2_auto.rcw | 4 +- + .../rcw_2200_750_2900_8_5_2_sdhc.rcw | 4 +- + .../rcw_2200_750_2900_8_5_2_xspi.rcw | 2 +- + .../rcw_2200_750_3200_18_5_2_auto.rcw | 4 +- + .../rcw_2200_750_3200_18_5_2_sdhc.rcw | 4 +- + .../rcw_2200_750_3200_18_5_2_xspi.rcw | 2 +- + .../rcw_2200_750_3200_8_5_2_auto.rcw | 4 +- + .../rcw_2200_750_3200_8_5_2_sdhc.rcw | 4 +- + .../rcw_2200_750_3200_8_5_2_xspi.rcw | 2 +- + 82 files changed, 216 insertions(+), 80 deletions(-) + create mode 100755 GenerateSRConfigs.sh + create mode 100644 lx2160acex7_clearfog-cx.tmpl + +diff --git a/GenerateSRConfigs.sh b/GenerateSRConfigs.sh +new file mode 100755 +index 0000000..907e359 +--- /dev/null ++++ b/GenerateSRConfigs.sh +@@ -0,0 +1,47 @@ ++#!/bin/bash -e ++ ++generate() { ++ local template=${1} ++ local MODULE=${2} ++ local SOC_REVISION=${3} ++ local BOARD=${4} ++ local CPU_SPEED=${5} ++ local BUS_SPEED=${6} ++ local DDR_SPEED=${7} ++ local SD1=${8} ++ local SD2=${9} ++ local SD3=${10} ++ local BOOTSOURCE=${11} ++ ++ local SOC_REVISION_SUFFIX="_rev${SOC_REVISION}" ++ if [ "${SOC_REVISION_SUFFIX}" = "_rev1" ]; then ++ SOC_REVISION_SUFFIX= ++ fi ++ ++ local rcw="${MODULE,,}${SOC_REVISION_SUFFIX,,}/${BOARD,,}/rcw_${CPU_SPEED}_${BUS_SPEED}_${DDR_SPEED}_${SD1}_${SD2}_${SD3}_${BOOTSOURCE,,}.rcw" ++ cat "$template" | sed \ ++ -e "s;%module%;${MODULE,,};g" -e "s;%MODULE%;${MODULE^^};g" \ ++ -e "s;%SOC_REVISION%;${SOC_REVISION};g" \ ++ -e "s;%board%;${BOARD,,};g" -e "s;%BOARD%;${BOARD^^};g" \ ++ -e "s;%CPU_SPEED%;${CPU_SPEED};g" \ ++ -e "s;%BUS_SPEED%;${BUS_SPEED};g" \ ++ -e "s;%DDR_SPEED%;${DDR_SPEED};g" \ ++ -e "s;%bootsource%;${BOOTSOURCE,,};g" -e "s;%BOOTSOURCE%;${BOOTSOURCE^^};g" \ ++ -e "s;%SD1%;${SD1};g" -e "s;%SD1%;${SD1};g" \ ++ -e "s;%SD2%;${SD2};g" -e "s;%SD2%;${SD2};g" \ ++ -e "s;%SD3%;${SD3};g" -e "s;%SD3%;${SD3};g" \ ++ > "$rcw" ++ echo "Generated $rcw" ++} ++ ++# generate LX2160A CEX-7 Clearfog-CX ++for DDR_SPEED in 2400 2600 2900 3200; do ++ for SOC_REVISION in 1 2; do ++ for BOOTSOURCE in auto sdhc xspi; do ++ for SD1 in 8 18; do ++ generate lx2160acex7_clearfog-cx.tmpl lx2160acex7 ${SOC_REVISION} clearfog-cx 2000 700 ${DDR_SPEED} ${SD1} 5 2 ${BOOTSOURCE} ++ generate lx2160acex7_clearfog-cx.tmpl lx2160acex7 ${SOC_REVISION} clearfog-cx 2200 750 ${DDR_SPEED} ${SD1} 5 2 ${BOOTSOURCE} ++ done ++ done ++ done ++done +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw +index 9e95ac8..6941de1 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2400 MT/s + * + * Silicon 1.0 ++ * Boot from AUTO + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw +index 470237f..7d178e9 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw +@@ -9,7 +9,7 @@ + * DDR -- 2400 MT/s + * + * Silicon 1.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 1 +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw +index ba0f82c..438b671 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2400 MT/s + * + * Silicon 1.0 ++ * Boot from AUTO + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw +index 4d67915..73c6f2d 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw +@@ -9,7 +9,7 @@ + * DDR -- 2400 MT/s + * + * Silicon 1.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 1 +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw +index ff8a674..a57abb1 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2600 MT/s + * + * Silicon 1.0 ++ * Boot from AUTO + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw +index 8d73b20..44cf09e 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw +@@ -9,7 +9,7 @@ + * DDR -- 2600 MT/s + * + * Silicon 1.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 1 +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw +index b1723d3..9e17570 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2600 MT/s + * + * Silicon 1.0 ++ * Boot from AUTO + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw +index 0424418..3e5409f 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw +@@ -9,7 +9,7 @@ + * DDR -- 2600 MT/s + * + * Silicon 1.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 1 +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw +index 978d3a6..11d63a0 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2900 MT/s + * + * Silicon 1.0 ++ * Boot from AUTO + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw +index 1d1a869..9f5b541 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw +@@ -9,7 +9,7 @@ + * DDR -- 2900 MT/s + * + * Silicon 1.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 1 +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw +index fa59785..3ec47b4 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2900 MT/s + * + * Silicon 1.0 ++ * Boot from AUTO + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw +index be0d219..b17d672 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw +@@ -9,7 +9,7 @@ + * DDR -- 2900 MT/s + * + * Silicon 1.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 1 +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw +index 732ca38..cfd8219 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw +@@ -9,9 +9,11 @@ + * DDR -- 3200 MT/s + * + * Silicon 1.0 ++ * Boot from AUTO + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw +index de60fca..bfb3a71 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw +@@ -9,7 +9,7 @@ + * DDR -- 3200 MT/s + * + * Silicon 1.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 1 +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw +index 90ac8a4..ac7755c 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw +@@ -9,9 +9,11 @@ + * DDR -- 3200 MT/s + * + * Silicon 1.0 ++ * Boot from AUTO + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw +index e1f9092..565252a 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw +@@ -9,7 +9,7 @@ + * DDR -- 3200 MT/s + * + * Silicon 1.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 1 +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw +index f69abb1..49ef64f 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw +@@ -5,13 +5,15 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2400 MT/s + * + * Silicon 1.0 ++ * Boot from AUTO + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw +index 09c62dc..e701626 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw +@@ -5,11 +5,11 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2400 MT/s + * + * Silicon 1.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 1 +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw +index f1c0c96..37eee98 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw +@@ -5,7 +5,7 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2400 MT/s + * + * Silicon 1.0 +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw +index 533fba1..53be672 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw +@@ -5,13 +5,15 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2400 MT/s + * + * Silicon 1.0 ++ * Boot from AUTO + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw +index 845ab35..400b9a9 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw +@@ -5,11 +5,11 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2400 MT/s + * + * Silicon 1.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 1 +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw +index 765758e..6ee9c7a 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw +@@ -5,7 +5,7 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2400 MT/s + * + * Silicon 1.0 +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw +index 2b75335..166b558 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw +@@ -5,13 +5,15 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2600 MT/s + * + * Silicon 1.0 ++ * Boot from AUTO + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw +index 7839ab2..240f34f 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw +@@ -5,11 +5,11 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2600 MT/s + * + * Silicon 1.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 1 +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw +index 901b323..9f8ed4e 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw +@@ -5,7 +5,7 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2600 MT/s + * + * Silicon 1.0 +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw +index c09807c..221d71a 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw +@@ -5,13 +5,15 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2600 MT/s + * + * Silicon 1.0 ++ * Boot from AUTO + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw +index 7808b12..d3bb414 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw +@@ -5,11 +5,11 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2600 MT/s + * + * Silicon 1.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 1 +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw +index 33bef8b..beefc3a 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw +@@ -5,7 +5,7 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2600 MT/s + * + * Silicon 1.0 +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw +index b430f80..925fadb 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw +@@ -5,13 +5,15 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2900 MT/s + * + * Silicon 1.0 ++ * Boot from AUTO + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw +index c935b09..a370eab 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw +@@ -5,11 +5,11 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2900 MT/s + * + * Silicon 1.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 1 +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw +index b1f39b4..75851ac 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw +@@ -5,7 +5,7 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2900 MT/s + * + * Silicon 1.0 +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw +index 0f3d8a3..fa408fa 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw +@@ -5,13 +5,15 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2900 MT/s + * + * Silicon 1.0 ++ * Boot from AUTO + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw +index 68452e0..3cfcc61 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw +@@ -5,11 +5,11 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2900 MT/s + * + * Silicon 1.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 1 +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw +index 0069109..4f89b17 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw +@@ -5,7 +5,7 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2900 MT/s + * + * Silicon 1.0 +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw +index d0736c2..aff7dab 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw +@@ -5,13 +5,15 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 3200 MT/s + * + * Silicon 1.0 ++ * Boot from AUTO + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw +index 6410353..772ec32 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw +@@ -5,11 +5,11 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 3200 MT/s + * + * Silicon 1.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 1 +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw +index daa99df..5c25062 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw +@@ -5,7 +5,7 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 3200 MT/s + * + * Silicon 1.0 +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw +index aa2fb4b..7ec91ef 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw +@@ -5,13 +5,15 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 3200 MT/s + * + * Silicon 1.0 ++ * Boot from AUTO + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw +index 6f06730..1756c4e 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw +@@ -5,11 +5,11 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 3200 MT/s + * + * Silicon 1.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 1 +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw +index 94dcc9b..85b9f95 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw +@@ -5,7 +5,7 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 3200 MT/s + * + * Silicon 1.0 +diff --git a/lx2160acex7_clearfog-cx.tmpl b/lx2160acex7_clearfog-cx.tmpl +new file mode 100644 +index 0000000..29b6fd0 +--- /dev/null ++++ b/lx2160acex7_clearfog-cx.tmpl +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - %SD1% ++ * SerDes Protocol 2 - %SD2% ++ * SerDes Protocol 3 - %SD3% ++ * ++ * Frequencies: ++ * Core -- %CPU_SPEED% MHz ++ * Platform -- %BUS_SPEED% MHz ++ * DDR -- %DDR_SPEED% MT/s ++ * ++ * Silicon %SOC_REVISION%.0 ++ * Boot from %BOOTSOURCE% ++ */ ++ ++#define LX_SR %SOC_REVISION% ++#define LX_BOOTSOURCE_%BOOTSOURCE% ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../%module%/include/pll_%CPU_SPEED%_%BUS_SPEED%_xxxx.rcwi> ++#include <../%module%/include/pll_xxxx_xxx_%DDR_SPEED%.rcwi> ++#include <../%module%/include/common.rcwi> ++#include <../%module%/include/SD1_%SD1%.rcwi> ++#include <../%module%/include/SD2_%SD2%.rcwi> ++#include <../%module%/include/SD3_%SD3%.rcwi> ++#include <../%module%/include/common_pbi.rcwi> ++#include <../%module%/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw +index 6f454ad..af1b66d 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2400 MT/s + * + * Silicon 2.0 ++ * Boot from AUTO + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw +index a3bc9c9..e3d8d98 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw +@@ -9,7 +9,7 @@ + * DDR -- 2400 MT/s + * + * Silicon 2.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 2 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw +index 1c23c5c..5359341 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2400 MT/s + * + * Silicon 2.0 ++ * Boot from AUTO + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw +index c7b307e..ef3e91f 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw +@@ -9,7 +9,7 @@ + * DDR -- 2400 MT/s + * + * Silicon 2.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 2 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw +index 2a11587..c24f4c5 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2600 MT/s + * + * Silicon 2.0 ++ * Boot from AUTO + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw +index bb3437e..3adbbd6 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw +@@ -9,7 +9,7 @@ + * DDR -- 2600 MT/s + * + * Silicon 2.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 2 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw +index 87391ab..eca9cd1 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2600 MT/s + * + * Silicon 2.0 ++ * Boot from AUTO + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw +index a4c254c..ad3cd52 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw +@@ -9,7 +9,7 @@ + * DDR -- 2600 MT/s + * + * Silicon 2.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 2 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw +index 2a23f78..ce5744f 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2900 MT/s + * + * Silicon 2.0 ++ * Boot from AUTO + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw +index cf44444..74a55e0 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw +@@ -9,7 +9,7 @@ + * DDR -- 2900 MT/s + * + * Silicon 2.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 2 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw +index 9114f36..5bdbd19 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2900 MT/s + * + * Silicon 2.0 ++ * Boot from AUTO + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw +index 88ea5f2..532bd1f 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw +@@ -9,7 +9,7 @@ + * DDR -- 2900 MT/s + * + * Silicon 2.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 2 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw +index 0067b24..15a5bb5 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw +@@ -9,9 +9,11 @@ + * DDR -- 3200 MT/s + * + * Silicon 2.0 ++ * Boot from AUTO + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw +index 290ebb1..71929a9 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw +@@ -9,7 +9,7 @@ + * DDR -- 3200 MT/s + * + * Silicon 2.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 2 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw +index 7e97984..a6e38c8 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw +@@ -9,9 +9,11 @@ + * DDR -- 3200 MT/s + * + * Silicon 2.0 ++ * Boot from AUTO + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw +index 486ade8..c3c7459 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw +@@ -9,7 +9,7 @@ + * DDR -- 3200 MT/s + * + * Silicon 2.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 2 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw +index 02b2961..37b5ed7 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw +@@ -5,13 +5,15 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2400 MT/s + * + * Silicon 2.0 ++ * Boot from AUTO + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw +index 1fa9e1f..2c64922 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw +@@ -5,11 +5,11 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2400 MT/s + * + * Silicon 2.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 2 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw +index 12f62c1..5d42ffd 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw +@@ -5,7 +5,7 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2400 MT/s + * + * Silicon 2.0 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw +index 4185ea6..8143c6a 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw +@@ -5,13 +5,15 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2400 MT/s + * + * Silicon 2.0 ++ * Boot from AUTO + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw +index 93b10d2..d4f9354 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw +@@ -5,11 +5,11 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2400 MT/s + * + * Silicon 2.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 2 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw +index feb3e42..54faf81 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw +@@ -5,7 +5,7 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2400 MT/s + * + * Silicon 2.0 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw +index f951e53..78a799e 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw +@@ -5,13 +5,15 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2600 MT/s + * + * Silicon 2.0 ++ * Boot from AUTO + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw +index 227510c..bdcc867 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw +@@ -5,11 +5,11 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2600 MT/s + * + * Silicon 2.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 2 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw +index 4a30d7f..5e5dd08 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw +@@ -5,7 +5,7 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2600 MT/s + * + * Silicon 2.0 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw +index e04fcfb..a00da7d 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw +@@ -5,13 +5,15 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2600 MT/s + * + * Silicon 2.0 ++ * Boot from AUTO + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw +index 32225fe..b635b12 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw +@@ -5,11 +5,11 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2600 MT/s + * + * Silicon 2.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 2 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw +index 6fbba40..8c8e91c 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw +@@ -5,7 +5,7 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2600 MT/s + * + * Silicon 2.0 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw +index 4444769..9fd6241 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw +@@ -5,13 +5,15 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2900 MT/s + * + * Silicon 2.0 ++ * Boot from AUTO + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw +index fc1ad2d..fb5b219 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw +@@ -5,11 +5,11 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2900 MT/s + * + * Silicon 2.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 2 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw +index 311d2df..f0ef2bc 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw +@@ -5,7 +5,7 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2900 MT/s + * + * Silicon 2.0 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw +index b9797ca..02f9795 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw +@@ -5,13 +5,15 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2900 MT/s + * + * Silicon 2.0 ++ * Boot from AUTO + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw +index a7b5bd2..e779da8 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw +@@ -5,11 +5,11 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2900 MT/s + * + * Silicon 2.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 2 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw +index 273d91c..6903faf 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw +@@ -5,7 +5,7 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 2900 MT/s + * + * Silicon 2.0 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw +index 3665618..6ce054a 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw +@@ -5,13 +5,15 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 3200 MT/s + * + * Silicon 2.0 ++ * Boot from AUTO + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw +index 49b4d42..22afca8 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw +@@ -5,11 +5,11 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 3200 MT/s + * + * Silicon 2.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 2 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw +index bdfe337..d600c86 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw +@@ -5,7 +5,7 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 3200 MT/s + * + * Silicon 2.0 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw +index 046adc8..9c0d832 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw +@@ -5,13 +5,15 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 3200 MT/s + * + * Silicon 2.0 ++ * Boot from AUTO + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw +index 9798b74..f037a47 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw +@@ -5,11 +5,11 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 3200 MT/s + * + * Silicon 2.0 +- * Boot from SDHC1 ++ * Boot from SDHC + */ + + #define LX_SR 2 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw +index 6b875e7..44e93b1 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw +@@ -5,7 +5,7 @@ + * + * Frequencies: + * Core -- 2200 MHz +- * Platform -- 700 MHz ++ * Platform -- 750 MHz + * DDR -- 3200 MT/s + * + * Silicon 2.0 +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0019-lx2160acex7-clearfog-cx-add-configuration-for-serdes.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0019-lx2160acex7-clearfog-cx-add-configuration-for-serdes.patch new file mode 100644 index 000000000000..037c88f760d0 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0019-lx2160acex7-clearfog-cx-add-configuration-for-serdes.patch @@ -0,0 +1,1611 @@ +From b40f6920f1f572bf5cfce1f8a0be20a45ce6af9f Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Thu, 7 Nov 2024 13:39:05 +0100 +Subject: [PATCH 19/19] lx2160acex7: clearfog-cx: add configuration for serdes + 1 protocol 4 + +Signed-off-by: Josua Mayer +--- + GenerateSRConfigs.sh | 2 +- + .../rcw_2000_700_2400_4_5_2_auto.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2400_4_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2400_4_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2600_4_5_2_auto.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2600_4_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2600_4_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2900_4_5_2_auto.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2900_4_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2900_4_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_3200_4_5_2_auto.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_3200_4_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_3200_4_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2400_4_5_2_auto.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2400_4_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2400_4_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2600_4_5_2_auto.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2600_4_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2600_4_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2900_4_5_2_auto.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2900_4_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2900_4_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_3200_4_5_2_auto.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_3200_4_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_3200_4_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2400_4_5_2_auto.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2400_4_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2400_4_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2600_4_5_2_auto.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2600_4_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2600_4_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2900_4_5_2_auto.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2900_4_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2900_4_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_3200_4_5_2_auto.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_3200_4_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_3200_4_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2400_4_5_2_auto.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2400_4_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2400_4_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2600_4_5_2_auto.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2600_4_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2600_4_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2900_4_5_2_auto.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2900_4_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2900_4_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_3200_4_5_2_auto.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_3200_4_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_3200_4_5_2_xspi.rcw | 25 +++++++++++++++++++ + 49 files changed, 1201 insertions(+), 1 deletion(-) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_xspi.rcw + +diff --git a/GenerateSRConfigs.sh b/GenerateSRConfigs.sh +index 907e359..1c98023 100755 +--- a/GenerateSRConfigs.sh ++++ b/GenerateSRConfigs.sh +@@ -38,7 +38,7 @@ generate() { + for DDR_SPEED in 2400 2600 2900 3200; do + for SOC_REVISION in 1 2; do + for BOOTSOURCE in auto sdhc xspi; do +- for SD1 in 8 18; do ++ for SD1 in 4 8 18; do + generate lx2160acex7_clearfog-cx.tmpl lx2160acex7 ${SOC_REVISION} clearfog-cx 2000 700 ${DDR_SPEED} ${SD1} 5 2 ${BOOTSOURCE} + generate lx2160acex7_clearfog-cx.tmpl lx2160acex7 ${SOC_REVISION} clearfog-cx 2200 750 ${DDR_SPEED} ${SD1} 5 2 ${BOOTSOURCE} + done +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_auto.rcw +new file mode 100644 +index 0000000..1494b58 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_auto.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from AUTO ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_sdhc.rcw +new file mode 100644 +index 0000000..6dfc0d0 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_xspi.rcw +new file mode 100644 +index 0000000..c89ebc5 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_auto.rcw +new file mode 100644 +index 0000000..5ba12c7 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_auto.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from AUTO ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_sdhc.rcw +new file mode 100644 +index 0000000..87ef115 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_xspi.rcw +new file mode 100644 +index 0000000..9cf27a5 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_auto.rcw +new file mode 100644 +index 0000000..5486e12 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_auto.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from AUTO ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_sdhc.rcw +new file mode 100644 +index 0000000..11654c8 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_xspi.rcw +new file mode 100644 +index 0000000..e8fc8e2 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_auto.rcw +new file mode 100644 +index 0000000..48e090c +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_auto.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from AUTO ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_sdhc.rcw +new file mode 100644 +index 0000000..8da555a +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_xspi.rcw +new file mode 100644 +index 0000000..7ff9fc0 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_auto.rcw +new file mode 100644 +index 0000000..02607db +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_auto.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from AUTO ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_sdhc.rcw +new file mode 100644 +index 0000000..a20aa56 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_xspi.rcw +new file mode 100644 +index 0000000..865d6e8 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_auto.rcw +new file mode 100644 +index 0000000..946750e +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_auto.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from AUTO ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_sdhc.rcw +new file mode 100644 +index 0000000..8458141 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_xspi.rcw +new file mode 100644 +index 0000000..8313e25 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_auto.rcw +new file mode 100644 +index 0000000..92bde97 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_auto.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from AUTO ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_sdhc.rcw +new file mode 100644 +index 0000000..b754615 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_xspi.rcw +new file mode 100644 +index 0000000..571fb86 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_auto.rcw +new file mode 100644 +index 0000000..85836d1 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_auto.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from AUTO ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_AUTO ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_sdhc.rcw +new file mode 100644 +index 0000000..877da0f +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_xspi.rcw +new file mode 100644 +index 0000000..e1fb8d0 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_auto.rcw +new file mode 100644 +index 0000000..5b8f33d +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_auto.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from AUTO ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_sdhc.rcw +new file mode 100644 +index 0000000..d499f67 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_xspi.rcw +new file mode 100644 +index 0000000..362e13c +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_auto.rcw +new file mode 100644 +index 0000000..262a600 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_auto.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from AUTO ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_sdhc.rcw +new file mode 100644 +index 0000000..d1100b8 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_xspi.rcw +new file mode 100644 +index 0000000..606a38b +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_auto.rcw +new file mode 100644 +index 0000000..4afc979 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_auto.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from AUTO ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_sdhc.rcw +new file mode 100644 +index 0000000..82f2e78 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_xspi.rcw +new file mode 100644 +index 0000000..41d1a83 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_auto.rcw +new file mode 100644 +index 0000000..948094c +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_auto.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from AUTO ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_sdhc.rcw +new file mode 100644 +index 0000000..a50664e +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_xspi.rcw +new file mode 100644 +index 0000000..57cd7ba +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_auto.rcw +new file mode 100644 +index 0000000..e09a28f +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_auto.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from AUTO ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_sdhc.rcw +new file mode 100644 +index 0000000..271fc35 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_xspi.rcw +new file mode 100644 +index 0000000..b2acfa1 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_auto.rcw +new file mode 100644 +index 0000000..637ece3 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_auto.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from AUTO ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_sdhc.rcw +new file mode 100644 +index 0000000..009c2af +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_xspi.rcw +new file mode 100644 +index 0000000..e3e28c7 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_auto.rcw +new file mode 100644 +index 0000000..bfff9a6 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_auto.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from AUTO ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_sdhc.rcw +new file mode 100644 +index 0000000..32e5ef4 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_xspi.rcw +new file mode 100644 +index 0000000..affe4a2 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_auto.rcw +new file mode 100644 +index 0000000..0e731e9 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_auto.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from AUTO ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_sdhc.rcw +new file mode 100644 +index 0000000..7ca0f52 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_xspi.rcw +new file mode 100644 +index 0000000..4c9df2a +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 4 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_4.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0020-lx2160acex6-add-configuration-for-each-ddr-speed.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0020-lx2160acex6-add-configuration-for-each-ddr-speed.patch new file mode 100644 index 000000000000..5ffbed12ea04 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0020-lx2160acex6-add-configuration-for-each-ddr-speed.patch @@ -0,0 +1,285 @@ +From 16dccb51dec1c08fcf5dfcf5ca6778bb387f6b32 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Tue, 26 Nov 2024 11:11:57 +0100 +Subject: [PATCH] lx2160acex6: add configuration for each ddr speed + +Signed-off-by: Josua Mayer +--- + GenerateSRConfigs.sh | 6 +++++ + lx2160acex6_evb.tmpl | 24 +++++++++++++++++++ + .../evb/rcw_2000_700_2400_3_3_2_auto.rcw | 24 +++++++++++++++++++ + .../evb/rcw_2000_700_2600_3_3_2_auto.rcw | 24 +++++++++++++++++++ + .../evb/rcw_2000_700_2900_3_3_2_auto.rcw | 2 ++ + .../evb/rcw_2000_700_3200_3_3_2_auto.rcw | 24 +++++++++++++++++++ + .../evb/rcw_2200_750_2400_3_3_2_auto.rcw | 24 +++++++++++++++++++ + .../evb/rcw_2200_750_2600_3_3_2_auto.rcw | 24 +++++++++++++++++++ + .../evb/rcw_2200_750_2900_3_3_2_auto.rcw | 24 +++++++++++++++++++ + .../evb/rcw_2200_750_3200_3_3_2_auto.rcw | 2 ++ + 10 files changed, 178 insertions(+) + create mode 100644 lx2160acex6_evb.tmpl + create mode 100644 lx2160acex6_rev2/evb/rcw_2000_700_2400_3_3_2_auto.rcw + create mode 100644 lx2160acex6_rev2/evb/rcw_2000_700_2600_3_3_2_auto.rcw + create mode 100644 lx2160acex6_rev2/evb/rcw_2000_700_3200_3_3_2_auto.rcw + create mode 100644 lx2160acex6_rev2/evb/rcw_2200_750_2400_3_3_2_auto.rcw + create mode 100644 lx2160acex6_rev2/evb/rcw_2200_750_2600_3_3_2_auto.rcw + create mode 100644 lx2160acex6_rev2/evb/rcw_2200_750_2900_3_3_2_auto.rcw + +diff --git a/GenerateSRConfigs.sh b/GenerateSRConfigs.sh +index 1c98023..e55667a 100755 +--- a/GenerateSRConfigs.sh ++++ b/GenerateSRConfigs.sh +@@ -45,3 +45,9 @@ for DDR_SPEED in 2400 2600 2900 3200; do + done + done + done ++ ++# generate LX2160A CEX-6 Internal Evaluation Board ++for DDR_SPEED in 2400 2600 2900 3200; do ++ generate lx2160acex6_evb.tmpl lx2160acex6 2 evb 2000 700 ${DDR_SPEED} 3 3 2 auto ++ generate lx2160acex6_evb.tmpl lx2160acex6 2 evb 2200 750 ${DDR_SPEED} 3 3 2 auto ++done +diff --git a/lx2160acex6_evb.tmpl b/lx2160acex6_evb.tmpl +new file mode 100644 +index 0000000..79fbe85 +--- /dev/null ++++ b/lx2160acex6_evb.tmpl +@@ -0,0 +1,24 @@ ++/* ++ * SerDes Protocol 1 - %SD1% ++ * SerDes Protocol 2 - %SD2% ++ * SerDes Protocol 3 - %SD3% ++ * ++ * Frequencies: ++ * Core -- %CPU_SPEED% MHz ++ * Platform -- %BUS_SPEED% MHz ++ * DDR -- %DDR_SPEED% MT/s ++ * ++ * Silicon %SOC_REVISION%.0 ++ * Boot from %BOOTSOURCE% ++ */ ++ ++#define LX_SR %SOC_REVISION% ++#define LX_BOOTSOURCE_%BOOTSOURCE% ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_%CPU_SPEED%_%BUS_SPEED%_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_%DDR_SPEED%.rcwi> ++#include <../%module%_rev%SOC_REVISION%/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_%SD1%.rcwi> ++#include <../lx2160acex7/include/SD2_%SD2%.rcwi> ++#include <../lx2160acex7/include/SD3_%SD3%.rcwi> ++#include <../%module%_rev%SOC_REVISION%/include/common_pbi.rcwi> +diff --git a/lx2160acex6_rev2/evb/rcw_2000_700_2400_3_3_2_auto.rcw b/lx2160acex6_rev2/evb/rcw_2000_700_2400_3_3_2_auto.rcw +new file mode 100644 +index 0000000..3ba20f4 +--- /dev/null ++++ b/lx2160acex6_rev2/evb/rcw_2000_700_2400_3_3_2_auto.rcw +@@ -0,0 +1,24 @@ ++/* ++ * SerDes Protocol 1 - 3 ++ * SerDes Protocol 2 - 3 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from AUTO ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex6_rev2/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_3.rcwi> ++#include <../lx2160acex7/include/SD2_3.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex6_rev2/include/common_pbi.rcwi> +diff --git a/lx2160acex6_rev2/evb/rcw_2000_700_2600_3_3_2_auto.rcw b/lx2160acex6_rev2/evb/rcw_2000_700_2600_3_3_2_auto.rcw +new file mode 100644 +index 0000000..780ac70 +--- /dev/null ++++ b/lx2160acex6_rev2/evb/rcw_2000_700_2600_3_3_2_auto.rcw +@@ -0,0 +1,24 @@ ++/* ++ * SerDes Protocol 1 - 3 ++ * SerDes Protocol 2 - 3 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from AUTO ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex6_rev2/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_3.rcwi> ++#include <../lx2160acex7/include/SD2_3.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex6_rev2/include/common_pbi.rcwi> +diff --git a/lx2160acex6_rev2/evb/rcw_2000_700_2900_3_3_2_auto.rcw b/lx2160acex6_rev2/evb/rcw_2000_700_2900_3_3_2_auto.rcw +index 6ae1090..6d54680 100644 +--- a/lx2160acex6_rev2/evb/rcw_2000_700_2900_3_3_2_auto.rcw ++++ b/lx2160acex6_rev2/evb/rcw_2000_700_2900_3_3_2_auto.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2900 MT/s + * + * Silicon 2.0 ++ * Boot from AUTO + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex6_rev2/evb/rcw_2000_700_3200_3_3_2_auto.rcw b/lx2160acex6_rev2/evb/rcw_2000_700_3200_3_3_2_auto.rcw +new file mode 100644 +index 0000000..97c7ba3 +--- /dev/null ++++ b/lx2160acex6_rev2/evb/rcw_2000_700_3200_3_3_2_auto.rcw +@@ -0,0 +1,24 @@ ++/* ++ * SerDes Protocol 1 - 3 ++ * SerDes Protocol 2 - 3 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from AUTO ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex6_rev2/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_3.rcwi> ++#include <../lx2160acex7/include/SD2_3.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex6_rev2/include/common_pbi.rcwi> +diff --git a/lx2160acex6_rev2/evb/rcw_2200_750_2400_3_3_2_auto.rcw b/lx2160acex6_rev2/evb/rcw_2200_750_2400_3_3_2_auto.rcw +new file mode 100644 +index 0000000..fbb8156 +--- /dev/null ++++ b/lx2160acex6_rev2/evb/rcw_2200_750_2400_3_3_2_auto.rcw +@@ -0,0 +1,24 @@ ++/* ++ * SerDes Protocol 1 - 3 ++ * SerDes Protocol 2 - 3 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from AUTO ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex6_rev2/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_3.rcwi> ++#include <../lx2160acex7/include/SD2_3.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex6_rev2/include/common_pbi.rcwi> +diff --git a/lx2160acex6_rev2/evb/rcw_2200_750_2600_3_3_2_auto.rcw b/lx2160acex6_rev2/evb/rcw_2200_750_2600_3_3_2_auto.rcw +new file mode 100644 +index 0000000..68bd37f +--- /dev/null ++++ b/lx2160acex6_rev2/evb/rcw_2200_750_2600_3_3_2_auto.rcw +@@ -0,0 +1,24 @@ ++/* ++ * SerDes Protocol 1 - 3 ++ * SerDes Protocol 2 - 3 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from AUTO ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex6_rev2/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_3.rcwi> ++#include <../lx2160acex7/include/SD2_3.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex6_rev2/include/common_pbi.rcwi> +diff --git a/lx2160acex6_rev2/evb/rcw_2200_750_2900_3_3_2_auto.rcw b/lx2160acex6_rev2/evb/rcw_2200_750_2900_3_3_2_auto.rcw +new file mode 100644 +index 0000000..a38c602 +--- /dev/null ++++ b/lx2160acex6_rev2/evb/rcw_2200_750_2900_3_3_2_auto.rcw +@@ -0,0 +1,24 @@ ++/* ++ * SerDes Protocol 1 - 3 ++ * SerDes Protocol 2 - 3 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 750 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from AUTO ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex6_rev2/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_3.rcwi> ++#include <../lx2160acex7/include/SD2_3.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex6_rev2/include/common_pbi.rcwi> +diff --git a/lx2160acex6_rev2/evb/rcw_2200_750_3200_3_3_2_auto.rcw b/lx2160acex6_rev2/evb/rcw_2200_750_3200_3_3_2_auto.rcw +index a66d4ec..7839e7c 100644 +--- a/lx2160acex6_rev2/evb/rcw_2200_750_3200_3_3_2_auto.rcw ++++ b/lx2160acex6_rev2/evb/rcw_2200_750_3200_3_3_2_auto.rcw +@@ -9,9 +9,11 @@ + * DDR -- 3200 MT/s + * + * Silicon 2.0 ++ * Boot from AUTO + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_AUTO + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +-- +2.43.0 + From patchwork Sun Dec 8 14:38:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 2019762 Return-Path: X-Original-To: incoming-buildroot@patchwork.ozlabs.org Delivered-To: patchwork-incoming-buildroot@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=buildroot.org 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a640c23a62f3a-aa666cf5743sm204660366b.65.2024.12.08.06.38.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Dec 2024 06:38:39 -0800 (PST) From: Vladimir Oltean To: buildroot@buildroot.org Cc: Brandon Maier , Rabeeh Khoury , Josua Mayer , Ioana Ciornei Date: Sun, 8 Dec 2024 16:38:01 +0200 Message-ID: <20241208143802.1048266-11-olteanv@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241208143802.1048266-1-olteanv@gmail.com> References: <20241208143802.1048266-1-olteanv@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1733668722; x=1734273522; darn=buildroot.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=klj0DaP6mgjOW5bP4MTD7qBWf7/qiPC3te29X5cS3zQ=; b=iG2DBQMNyuXMTLr5ZVYhY0QFynrocVXb0ga5xzKhtutgsDU/EEgMpyYdK4gnqitI/O dkg1uJT09dVdv4B30N8OwPKlKg6eyQ3qG7qCF6wR//rQMyQc4jUtJtdVtfoExq3w7Q+9 dh9W0MIVZQwsnSYyhJ39JSe0r7wVIwKbG6n8UU455B31HbHhs/0746evB+fh7Z0QP6p9 0dlRPKs0FxX/jCzlr68t11I0ThLd1A8r/6XuZF4jl52Thuyy7HC2uJHdIGSm7LAn2ddH lVK2CH4km4ocS3qqdtVvwF3UM6RQhepaEJKDTDHBjwJ9WKhb8M1GzdWT4Vt+2XyGIRbn rAmw== X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dmarc=pass (p=none dis=none) header.from=gmail.com X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=iG2DBQMN Subject: [Buildroot] [PATCH v2 10/11] board/lx2160acex7: add u-boot patches X-BeenThere: buildroot@buildroot.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: buildroot-bounces@buildroot.org Sender: "buildroot" The board is not supported in upstream U-Boot. Add the SolidRun patches over NXP lf-5.15.71-2.2.0 which allow it to have a functional bootloader. Signed-off-by: Vladimir Oltean --- v1->v2: - split out from previous [PATCH 6/7] board/lx2160acex7: new platform - update to latest lx2160a_build HEAD ...d-solidrun-lx2160-cex7-board-support.patch | 1342 +++++++++++++++++ ...ait-100ms-for-Link-Up-in-ls_pcie_g4_.patch | 65 + ...t-100ms-for-Link-Up-in-ls_pcie_probe.patch | 64 + ...-calculation-of-ddr-clock-rate-to-in.patch | 63 + ...able-workaround-for-SPI-erratum-A-05.patch | 102 ++ ...x2160-cex7-enable-additional-drivers.patch | 96 ++ ...on-t-fail-boot-when-reading-eeprom-f.patch | 32 + ...x2160-cex7-fixup-u-boot-dts-dpmac-by.patch | 389 +++++ ...x2160acex7-enable-reading-tlv-eeprom.patch | 40 + ...x2160acex7-disable-second-usb-on-lx2.patch | 32 + ...x2160acex7-allocate-memory-before-pa.patch | 39 + ...upport-specifying-tlv-eeprom-in-DT-a.patch | 58 + ...x2160acex7-use-dt-alias-for-tlv-eepr.patch | 90 ++ ...om-fix-alias-access-to-second-eeprom.patch | 32 + 14 files changed, 2444 insertions(+) create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0001-add-solidrun-lx2160-cex7-board-support.patch create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0002-pci-ls_pcie_g4-Wait-100ms-for-Link-Up-in-ls_pcie_g4_.patch create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0003-pci-ls_pcie-Wait-100ms-for-Link-Up-in-ls_pcie_probe.patch create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0004-fsl-lsch3-update-calculation-of-ddr-clock-rate-to-in.patch create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0005-armv8-lx2160a-enable-workaround-for-SPI-erratum-A-05.patch create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0006-configs-lx2160-cex7-enable-additional-drivers.patch create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0007-cmd-tlv_eeprom-don-t-fail-boot-when-reading-eeprom-f.patch create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0008-board-solidrun-lx2160-cex7-fixup-u-boot-dts-dpmac-by.patch create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0009-board-solidrun-lx2160acex7-enable-reading-tlv-eeprom.patch create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0010-board-solidrun-lx2160acex7-disable-second-usb-on-lx2.patch create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0011-board-solidrun-lx2160acex7-allocate-memory-before-pa.patch create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0012-cmd-tlv_eeprom-support-specifying-tlv-eeprom-in-DT-a.patch create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0013-board-solidrun-lx2160acex7-use-dt-alias-for-tlv-eepr.patch create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0014-cmd-tlv_eeprom-fix-alias-access-to-second-eeprom.patch diff --git a/board/solidrun/lx2160acex7/patches/uboot/0001-add-solidrun-lx2160-cex7-board-support.patch b/board/solidrun/lx2160acex7/patches/uboot/0001-add-solidrun-lx2160-cex7-board-support.patch new file mode 100644 index 000000000000..93884d09a5f2 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/uboot/0001-add-solidrun-lx2160-cex7-board-support.patch @@ -0,0 +1,1342 @@ +From 9e4a5468f62cf4f639a2d6224d33f545c67d1a88 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Thu, 13 Jun 2024 17:26:47 +0200 +Subject: [PATCH] add solidrun lx2160-cex7 board support + +Signed-off-by: Josua Mayer +--- + arch/arm/Kconfig | 14 + + arch/arm/dts/Makefile | 1 + + arch/arm/dts/fsl-lx2160a-cex7-u-boot.dtsi | 22 ++ + arch/arm/dts/fsl-lx2160a-cex7.dts | 20 ++ + arch/arm/dts/fsl-lx2160a-cex7.dtsi | 187 ++++++++++ + board/solidrun/lx2160acex7/Kconfig | 15 + + board/solidrun/lx2160acex7/Makefile | 10 + + board/solidrun/lx2160acex7/ddr.c | 22 ++ + board/solidrun/lx2160acex7/eth_lx2160acex7.c | 88 +++++ + board/solidrun/lx2160acex7/lx2160a.c | 308 +++++++++++++++++ + configs/lx2160acex7_tfa_SECURE_BOOT_defconfig | 86 +++++ + configs/lx2160acex7_tfa_defconfig | 96 ++++++ + include/configs/lx2160acex7.h | 324 ++++++++++++++++++ + scripts/config_whitelist.txt | 6 + + 14 files changed, 1199 insertions(+) + create mode 100644 arch/arm/dts/fsl-lx2160a-cex7-u-boot.dtsi + create mode 100644 arch/arm/dts/fsl-lx2160a-cex7.dts + create mode 100644 arch/arm/dts/fsl-lx2160a-cex7.dtsi + create mode 100644 board/solidrun/lx2160acex7/Kconfig + create mode 100644 board/solidrun/lx2160acex7/Makefile + create mode 100644 board/solidrun/lx2160acex7/ddr.c + create mode 100644 board/solidrun/lx2160acex7/eth_lx2160acex7.c + create mode 100644 board/solidrun/lx2160acex7/lx2160a.c + create mode 100644 configs/lx2160acex7_tfa_SECURE_BOOT_defconfig + create mode 100644 configs/lx2160acex7_tfa_defconfig + create mode 100644 include/configs/lx2160acex7.h + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 39b6a2b1b5..7c51c37c93 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -1375,6 +1375,19 @@ config TARGET_LS2081ARDB + development platform that supports the QorIQ LS2081A/LS2041A + Layerscape Architecture processor. + ++config TARGET_LX2160ACEX7 ++ bool "Support lx2160acex7" ++ select ARCH_LX2160A ++ select ARM64 ++ select ARMV8_MULTIENTRY ++ select ARCH_SUPPORT_TFABOOT ++ select BOARD_LATE_INIT ++ help ++ Support for SolidRun LX2160ACEX7 platform. ++ The lx2160acex7 (LX2160A COM-Express Type 7) ++ is a high-performance platform based on the ++ QorIQ LX2160A Layerscape Architecture processor. ++ + config TARGET_LX2160ARDB + bool "Support lx2160ardb" + select ARCH_LX2160A +@@ -2261,6 +2274,7 @@ source "board/kontron/sl28/Kconfig" + source "board/myir/mys_6ulx/Kconfig" + source "board/seeed/npi_imx6ull/Kconfig" + source "board/socionext/developerbox/Kconfig" ++source "board/solidrun/lx2160acex7/Kconfig" + source "board/st/stv0991/Kconfig" + source "board/tcl/sl50/Kconfig" + source "board/toradex/colibri_pxa270/Kconfig" +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 709fdaecd7..8f6f5bf7cc 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -454,6 +454,7 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ + fsl-ls1028a-rdb.dtb \ + fsl-ls1028a-qds-duart.dtb \ + fsl-ls1028a-qds-lpuart.dtb \ ++ fsl-lx2160a-cex7.dtb \ + fsl-lx2160a-rdb.dtb \ + fsl-lx2160a-qds.dtb \ + fsl-lx2160a-qds-3-x-x.dtb \ +diff --git a/arch/arm/dts/fsl-lx2160a-cex7-u-boot.dtsi b/arch/arm/dts/fsl-lx2160a-cex7-u-boot.dtsi +new file mode 100644 +index 0000000000..9855fcb31c +--- /dev/null ++++ b/arch/arm/dts/fsl-lx2160a-cex7-u-boot.dtsi +@@ -0,0 +1,22 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++/ { ++ fanctrl-override { ++ compatible = "solidrun,lx2160acex7-fanctrl-override"; ++ override-gpios = <&gpio2 2 0>; ++ }; ++}; ++ ++&i2c0 { ++ u-boot,dm-pre-reloc; ++ ++ i2c-mux@77 { ++ u-boot,dm-pre-reloc; ++ ++ i2c@0 { ++ eeprom@57 { ++ u-boot,dm-pre-reloc; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/dts/fsl-lx2160a-cex7.dts b/arch/arm/dts/fsl-lx2160a-cex7.dts +new file mode 100644 +index 0000000000..60f99f143c +--- /dev/null ++++ b/arch/arm/dts/fsl-lx2160a-cex7.dts +@@ -0,0 +1,20 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Device Tree file for LX2160A-CEx7 Standalone (Generic Carrier Board) ++ * ++ * Copyright 2024 Josua Mayer ++ */ ++ ++#include "fsl-lx2160a-cex7.dtsi" ++ ++&dpmac17 { ++ status = "okay"; ++}; ++ ++&esdhc0 { ++ sd-uhs-sdr104; ++ sd-uhs-sdr50; ++ sd-uhs-sdr25; ++ sd-uhs-sdr12; ++ status = "okay"; ++}; +diff --git a/arch/arm/dts/fsl-lx2160a-cex7.dtsi b/arch/arm/dts/fsl-lx2160a-cex7.dtsi +new file mode 100644 +index 0000000000..d32a52ab00 +--- /dev/null ++++ b/arch/arm/dts/fsl-lx2160a-cex7.dtsi +@@ -0,0 +1,187 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++// ++// Device Tree file for LX2160A-CEx7 ++// ++// Copyright 2019 SolidRun Ltd. ++ ++/dts-v1/; ++ ++#include "fsl-lx2160a.dtsi" ++ ++/ { ++ model = "SolidRun LX2160A COM Express Type 7 module"; ++ compatible = "solidrun,lx2160a-cex7", "fsl,lx2160a"; ++ ++ aliases { ++ crypto = &crypto; ++ }; ++ ++ sb_3v3: regulator-sb3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "RT7290"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++}; ++ ++&crypto { ++ status = "okay"; ++}; ++ ++&dpmac17 { ++ phy-handle = <&rgmii_phy1>; ++ phy-connection-type = "rgmii-id"; ++}; ++ ++&emdio1 { ++ status = "okay"; ++ ++ rgmii_phy1: ethernet-phy@1 { ++ reg = <1>; ++ qca,smarteee-tw-us-1g = <24>; ++ }; ++}; ++ ++&esdhc1 { ++ mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++ bus-width = <8>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ i2c-mux@77 { ++ compatible = "nxp,pca9547"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x77>; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ ++ eeprom@50 { ++ compatible = "atmel,24c512"; ++ reg = <0x50>; ++ }; ++ ++ eeprom@51 { ++ compatible = "atmel,spd"; ++ reg = <0x51>; ++ }; ++ ++ eeprom@53 { ++ compatible = "atmel,spd"; ++ reg = <0x53>; ++ }; ++ ++ eeprom@57 { ++ compatible = "atmel,24c02"; ++ reg = <0x57>; ++ }; ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ ++ fan-temperature-ctrlr@18 { ++ compatible = "ti,amc6821"; ++ reg = <0x18>; ++ cooling-min-state = <0>; ++ cooling-max-state = <9>; ++ #cooling-cells = <2>; ++ }; ++ }; ++ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ ++ regulator@5c { ++ compatible = "lltc,ltc3882"; ++ reg = <0x5c>; ++ }; ++ }; ++ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ ++ temperature-sensor@48 { ++ compatible = "nxp,sa56004"; ++ reg = <0x48>; ++ vcc-supply = <&sb_3v3>; ++ }; ++ }; ++ ++ sfp0_i2c: i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ }; ++ ++ sfp1_i2c: i2c@5 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <5>; ++ }; ++ ++ sfp2_i2c: i2c@6 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <6>; ++ }; ++ ++ sfp3_i2c: i2c@7 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <7>; ++ }; ++ }; ++}; ++ ++&i2c2 { ++ status = "okay"; ++}; ++ ++&i2c4 { ++ status = "okay"; ++ ++ rtc@51 { ++ compatible = "nxp,pcf2129"; ++ reg = <0x51>; ++ }; ++}; ++ ++&fspi { ++ status = "okay"; ++ ++ flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "micron,m25p80"; ++ m25p,fast-read; ++ spi-max-frequency = <50000000>; ++ reg = <0>; ++ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */ ++ spi-rx-bus-width = <8>; ++ spi-tx-bus-width = <1>; ++ }; ++}; ++ ++&usb0 { ++ status = "okay"; ++}; ++ ++&usb1 { ++ status = "okay"; ++}; +diff --git a/board/solidrun/lx2160acex7/Kconfig b/board/solidrun/lx2160acex7/Kconfig +new file mode 100644 +index 0000000000..85673846a4 +--- /dev/null ++++ b/board/solidrun/lx2160acex7/Kconfig +@@ -0,0 +1,15 @@ ++if TARGET_LX2160ACEX7 ++ ++config SYS_BOARD ++ default "lx2160acex7" ++ ++config SYS_VENDOR ++ default "solidrun" ++ ++config SYS_SOC ++ default "fsl-layerscape" ++ ++config SYS_CONFIG_NAME ++ default "lx2160acex7" ++ ++endif +diff --git a/board/solidrun/lx2160acex7/Makefile b/board/solidrun/lx2160acex7/Makefile +new file mode 100644 +index 0000000000..4a3b039a5c +--- /dev/null ++++ b/board/solidrun/lx2160acex7/Makefile +@@ -0,0 +1,10 @@ ++# ++# Copyright 2018 Freescale Semiconductor ++# Copyright 2024 Josua Mayer ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++obj-y += lx2160a.o ++obj-y += ddr.o ++obj-$(CONFIG_TARGET_LX2160ACEX7) += eth_lx2160acex7.o +diff --git a/board/solidrun/lx2160acex7/ddr.c b/board/solidrun/lx2160acex7/ddr.c +new file mode 100644 +index 0000000000..d872e57530 +--- /dev/null ++++ b/board/solidrun/lx2160acex7/ddr.c +@@ -0,0 +1,22 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2018 NXP ++ * Copyright 2024 Josua Mayer ++ */ ++ ++#include ++#include ++#include ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++int fsl_initdram(void) ++{ ++ gd->ram_size = tfa_get_dram_size(); ++ ++ if (!gd->ram_size) ++ gd->ram_size = fsl_ddr_sdram_size(); ++ ++ return 0; ++} +diff --git a/board/solidrun/lx2160acex7/eth_lx2160acex7.c b/board/solidrun/lx2160acex7/eth_lx2160acex7.c +new file mode 100644 +index 0000000000..d2c68d3424 +--- /dev/null ++++ b/board/solidrun/lx2160acex7/eth_lx2160acex7.c +@@ -0,0 +1,88 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2018-2021 NXP ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++int board_eth_init(struct bd_info *bis) ++{ ++#if defined(CONFIG_FSL_MC_ENET) ++ struct memac_mdio_info mdio_info; ++ struct memac_mdio_controller *reg; ++ int i, interface; ++ struct mii_dev *dev; ++ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); ++ u32 srds_s1; ++ ++ srds_s1 = in_le32(&gur->rcwsr[28]) & ++ FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; ++ srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; ++ ++ reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; ++ mdio_info.regs = reg; ++ mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME; ++ ++ /* Register the EMI 1 */ ++ fm_memac_mdio_init(bis, &mdio_info); ++ ++ switch (srds_s1) { ++ case 8: ++ wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1); ++ break; ++ ++ default: ++ printf("SerDes1 protocol 0x%x is not supported on LX2160ACEX7\n", ++ srds_s1); ++ goto next; ++ } ++ ++ for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC17; i++) { ++ interface = wriop_get_enet_if(i); ++ switch (interface) { ++ case PHY_INTERFACE_MODE_RGMII: ++ case PHY_INTERFACE_MODE_RGMII_ID: ++ dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); ++ wriop_set_mdio(i, dev); ++ break; ++ default: ++ break; ++ } ++ } ++ ++next: ++ cpu_eth_init(bis); ++#endif /* CONFIG_FSL_MC_ENET */ ++ ++ return pci_eth_init(bis); ++} ++ ++#if defined(CONFIG_RESET_PHY_R) ++void reset_phy(void) ++{ ++#if defined(CONFIG_FSL_MC_ENET) ++ mc_env_boot(); ++#endif ++} ++#endif /* CONFIG_RESET_PHY_R */ ++ ++int mac_read_from_eeprom(void) ++{ ++ return 0; ++} ++ ++int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ++{ ++ puts("Not implemented.\n"); ++ return CMD_RET_FAILURE; ++} +diff --git a/board/solidrun/lx2160acex7/lx2160a.c b/board/solidrun/lx2160acex7/lx2160a.c +new file mode 100644 +index 0000000000..08fa607067 +--- /dev/null ++++ b/board/solidrun/lx2160acex7/lx2160a.c +@@ -0,0 +1,308 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2018-2021 NXP ++ * Copyright 2024 Josua Mayer ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++static struct pl01x_serial_plat serial0 = { ++#if CONFIG_CONS_INDEX == 0 ++ .base = CONFIG_SYS_SERIAL0, ++#elif CONFIG_CONS_INDEX == 1 ++ .base = CONFIG_SYS_SERIAL1, ++#else ++#error "Unsupported console index value." ++#endif ++ .type = TYPE_PL011, ++}; ++ ++U_BOOT_DRVINFO(nxp_serial0) = { ++ .name = "serial_pl01x", ++ .plat = &serial0, ++}; ++ ++static struct pl01x_serial_plat serial1 = { ++ .base = CONFIG_SYS_SERIAL1, ++ .type = TYPE_PL011, ++}; ++ ++U_BOOT_DRVINFO(nxp_serial1) = { ++ .name = "serial_pl01x", ++ .plat = &serial1, ++}; ++ ++static void uart_get_clock(void) ++{ ++ serial0.clock = get_serial_clock(); ++ serial1.clock = get_serial_clock(); ++} ++ ++int board_early_init_f(void) ++{ ++#ifdef CONFIG_SYS_I2C_EARLY_INIT ++ i2c_early_init_f(); ++#endif ++ /* get required clock for UART IP */ ++ uart_get_clock(); ++ ++ fsl_lsch3_early_init_f(); ++ return 0; ++} ++ ++#ifdef CONFIG_OF_BOARD_FIXUP ++int board_fix_fdt(void *fdt) ++{ ++ char *reg_names, *reg_name; ++ int names_len, old_name_len, new_name_len, remaining_names_len; ++ struct str_map { ++ char *old_str; ++ char *new_str; ++ } reg_names_map[] = { ++ { "ccsr", "dbi" }, ++ { "pf_ctrl", "ctrl" } ++ }; ++ int off = -1, i = 0; ++ ++ if (IS_SVR_REV(get_svr(), 1, 0)) ++ return 0; ++ ++ off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie"); ++ while (off != -FDT_ERR_NOTFOUND) { ++ fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie", ++ strlen("fsl,ls-pcie") + 1); ++ ++ reg_names = (char *)fdt_getprop(fdt, off, "reg-names", ++ &names_len); ++ if (!reg_names) ++ continue; ++ ++ reg_name = reg_names; ++ remaining_names_len = names_len - (reg_name - reg_names); ++ i = 0; ++ while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) { ++ old_name_len = strlen(reg_names_map[i].old_str); ++ new_name_len = strlen(reg_names_map[i].new_str); ++ if (memcmp(reg_name, reg_names_map[i].old_str, ++ old_name_len) == 0) { ++ /* first only leave required bytes for new_str ++ * and copy rest of the string after it ++ */ ++ memcpy(reg_name + new_name_len, ++ reg_name + old_name_len, ++ remaining_names_len - old_name_len); ++ /* Now copy new_str */ ++ memcpy(reg_name, reg_names_map[i].new_str, ++ new_name_len); ++ names_len -= old_name_len; ++ names_len += new_name_len; ++ i++; ++ } ++ ++ reg_name = memchr(reg_name, '\0', remaining_names_len); ++ if (!reg_name) ++ break; ++ ++ reg_name += 1; ++ ++ remaining_names_len = names_len - ++ (reg_name - reg_names); ++ } ++ ++ fdt_setprop(fdt, off, "reg-names", reg_names, names_len); ++ off = fdt_node_offset_by_compatible(fdt, off, ++ "fsl,lx2160a-pcie"); ++ } ++ ++ return 0; ++} ++#endif ++ ++int esdhc_status_fixup(void *blob, const char *compat) ++{ ++ /* Enable both esdhc DT nodes for LX2160ARDB */ ++ do_fixup_by_compat(blob, compat, "status", "okay", ++ sizeof("okay"), 1); ++ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ enum boot_src src = get_boot_src(); ++ char buf[64]; ++ ++ cpu_name(buf); ++ printf("Board: LX2160A-CEX7, %s, boot from ", buf); ++ ++ if (src == BOOT_SOURCE_SD_MMC) { ++ puts("SD\n"); ++ } else if (src == BOOT_SOURCE_SD_MMC2) { ++ puts("eMMC\n"); ++ } else if (src == BOOT_SOURCE_XSPI_NOR) { ++ puts("FlexSPI\n"); ++ } ++ ++ return 0; ++} ++ ++int config_board_mux(void) ++{ ++ return 0; ++} ++ ++unsigned long get_board_sys_clk(void) ++{ ++ return 100000000; ++} ++ ++unsigned long get_board_ddr_clk(void) ++{ ++ return 100000000; ++} ++ ++int board_init(void) ++{ ++#ifdef CONFIG_ENV_IS_NOWHERE ++ gd->env_addr = (ulong)&default_environment[0]; ++#endif ++ ++#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) ++ pci_init(); ++#endif ++ return 0; ++} ++ ++void detail_board_ddr_info(void) ++{ ++ int i; ++ u64 ddr_size = 0; ++ ++ puts("\nDDR "); ++ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) ++ ddr_size += gd->bd->bi_dram[i].size; ++ print_size(ddr_size, ""); ++ print_ddr_info(0); ++} ++ ++#ifdef CONFIG_MISC_INIT_R ++int misc_init_r(void) ++{ ++ config_board_mux(); ++ ++ return 0; ++} ++#endif ++ ++#ifdef CONFIG_FSL_MC_ENET ++void fdt_fixup_board_enet(void *fdt) ++{ ++ int offset; ++ ++ offset = fdt_path_offset(fdt, "/soc/fsl-mc"); ++ ++ if (offset < 0) ++ offset = fdt_path_offset(fdt, "/fsl-mc"); ++ ++ if (offset < 0) { ++ printf("%s: fsl-mc node not found in device tree (error %d)\n", ++ __func__, offset); ++ return; ++ } ++ ++ if (get_mc_boot_status() == 0 && ++ (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) { ++ fdt_status_okay(fdt, offset); ++ } else { ++ fdt_status_fail(fdt, offset); ++ } ++} ++ ++void board_quiesce_devices(void) ++{ ++ fsl_mc_ldpaa_exit(gd->bd); ++} ++#endif ++ ++#ifdef CONFIG_OF_BOARD_SETUP ++int ft_board_setup(void *blob, struct bd_info *bd) ++{ ++ int i; ++ u16 mc_memory_bank = 0; ++ ++ u64 *base; ++ u64 *size; ++ u64 mc_memory_base = 0; ++ u64 mc_memory_size = 0; ++ u16 total_memory_banks; ++ ++ ft_cpu_setup(blob, bd); ++ ++ fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); ++ ++ if (mc_memory_base != 0) ++ mc_memory_bank++; ++ ++ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; ++ ++ base = calloc(total_memory_banks, sizeof(u64)); ++ size = calloc(total_memory_banks, sizeof(u64)); ++ ++ /* fixup DT for the three GPP DDR banks */ ++ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { ++ base[i] = gd->bd->bi_dram[i].start; ++ size[i] = gd->bd->bi_dram[i].size; ++ } ++ ++#ifdef CONFIG_RESV_RAM ++ /* reduce size if reserved memory is within this bank */ ++ if (gd->arch.resv_ram >= base[0] && ++ gd->arch.resv_ram < base[0] + size[0]) ++ size[0] = gd->arch.resv_ram - base[0]; ++ else if (gd->arch.resv_ram >= base[1] && ++ gd->arch.resv_ram < base[1] + size[1]) ++ size[1] = gd->arch.resv_ram - base[1]; ++ else if (gd->arch.resv_ram >= base[2] && ++ gd->arch.resv_ram < base[2] + size[2]) ++ size[2] = gd->arch.resv_ram - base[2]; ++#endif ++ ++ if (mc_memory_base != 0) { ++ for (i = 0; i <= total_memory_banks; i++) { ++ if (base[i] == 0 && size[i] == 0) { ++ base[i] = mc_memory_base; ++ size[i] = mc_memory_size; ++ break; ++ } ++ } ++ } ++ ++ fdt_fixup_memory_banks(blob, base, size, total_memory_banks); ++ ++#ifdef CONFIG_USB ++ fsl_fdt_fixup_dr_usb(blob, bd); ++#endif ++ ++#ifdef CONFIG_FSL_MC_ENET ++ fdt_fsl_mc_fixup_iommu_map_entry(blob); ++ fdt_fixup_board_enet(blob); ++#endif ++ fdt_fixup_icid(blob); ++ ++ return 0; ++} ++#endif +diff --git a/configs/lx2160acex7_tfa_SECURE_BOOT_defconfig b/configs/lx2160acex7_tfa_SECURE_BOOT_defconfig +new file mode 100644 +index 0000000000..12f236aad0 +--- /dev/null ++++ b/configs/lx2160acex7_tfa_SECURE_BOOT_defconfig +@@ -0,0 +1,86 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_GIC_V3_ITS=y ++CONFIG_TARGET_LX2160ACEX7=y ++CONFIG_TFABOOT=y ++CONFIG_SYS_TEXT_BASE=0x82000000 ++CONFIG_SYS_MALLOC_LEN=0x202000 ++CONFIG_SYS_MALLOC_F_LEN=0x6000 ++CONFIG_NR_DRAM_BANKS=3 ++CONFIG_ENV_SIZE=0x2000 ++CONFIG_NXP_ESBC=y ++CONFIG_DM_GPIO=y ++CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7" ++CONFIG_FSPI_AHB_EN_4BYTE=y ++CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y ++CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y ++CONFIG_AHCI=y ++CONFIG_OF_BOARD_FIXUP=y ++CONFIG_REMAKE_ELF=y ++CONFIG_MP=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_OF_BOARD_SETUP=y ++CONFIG_OF_STDOUT_VIA_ALIAS=y ++CONFIG_DYNAMIC_SYS_CLK_FREQ=y ++CONFIG_USE_BOOTARGS=y ++CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" ++CONFIG_DEFAULT_FDT_FILE="freescale/fsl-lx2160a-clearfog-cx.dtb" ++CONFIG_MISC_INIT_R=y ++CONFIG_CMD_GREPENV=y ++CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 ++CONFIG_CMD_DM=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_CACHE=y ++CONFIG_OF_CONTROL=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_DM=y ++CONFIG_SATA=y ++CONFIG_SATA_CEVA=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y ++CONFIG_MPC8XXX_GPIO=y ++CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 ++CONFIG_MMC_HS400_SUPPORT=y ++CONFIG_FSL_ESDHC=y ++CONFIG_MTD=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_SPI_FLASH_MT35XU=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_PHYLIB=y ++CONFIG_PHY_ATHEROS=y ++CONFIG_DM_ETH=y ++CONFIG_DM_MDIO=y ++CONFIG_E1000=y ++CONFIG_MII=y ++CONFIG_FSL_LS_MDIO=y ++CONFIG_NVME_PCI=y ++CONFIG_PCI=y ++CONFIG_PCIE_LAYERSCAPE_RC=y ++CONFIG_PCIE_LAYERSCAPE_GEN4=y ++CONFIG_DM_RTC=y ++CONFIG_RTC_PCF2127=y ++CONFIG_DM_SCSI=y ++CONFIG_DM_SERIAL=y ++CONFIG_PL01X_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_NXP_FSPI=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_RSA=y ++CONFIG_SPL_RSA=y ++CONFIG_RSA_SOFTWARE_EXP=y ++CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig +new file mode 100644 +index 0000000000..9f24e12a85 +--- /dev/null ++++ b/configs/lx2160acex7_tfa_defconfig +@@ -0,0 +1,96 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_GIC_V3_ITS=y ++CONFIG_TARGET_LX2160ACEX7=y ++CONFIG_TFABOOT=y ++CONFIG_SYS_TEXT_BASE=0x82000000 ++CONFIG_SYS_MALLOC_LEN=0x202000 ++CONFIG_SYS_MALLOC_F_LEN=0x6000 ++CONFIG_NR_DRAM_BANKS=3 ++CONFIG_ENV_SIZE=0x2000 ++CONFIG_ENV_OFFSET=0x500000 ++CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_DM_GPIO=y ++CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7" ++CONFIG_FSPI_AHB_EN_4BYTE=y ++CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y ++CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y ++CONFIG_AHCI=y ++CONFIG_OF_BOARD_FIXUP=y ++CONFIG_REMAKE_ELF=y ++CONFIG_MP=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_OF_BOARD_SETUP=y ++CONFIG_OF_STDOUT_VIA_ALIAS=y ++CONFIG_DYNAMIC_SYS_CLK_FREQ=y ++CONFIG_BOOTDELAY=10 ++CONFIG_USE_BOOTARGS=y ++CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" ++CONFIG_DEFAULT_FDT_FILE="freescale/fsl-lx2160a-clearfog-cx.dtb" ++CONFIG_MISC_INIT_R=y ++CONFIG_CMD_GREPENV=y ++CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 ++CONFIG_CMD_DM=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_OPTEE_RPMB=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_WDT=y ++CONFIG_CMD_CACHE=y ++CONFIG_OF_CONTROL=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_ENV_IS_IN_SPI_FLASH=y ++CONFIG_ENV_ADDR=0x20500000 ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_DM=y ++CONFIG_SATA=y ++CONFIG_SATA_CEVA=y ++CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y ++CONFIG_MPC8XXX_GPIO=y ++CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_HS400_SUPPORT=y ++CONFIG_FSL_ESDHC=y ++CONFIG_MTD=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_SPI_FLASH_MT35XU=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_PHYLIB=y ++CONFIG_PHY_ATHEROS=y ++CONFIG_DM_ETH=y ++CONFIG_DM_MDIO=y ++CONFIG_E1000=y ++CONFIG_MII=y ++CONFIG_FSL_LS_MDIO=y ++CONFIG_NVME_PCI=y ++CONFIG_PCI=y ++CONFIG_PCIE_LAYERSCAPE_RC=y ++CONFIG_PCIE_LAYERSCAPE_GEN4=y ++CONFIG_DM_RTC=y ++CONFIG_RTC_PCF2127=y ++CONFIG_DM_SCSI=y ++CONFIG_DM_SERIAL=y ++CONFIG_PL01X_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_NXP_FSPI=y ++CONFIG_TEE=y ++CONFIG_OPTEE=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_WDT=y ++CONFIG_WDT_SBSA=y ++CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h +new file mode 100644 +index 0000000000..83f64e65a8 +--- /dev/null ++++ b/include/configs/lx2160acex7.h +@@ -0,0 +1,324 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2018-2022 NXP ++ * Copyright 2024 Josua Mayer ++ */ ++ ++#ifndef __CONFIG_LX2160ACEX7_H ++#define __CONFIG_LX2160ACEX7_H ++ ++#include ++#include ++#include ++ ++#define CONFIG_FSL_MEMAC ++ ++#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE ++#define CONFIG_SYS_FLASH_BASE 0x20000000 ++ ++/* DDR */ ++#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ ++#define CONFIG_VERY_BIG_RAM ++#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL ++#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 ++#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL ++#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 ++#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL ++#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE ++#define CONFIG_MEM_INIT_VALUE 0xdeadbeef ++#define SPD_EEPROM_ADDRESS1 0x51 ++#define SPD_EEPROM_ADDRESS2 0x52 ++#define SPD_EEPROM_ADDRESS3 0x53 ++#define SPD_EEPROM_ADDRESS4 0x54 ++#define SPD_EEPROM_ADDRESS5 0x55 ++#define SPD_EEPROM_ADDRESS6 0x56 ++#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 ++#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ ++#define CONFIG_DIMM_SLOTS_PER_CTLR 1 ++#define CONFIG_CHIP_SELECTS_PER_CTRL 4 ++#define CONFIG_SYS_MONITOR_LEN (936 * 1024) ++ ++/* SMP Definitinos */ ++#define CPU_RELEASE_ADDR secondary_boot_addr ++ ++/* Generic Timer Definitions */ ++/* ++ * This is not an accurate number. It is used in start.S. The frequency ++ * will be udpated later when get_bus_freq(0) is available. ++ */ ++ ++#define COUNTER_FREQUENCY 25000000 /* 25MHz */ ++ ++/* Serial Port */ ++#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4) ++#define CONFIG_SYS_SERIAL0 0x21c0000 ++#define CONFIG_SYS_SERIAL1 0x21d0000 ++#define CONFIG_SYS_SERIAL2 0x21e0000 ++#define CONFIG_SYS_SERIAL3 0x21f0000 ++/*below might needs to be removed*/ ++#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ ++ (void *)CONFIG_SYS_SERIAL1, \ ++ (void *)CONFIG_SYS_SERIAL2, \ ++ (void *)CONFIG_SYS_SERIAL3 } ++ ++/* MC firmware */ ++#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 ++#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 ++#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 ++#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 ++#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 ++ ++/* Define phy_reset function to boot the MC based on mcinitcmd. ++ * This happens late enough to properly fixup u-boot env MAC addresses. ++ */ ++#define CONFIG_RESET_PHY_R ++ ++/* ++ * Carve out a DDR region which will not be used by u-boot/Linux ++ * ++ * It will be used by MC and Debug Server. The MC region must be ++ * 512MB aligned, so the min size to hide is 512MB. ++ */ ++#ifdef CONFIG_FSL_MC_ENET ++#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) ++#endif ++ ++/* GPIO */ ++#define CONFIG_GPIO_EXTRA_HEADER ++ ++/* SATA */ ++#ifdef CONFIG_SCSI ++#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 ++#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 ++#define CONFIG_SYS_SATA3 AHCI_BASE_ADDR3 ++#define CONFIG_SYS_SATA4 AHCI_BASE_ADDR4 ++#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 ++#define CONFIG_SYS_SCSI_MAX_LUN 1 ++#endif ++ ++/* USB */ ++#ifdef CONFIG_USB ++#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 ++#endif ++ ++/* MAC/PHY configuration */ ++#if defined(CONFIG_FSL_MC_ENET) ++#define CONFIG_ETHPRIME "DPMAC17@rgmii-id" ++#define RGMII_PHY_ADDR1 0x01 ++#endif ++ ++#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4) ++ ++#define CONFIG_HWCONFIG ++#define HWCONFIG_BUFFER_SIZE 128 ++ ++/* Monitor Command Prompt */ ++#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ ++#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ ++ sizeof(CONFIG_SYS_PROMPT) + 16) ++#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ ++#define CONFIG_SYS_MAXARGS 64 /* max command args */ ++ ++#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ ++ ++/* ++ * Memory Layout Ovverview: ++ * ++ */ ++ ++/* ++ * Boot-Media Latout: ++ * - SD/eMMC MC offsets (in sectors): ++ * - 0x3000: kernel header ++ * - 0x3200: mc firmware header ++ * - 0x3400: dpc header ++ * - 0x5000: firmware ++ * - 0x6800: dpl ++ * - 0x7000: dpc ++ * - 0x7800: dtb ++ * - 0x8000: kernel ++ * - SPI offsets (in byte): ++ * - 0x0600000: kernel header ++ * - 0x0640000: mc firmware header ++ * - 0x0680000: dpc header ++ * - 0x0a00000: mc firmware ++ * - 0x0e00000: dpc ++ * - 0x0d00000: dpl ++ * - 0x0f00000: dtb ++ * - 0x1000000: kernel ++ */ ++ ++/* ++ * Load Adresses (different from lx2160a_common.h): ++ * Use GPP DRAM Region #1 (2GB: [0x80000000-0xffffffff]). ++ * - 16MB for secure-boot / mc ([0x80000000-0x80ffffff]) ++ * - 1MB for boot-script ++ * - 1MB for pxe ++ * - 1MB for DTB ++ * - 64MB for compressed kernel ++ * - 512MB for uncompressed kernel ++ * - ~1.5GB for ramdisk ++ */ ++#define SCRIPT_ADDR_R __stringify(0x81000000) ++#define PXEFILE_ADDR_R __stringify(0x81100000) ++#define FDT_ADDR_R __stringify(0x81200000) ++#define KERNEL_COMP_ADDR_R __stringify(0x81300000) ++#define KERNEL_COMP_SIZE __stringify(0x04000000) ++#define KERNEL_ADDR_R __stringify(0x85300000) ++#define RAMDISK_ADDR_R __stringify(0xa5300000) ++#define FDT_RELOCATION_LIMIT __stringify(0xffffffff) ++ ++/* Initial environment variables */ ++#define XSPI_MC_INIT_CMD \ ++ "sf probe 0:0 && " \ ++ "sf read 0x80640000 0x640000 0x80000 && " \ ++ "sf read $fdt_addr_r 0xf00000 0x100000 && " \ ++ "env exists secureboot && " \ ++ "esbc_validate 0x80640000 && " \ ++ "esbc_validate 0x80680000; " \ ++ "sf read 0x80a00000 0xa00000 0x300000 && " \ ++ "sf read 0x80e00000 0xe00000 0x100000; " \ ++ "fsl_mc start mc 0x80a00000 0x80e00000\0" ++ ++#define SD_MC_INIT_CMD \ ++ "mmc read 0x80a00000 0x5000 0x1200;" \ ++ "mmc read 0x80e00000 0x7000 0x800;" \ ++ "mmc read $fdt_addr_r 0x7800 0x800;" \ ++ "env exists secureboot && " \ ++ "mmc read 0x80640000 0x3200 0x20 && " \ ++ "mmc read 0x80680000 0x3400 0x20 && " \ ++ "esbc_validate 0x80640000 && " \ ++ "esbc_validate 0x80680000 ;" \ ++ "fsl_mc start mc 0x80a00000 0x80e00000\0" ++ ++#define SD2_MC_INIT_CMD \ ++ "mmc dev 1; mmc read 0x80a00000 0x5000 0x1200;" \ ++ "mmc read 0x80e00000 0x7000 0x800;" \ ++ "mmc read $fdt_addr_r 0x7800 0x800;" \ ++ "env exists secureboot && " \ ++ "mmc read 0x80640000 0x3200 0x20 && " \ ++ "mmc read 0x80680000 0x3400 0x20 && " \ ++ "esbc_validate 0x80640000 && " \ ++ "esbc_validate 0x80680000 ;" \ ++ "fsl_mc start mc 0x80a00000 0x80e00000\0" ++ ++#define EXTRA_ENV_SETTINGS \ ++ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ ++ "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ ++ "fdt_high=" FDT_RELOCATION_LIMIT "\0" \ ++ "initrd_high=0xffffffffffffffff\0" \ ++ "kernel_start=0x1000000\0" \ ++ "kernelheader_start=0x600000\0" \ ++ "scriptaddr=" SCRIPT_ADDR_R "\0" \ ++ "scripthdraddr=0x80080000\0" \ ++ "fdtheader_addr_r=0x80100000\0" \ ++ "kernelheader_addr_r=0x80200000\0" \ ++ "kernel_addr_r=" KERNEL_ADDR_R "\0" \ ++ "kernelheader_size=0x40000\0" \ ++ "fdt_addr_r=" FDT_ADDR_R "\0" \ ++ "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \ ++ "kernel_comp_addr_r=" KERNEL_COMP_ADDR_R "\0" \ ++ "kernel_comp_size=" KERNEL_COMP_SIZE "\0" \ ++ "load_addr=" KERNEL_ADDR_R "\0" \ ++ "kernel_size=0x2800000\0" \ ++ "kernel_addr_sd=0x8000\0" \ ++ "kernelhdr_addr_sd=0x3000\0" \ ++ "kernel_size_sd=0x14000\0" \ ++ "kernelhdr_size_sd=0x20\0" \ ++ "console=ttyAMA0,115200n8\0" \ ++ BOOTENV \ ++ "mcmemsize=0x70000000\0" \ ++ XSPI_MC_INIT_CMD \ ++ "scan_dev_for_boot_part=" \ ++ "part list ${devtype} ${devnum} devplist; " \ ++ "env exists devplist || setenv devplist 1; " \ ++ "for distro_bootpart in ${devplist}; do " \ ++ "if fstype ${devtype} " \ ++ "${devnum}:${distro_bootpart} " \ ++ "bootfstype; then " \ ++ "run scan_dev_for_boot; " \ ++ "fi; " \ ++ "done\0" \ ++ "boot_a_script=" \ ++ "load ${devtype} ${devnum}:${distro_bootpart} " \ ++ "${scriptaddr} ${prefix}${script}; " \ ++ "env exists secureboot && load ${devtype} " \ ++ "${devnum}:${distro_bootpart} " \ ++ "${scripthdraddr} ${prefix}${boot_script_hdr} " \ ++ "&& esbc_validate ${scripthdraddr};" \ ++ "source ${scriptaddr}\0" ++ ++#define XSPI_NOR_BOOTCOMMAND \ ++ "sf probe 0:0; " \ ++ "sf read 0x806c0000 0x6c0000 0x40000; " \ ++ "env exists mcinitcmd && env exists secureboot" \ ++ " && esbc_validate 0x806c0000; " \ ++ "sf read 0x80d00000 0xd00000 0x100000; " \ ++ "env exists mcinitcmd && " \ ++ "fsl_mc lazyapply dpl 0x80d00000; " \ ++ "run distro_bootcmd;run xspi_bootcmd; " \ ++ "env exists secureboot && esbc_halt;" ++ ++#define SD_BOOTCOMMAND \ ++ "env exists mcinitcmd && mmcinfo; " \ ++ "mmc read 0x80d00000 0x6800 0x800; " \ ++ "env exists mcinitcmd && env exists secureboot " \ ++ " && mmc read 0x806C0000 0x3600 0x20 " \ ++ "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ ++ "&& fsl_mc lazyapply dpl 0x80d00000;" \ ++ "run distro_bootcmd;run sd_bootcmd;" \ ++ "env exists secureboot && esbc_halt;" ++ ++#define SD2_BOOTCOMMAND \ ++ "mmc dev 1; env exists mcinitcmd && mmcinfo; " \ ++ "mmc read 0x80d00000 0x6800 0x800; " \ ++ "env exists mcinitcmd && env exists secureboot " \ ++ " && mmc read 0x806C0000 0x3600 0x20 " \ ++ "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ ++ "&& fsl_mc lazyapply dpl 0x80d00000;" \ ++ "run distro_bootcmd;run sd2_bootcmd;" \ ++ "env exists secureboot && esbc_halt;" ++ ++/* configure boot order for distro-boot feature */ ++#define BOOT_TARGET_DEVICES(func) \ ++ func(USB, usb, 0) \ ++ func(MMC, mmc, 0) \ ++ func(MMC, mmc, 1) \ ++ func(SCSI, scsi, 0) \ ++ func(SCSI, scsi, 1) \ ++ func(SCSI, scsi, 2) \ ++ func(SCSI, scsi, 3) \ ++ func(PXE, pxe, na) \ ++ func(DHCP, dhcp, na) ++#include ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ EXTRA_ENV_SETTINGS \ ++ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ ++ "boot_scripts=lx2160acex7_boot.scr\0" \ ++ "boot_script_hdr=hdr_lx2160acex7_bs.out\0" \ ++ "BOARD=lx2160acex7\0" \ ++ "xspi_bootcmd=echo Trying load from flexspi..;" \ ++ "sf probe 0:0 && sf read $load_addr " \ ++ "$kernel_start $kernel_size ; env exists secureboot &&" \ ++ "sf read $kernelheader_addr_r $kernelheader_start " \ ++ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ ++ " bootm $load_addr#$BOARD\0" \ ++ "sd_bootcmd=echo Trying load from sd card..;" \ ++ "mmc dev 0; mmcinfo; mmc read $load_addr " \ ++ "$kernel_addr_sd $kernel_size_sd ;" \ ++ "env exists secureboot && mmc read $kernelheader_addr_r "\ ++ "$kernelhdr_addr_sd $kernelhdr_size_sd " \ ++ " && esbc_validate ${kernelheader_addr_r};" \ ++ "bootm $load_addr#$BOARD\0" \ ++ "sd2_bootcmd=echo Trying load from emmc card..;" \ ++ "mmc dev 1; mmcinfo; mmc read $load_addr " \ ++ "$kernel_addr_sd $kernel_size_sd ;" \ ++ "env exists secureboot && mmc read $kernelheader_addr_r "\ ++ "$kernelhdr_addr_sd $kernelhdr_size_sd " \ ++ " && esbc_validate ${kernelheader_addr_r};" \ ++ "bootm $load_addr#$BOARD\0" ++ ++#include ++ ++#endif /* __CONFIG_LX2160ACEX7_H */ +diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt +index 8abfe47888..b8c0735d75 100644 +--- a/scripts/config_whitelist.txt ++++ b/scripts/config_whitelist.txt +@@ -1858,6 +1858,12 @@ CONFIG_SYS_SATA1_OFFSET + CONFIG_SYS_SATA2 + CONFIG_SYS_SATA2_FLAGS + CONFIG_SYS_SATA2_OFFSET ++CONFIG_SYS_SATA3 ++CONFIG_SYS_SATA3_FLAGS ++CONFIG_SYS_SATA3_OFFSET ++CONFIG_SYS_SATA4 ++CONFIG_SYS_SATA4_FLAGS ++CONFIG_SYS_SATA4_OFFSET + CONFIG_SYS_SATA_ENV_DEV + CONFIG_SYS_SATA_FAT_BOOT_PARTITION + CONFIG_SYS_SBFHDR_DATA_OFFSET +-- +2.35.3 + diff --git a/board/solidrun/lx2160acex7/patches/uboot/0002-pci-ls_pcie_g4-Wait-100ms-for-Link-Up-in-ls_pcie_g4_.patch b/board/solidrun/lx2160acex7/patches/uboot/0002-pci-ls_pcie_g4-Wait-100ms-for-Link-Up-in-ls_pcie_g4_.patch new file mode 100644 index 000000000000..02cdff7ac52e --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/uboot/0002-pci-ls_pcie_g4-Wait-100ms-for-Link-Up-in-ls_pcie_g4_.patch @@ -0,0 +1,65 @@ +From 4c869a8ebbd4eff85f7fbd7d7102777dadcc0dd9 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Wed, 3 Apr 2024 17:58:37 +0200 +Subject: [PATCH 2/3] pci: ls_pcie_g4: Wait 100ms for Link Up in + ls_pcie_g4_probe + +PCI Link-up can be delayed especially with pci bridges or fpga starting +up slowly. + +Add a 100ms delay during probe polling for link-up. + +Signed-off-by: Josua Mayer +--- + drivers/pci/pcie_layerscape_gen4.c | 21 ++++++++++++++++++++- + 1 file changed, 20 insertions(+), 1 deletion(-) + +diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c +index 6ecdd6af408..eeda47470c1 100644 +--- a/drivers/pci/pcie_layerscape_gen4.c ++++ b/drivers/pci/pcie_layerscape_gen4.c +@@ -19,6 +19,9 @@ + + #include "pcie_layerscape_gen4.h" + ++#define LINK_WAIT_RETRIES 100 ++#define LINK_WAIT_TIMEOUT 1000 ++ + DECLARE_GLOBAL_DATA_PTR; + + LIST_HEAD(ls_pcie_g4_list); +@@ -50,6 +53,22 @@ static int ls_pcie_g4_link_up(struct ls_pcie_g4 *pcie) + return 1; + } + ++static int ls_pcie_g4_wait_for_link(struct ls_pcie_g4 *pcie) ++{ ++ int retries; ++ ++ /* check if the link is up or not */ ++ for (retries = 0; retries < LINK_WAIT_RETRIES; retries++) { ++ if (ls_pcie_g4_link_up(pcie)) { ++ return 1; ++ } ++ ++ udelay(LINK_WAIT_TIMEOUT); ++ } ++ ++ return 0; ++} ++ + static void ls_pcie_g4_ep_enable_cfg(struct ls_pcie_g4 *pcie) + { + ccsr_writel(pcie, GPEX_CFG_READY, PCIE_CONFIG_READY); +@@ -548,7 +567,7 @@ static int ls_pcie_g4_probe(struct udevice *dev) + val |= PPIO_EN; + ccsr_writel(pcie, PAB_PEX_PIO_CTRL(0), val); + +- if (!ls_pcie_g4_link_up(pcie)) { ++ if (!ls_pcie_g4_wait_for_link(pcie)) { + /* Let the user know there's no PCIe link */ + printf(": no link\n"); + return 0; +-- +2.35.3 + diff --git a/board/solidrun/lx2160acex7/patches/uboot/0003-pci-ls_pcie-Wait-100ms-for-Link-Up-in-ls_pcie_probe.patch b/board/solidrun/lx2160acex7/patches/uboot/0003-pci-ls_pcie-Wait-100ms-for-Link-Up-in-ls_pcie_probe.patch new file mode 100644 index 000000000000..074c73500ca5 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/uboot/0003-pci-ls_pcie-Wait-100ms-for-Link-Up-in-ls_pcie_probe.patch @@ -0,0 +1,64 @@ +From 1abb4b0ba3dd29f3b52c839cc3d2844e8bf78790 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sun, 14 Apr 2024 16:45:42 +0200 +Subject: [PATCH 3/3] pci: ls_pcie: Wait 100ms for Link Up in ls_pcie_probe + +PCI Link-up can be delayed especially with pci bridges or fpga starting +up slowly. + +Add a 100ms delay during probe polling for link-up. + +Signed-off-by: Josua Mayer +--- + drivers/pci/pcie_layerscape_rc.c | 21 ++++++++++++++++++++- + 1 file changed, 20 insertions(+), 1 deletion(-) + +diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c +index 17969e2f236..c78b8efd521 100644 +--- a/drivers/pci/pcie_layerscape_rc.c ++++ b/drivers/pci/pcie_layerscape_rc.c +@@ -19,6 +19,9 @@ + #endif + #include "pcie_layerscape.h" + ++#define LINK_WAIT_RETRIES 100 ++#define LINK_WAIT_TIMEOUT 1000 ++ + DECLARE_GLOBAL_DATA_PTR; + + struct ls_pcie_drvdata { +@@ -27,6 +30,22 @@ struct ls_pcie_drvdata { + bool big_endian; + }; + ++static int ls_pcie_wait_for_link(struct ls_pcie *pcie) ++{ ++ int retries; ++ ++ /* check if the link is up or not */ ++ for (retries = 0; retries < LINK_WAIT_RETRIES; retries++) { ++ if (ls_pcie_link_up(pcie)) { ++ return 1; ++ } ++ ++ udelay(LINK_WAIT_TIMEOUT); ++ } ++ ++ return 0; ++} ++ + static void ls_pcie_cfg0_set_busdev(struct ls_pcie_rc *pcie_rc, u32 busdev) + { + struct ls_pcie *pcie = pcie_rc->pcie; +@@ -375,7 +394,7 @@ static int ls_pcie_probe(struct udevice *dev) + "Root Complex"); + ls_pcie_setup_ctrl(pcie_rc); + +- if (!ls_pcie_link_up(pcie)) { ++ if (!ls_pcie_wait_for_link(pcie)) { + /* Let the user know there's no PCIe link */ + printf(": no link\n"); + return 0; +-- +2.35.3 + diff --git a/board/solidrun/lx2160acex7/patches/uboot/0004-fsl-lsch3-update-calculation-of-ddr-clock-rate-to-in.patch b/board/solidrun/lx2160acex7/patches/uboot/0004-fsl-lsch3-update-calculation-of-ddr-clock-rate-to-in.patch new file mode 100644 index 000000000000..a961bd77d7f0 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/uboot/0004-fsl-lsch3-update-calculation-of-ddr-clock-rate-to-in.patch @@ -0,0 +1,63 @@ +From 7320dd540f97a56f7f7cfcbd0dc2e9fae393a8a1 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Tue, 8 Oct 2024 13:29:36 +0200 +Subject: [PATCH] fsl-lsch3: update calculation of ddr clock rate to include + divider + +DDR clock is passes through a divider and a multiplier - and is then +again doubled once by the phy and once by the controller. +The doubling was previously hidden by divider default value of 4. + +Take into account the divider value per MEM_PLL_CFG when calculating ddr +bus frequency, and multiply the result by 4. + +Signed-off-by: Josua Mayer +--- + arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 8 ++++++++ + arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 ++++ + 2 files changed, 12 insertions(+) + +diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +index 1c04a5b5b7e..29a786bf26c 100644 +--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c ++++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +@@ -97,11 +97,19 @@ void get_sys_info(struct sys_info *sys_info) + sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> + FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & + FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; ++ sys_info->freq_ddrbus /= ((gur_in32(&gur->rcwsr[0]) >> ++ FSL_CHASSIS3_RCWSR0_MEM_PLL_CFG_SHIFT) & ++ FSL_CHASSIS3_RCWSR0_MEM_PLL_CFG_MASK) + 1; ++ /* ddr clock is doubled at phy, then doubled again controller */ ++ sys_info->freq_ddrbus *= 4; + #ifdef CONFIG_SYS_FSL_HAS_DP_DDR + if (soc_has_dp_ddr()) { + sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >> + FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) & + FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK; ++ sys_info->freq_ddrbus2 /= ((gur_in32(&gur->rcwsr[0]) >> ++ FSL_CHASSIS3_RCWSR0_MEM2_PLL_CFG_SHIFT) & ++ FSL_CHASSIS3_RCWSR0_MEM2_PLL_CFG_MASK) + 1; + } else { + sys_info->freq_ddrbus2 = 0; + } +diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +index 863618a5f3d..ec9505fb6f1 100644 +--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h ++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +@@ -374,8 +374,12 @@ struct ccsr_gur { + + #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2 + #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f ++#define FSL_CHASSIS3_RCWSR0_MEM_PLL_CFG_SHIFT 8 ++#define FSL_CHASSIS3_RCWSR0_MEM_PLL_CFG_MASK 0x3 + #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10 + #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f ++#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_CFG_SHIFT 16 ++#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_CFG_MASK 0x3 + #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 + #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f + +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/uboot/0005-armv8-lx2160a-enable-workaround-for-SPI-erratum-A-05.patch b/board/solidrun/lx2160acex7/patches/uboot/0005-armv8-lx2160a-enable-workaround-for-SPI-erratum-A-05.patch new file mode 100644 index 000000000000..d6c9de0d6d3d --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/uboot/0005-armv8-lx2160a-enable-workaround-for-SPI-erratum-A-05.patch @@ -0,0 +1,102 @@ +From f107c333541cdb1dd35fdd056c4f72d1e23f610a Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Thu, 24 Oct 2024 16:17:49 +0200 +Subject: [PATCH] armv8: lx2160a: enable workaround for SPI erratum A-050752 + +When RCW is loaded from SDHC1, chip-selects signals for SPI3 are always +low and not usable. + +Implement workaround for erratum A-050752 by clearing rcw source values +in dynamic configuration register and masking HRESET_B. + +Signed-off-by: Josua Mayer +--- + arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 ++++ + arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 +++ + arch/arm/cpu/armv8/fsl-layerscape/soc.c | 18 ++++++++++++++++++ + arch/arm/include/asm/arch-fsl-layerscape/soc.h | 4 ++++ + 4 files changed, 29 insertions(+) + +diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +index 9bb870dcd8c..ad7bea8e44e 100644 +--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig ++++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +@@ -296,6 +296,7 @@ config ARCH_LX2160A + select SYS_FSL_EC2 + select SYS_FSL_ERRATUM_A050204 + select SYS_FSL_ERRATUM_A011334 ++ select SYS_FSL_ERRATUM_A050752 + select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND + select SYS_FSL_HAS_RGMII + select SYS_FSL_HAS_SEC +@@ -671,6 +672,9 @@ config SYS_FSL_ERRATUM_A009660 + config SYS_FSL_ERRATUM_A050382 + bool + ++config SYS_FSL_ERRATUM_A050752 ++ bool ++ + config SYS_FSL_HAS_RGMII + bool + depends on SYS_FSL_EC1 || SYS_FSL_EC2 +diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +index 16650526e7d..eea3bd7c88f 100644 +--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c ++++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +@@ -1133,6 +1133,9 @@ int arch_early_init_r(void) + #endif + #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR) + erratum_a009942_check_cpo(); ++#endif ++#ifdef CONFIG_SYS_FSL_ERRATUM_A050752 ++ erratum_a050752(); + #endif + if (check_psci()) { + debug("PSCI: PSCI does not exist.\n"); +diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c +index d3a5cfaac19..bfe7c7f5d9f 100644 +--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c ++++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c +@@ -315,6 +315,24 @@ void erratum_a009635(void) + writel(val | 0x80000000, EPU_EPGCR); + } + #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */ ++#ifdef CONFIG_SYS_FSL_ERRATUM_A050752 ++#define RESET_BASE 0x01e60000 ++#define RESET_CCSR 0 ++#define RESET_CCSR_HRESET_B_DIS BIT(25) ++ ++void erratum_a050752(void) ++{ ++ u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; ++ u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; ++ u32 __iomem *reset_ccsr = (u32 __iomem *)RESET_BASE; ++ u32 val; ++ ++ val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); ++ val &= ~DCFG_PORSR1_RCW_SRC; ++ out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val); ++ out_le32(reset_ccsr + RESET_CCSR / 4, RESET_CCSR_HRESET_B_DIS); ++} ++#endif /* CONFIG_SYS_FSL_ERRATUM_A050752 */ + + static void erratum_rcw_src(void) + { +diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h +index bd41df1be44..3e7c5b0e724 100644 +--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h ++++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h +@@ -131,6 +131,10 @@ void erratum_a009635(void); + void erratum_a010315(void); + #endif + ++#ifdef CONFIG_SYS_FSL_ERRATUM_A050752 ++void erratum_a050752(void); ++#endif ++ + bool soc_has_dp_ddr(void); + bool soc_has_aiop(void); + +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/uboot/0006-configs-lx2160-cex7-enable-additional-drivers.patch b/board/solidrun/lx2160acex7/patches/uboot/0006-configs-lx2160-cex7-enable-additional-drivers.patch new file mode 100644 index 000000000000..46b4cab7e686 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/uboot/0006-configs-lx2160-cex7-enable-additional-drivers.patch @@ -0,0 +1,96 @@ +From 9f64e0b7828602683f618793e795350128f4760b Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sat, 26 Oct 2024 13:50:39 +0200 +Subject: [PATCH] configs: lx2160-cex7: enable additional drivers + +--- + configs/lx2160acex7_tfa_SECURE_BOOT_defconfig | 11 +++++++++++ + configs/lx2160acex7_tfa_defconfig | 3 +++ + 2 files changed, 14 insertions(+) + +diff --git a/configs/lx2160acex7_tfa_SECURE_BOOT_defconfig b/configs/lx2160acex7_tfa_SECURE_BOOT_defconfig +index 12f236aad06..d55bdb24a4b 100644 +--- a/configs/lx2160acex7_tfa_SECURE_BOOT_defconfig ++++ b/configs/lx2160acex7_tfa_SECURE_BOOT_defconfig +@@ -35,8 +35,10 @@ CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y ++CONFIG_CMD_OPTEE_RPMB=y + CONFIG_CMD_PCI=y + CONFIG_CMD_USB=y ++CONFIG_CMD_WDT=y + CONFIG_CMD_CACHE=y + CONFIG_OF_CONTROL=y + CONFIG_ENV_OVERWRITE=y +@@ -44,6 +46,7 @@ CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_DM=y + CONFIG_SATA=y + CONFIG_SATA_CEVA=y ++CONFIG_FSL_CAAM=y + CONFIG_DYNAMIC_DDR_CLK_FREQ=y + CONFIG_DDR_ECC=y + CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +@@ -51,12 +54,15 @@ CONFIG_MPC8XXX_GPIO=y + CONFIG_DM_I2C=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + CONFIG_SYS_I2C_EEPROM_ADDR=0x57 ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_HS400_SUPPORT=y + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_STMICRO=y + CONFIG_SPI_FLASH_MT35XU=y ++CONFIG_SPI_FLASH_WINBOND=y + # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set + CONFIG_PHYLIB=y + CONFIG_PHY_ATHEROS=y +@@ -76,11 +82,16 @@ CONFIG_DM_SERIAL=y + CONFIG_PL01X_SERIAL=y + CONFIG_SPI=y + CONFIG_DM_SPI=y ++CONFIG_FSL_DSPI=y + CONFIG_NXP_FSPI=y ++CONFIG_TEE=y ++CONFIG_OPTEE=y + CONFIG_USB=y + CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_DWC3=y + CONFIG_RSA=y + CONFIG_SPL_RSA=y + CONFIG_RSA_SOFTWARE_EXP=y ++CONFIG_WDT=y ++CONFIG_WDT_SBSA=y + CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig +index 9f24e12a85d..8fd603cb87e 100644 +--- a/configs/lx2160acex7_tfa_defconfig ++++ b/configs/lx2160acex7_tfa_defconfig +@@ -60,12 +60,14 @@ CONFIG_DM_I2C=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_HS400_SUPPORT=y + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_STMICRO=y + CONFIG_SPI_FLASH_MT35XU=y ++CONFIG_SPI_FLASH_WINBOND=y + # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set + CONFIG_PHYLIB=y + CONFIG_PHY_ATHEROS=y +@@ -85,6 +87,7 @@ CONFIG_DM_SERIAL=y + CONFIG_PL01X_SERIAL=y + CONFIG_SPI=y + CONFIG_DM_SPI=y ++CONFIG_FSL_DSPI=y + CONFIG_NXP_FSPI=y + CONFIG_TEE=y + CONFIG_OPTEE=y +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/uboot/0007-cmd-tlv_eeprom-don-t-fail-boot-when-reading-eeprom-f.patch b/board/solidrun/lx2160acex7/patches/uboot/0007-cmd-tlv_eeprom-don-t-fail-boot-when-reading-eeprom-f.patch new file mode 100644 index 000000000000..d84ea44e1688 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/uboot/0007-cmd-tlv_eeprom-don-t-fail-boot-when-reading-eeprom-f.patch @@ -0,0 +1,32 @@ +From fff14a56662e7f4ff86cdb5452e5c1b1e35f28bd Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sat, 2 Nov 2024 16:31:01 +0100 +Subject: [PATCH 07/10] cmd: tlv_eeprom: don't fail boot when reading eeprom + fails + +When u-boot calls mac_read_from_eeprom during init an error return code +will fail the boot before reaching u-boot shell. + +Return success error code even on error, mac addresses are not critical. + +Signed-off-by: Josua Mayer +--- + cmd/tlv_eeprom.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c +index bf8d453dc5b..cbc11ebf421 100644 +--- a/cmd/tlv_eeprom.c ++++ b/cmd/tlv_eeprom.c +@@ -1023,7 +1023,7 @@ int mac_read_from_eeprom(void) + + if (read_eeprom(eeprom)) { + printf("Read failed.\n"); +- return -1; ++ return 0; + } + + maccount = 1; +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/uboot/0008-board-solidrun-lx2160-cex7-fixup-u-boot-dts-dpmac-by.patch b/board/solidrun/lx2160acex7/patches/uboot/0008-board-solidrun-lx2160-cex7-fixup-u-boot-dts-dpmac-by.patch new file mode 100644 index 000000000000..219f6eaf559d --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/uboot/0008-board-solidrun-lx2160-cex7-fixup-u-boot-dts-dpmac-by.patch @@ -0,0 +1,389 @@ +From 23e2133cf0e5bdd8d2556fe0fe63f5b9ab534e65 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sat, 2 Nov 2024 17:55:53 +0100 +Subject: [PATCH 08/10] board: solidrun: lx2160-cex7: fixup u-boot dts dpmac by + serdes protocol + +LX2160A network interface availability and speed depend on serdes +protocol selected in RCW. Creating device-tree for every possible +combination would be cumbersome and hard to maintain. + +U-Boot dpaa2 driver does not reconfigure network interfaces but leaves +them as brought up by MC firmware, based on serdes protocol. +At the same time, u-boot expects the dt phy-mode property to match +actual interface protocol. + +Fixup u-boot fdt during board_fix_fdt, setting status property and +phy-mode according to default protocol for the running serdes protocol. + +This allows with the same u-boot build and internal device-tree to +enable all available network interfaces as dictatd by a particular RCW. + +Signed-off-by: Josua Mayer +--- + board/solidrun/lx2160acex7/eth_lx2160acex7.c | 312 +++++++++++++++++++ + board/solidrun/lx2160acex7/lx2160a.c | 4 + + 2 files changed, 316 insertions(+) + +diff --git a/board/solidrun/lx2160acex7/eth_lx2160acex7.c b/board/solidrun/lx2160acex7/eth_lx2160acex7.c +index d2c68d34243..63aa6610a02 100644 +--- a/board/solidrun/lx2160acex7/eth_lx2160acex7.c ++++ b/board/solidrun/lx2160acex7/eth_lx2160acex7.c +@@ -12,6 +12,8 @@ + #include + #include + #include ++#include ++#include + + DECLARE_GLOBAL_DATA_PTR; + +@@ -76,13 +78,323 @@ void reset_phy(void) + } + #endif /* CONFIG_RESET_PHY_R */ + ++#ifndef CONFIG_CMD_TLV_EEPROM + int mac_read_from_eeprom(void) + { + return 0; + } ++#endif + + int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) + { + puts("Not implemented.\n"); + return CMD_RET_FAILURE; + } ++ ++static void dpmac_set_phymode(void *fdt, unsigned int id, const char *mode) { ++ char path[34] = {}; ++ int node; ++ ++ snprintf(path, sizeof(path), "/fsl-mc@80c000000/dpmacs/dpmac@%x", id); ++ node = fdt_path_offset(fdt, path); ++ fdt_delprop(fdt, node, "phy-mode"); ++ do_fixup_by_path_string(fdt, path, "phy-connection-type", mode); ++ do_fixup_by_path_string(fdt, path, "status", "okay"); ++} ++ ++/* ++ * Fixup dpmac phy-modes by serdes protocol to fix ethernet driver probe ++ */ ++void board_fix_fdt_eth(void *fdt) { ++ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); ++ u32 is_lx2162 = get_svr() & 0x800; ++ u32 srds_s1, srds_s2; ++ ++ srds_s1 = in_le32(&gur->rcwsr[28]) & ++ FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; ++ srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; ++ ++ srds_s2 = in_le32(&gur->rcwsr[28]) & ++ FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; ++ srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; ++ ++ /* allocate space in case properties must be added */ ++ fdt_increase_size(fdt, 256); ++ ++ switch (srds_s1) { ++ case 0: ++ case 1: ++ break; ++ case 2: ++ /* 3, 4, 5, 6 = sgmii */ ++ dpmac_set_phymode(fdt, 3, "sgmii"); ++ dpmac_set_phymode(fdt, 4, "sgmii"); ++ dpmac_set_phymode(fdt, 5, "sgmii"); ++ dpmac_set_phymode(fdt, 6, "sgmii"); ++ break; ++ case 3: ++ /* 3, 4, 5, 6 = xgmii */ ++ dpmac_set_phymode(fdt, 3, "xgmii"); ++ dpmac_set_phymode(fdt, 4, "xgmii"); ++ dpmac_set_phymode(fdt, 5, "xgmii"); ++ dpmac_set_phymode(fdt, 6, "xgmii"); ++ break; ++ case 4: ++ /* 3, 4, 5, 6, 7, 8, 9, 10 = sgmii */ ++ dpmac_set_phymode(fdt, 3, "sgmii"); ++ dpmac_set_phymode(fdt, 4, "sgmii"); ++ dpmac_set_phymode(fdt, 5, "sgmii"); ++ dpmac_set_phymode(fdt, 6, "sgmii"); ++ if (is_lx2162) ++ break; ++ dpmac_set_phymode(fdt, 7, "sgmii"); ++ dpmac_set_phymode(fdt, 8, "sgmii"); ++ dpmac_set_phymode(fdt, 9, "sgmii"); ++ dpmac_set_phymode(fdt, 10, "sgmii"); ++ break; ++ case 5: ++ /* 7, 8, 9, 10 = xgmii */ ++ if (is_lx2162) ++ break; ++ dpmac_set_phymode(fdt, 7, "xgmii"); ++ dpmac_set_phymode(fdt, 8, "xgmii"); ++ dpmac_set_phymode(fdt, 9, "xgmii"); ++ dpmac_set_phymode(fdt, 10, "xgmii"); ++ break; ++ case 6: ++ /* 3, 4 = xgmii; 5, 6, 7, 8, 9, 10 = sgmii */ ++ dpmac_set_phymode(fdt, 3, "xgmii"); ++ dpmac_set_phymode(fdt, 4, "xgmii"); ++ dpmac_set_phymode(fdt, 5, "sgmii"); ++ dpmac_set_phymode(fdt, 6, "sgmii"); ++ if (is_lx2162) ++ break; ++ dpmac_set_phymode(fdt, 7, "sgmii"); ++ dpmac_set_phymode(fdt, 8, "sgmii"); ++ dpmac_set_phymode(fdt, 9, "sgmii"); ++ dpmac_set_phymode(fdt, 10, "sgmii"); ++ break; ++ case 7: ++ /* 3, 4, 5, 6 = xgmii; 7, 8, 9, 10 = sgmii */ ++ dpmac_set_phymode(fdt, 3, "xgmii"); ++ dpmac_set_phymode(fdt, 4, "xgmii"); ++ dpmac_set_phymode(fdt, 5, "xgmii"); ++ dpmac_set_phymode(fdt, 6, "xgmii"); ++ if (is_lx2162) ++ break; ++ dpmac_set_phymode(fdt, 7, "sgmii"); ++ dpmac_set_phymode(fdt, 8, "sgmii"); ++ dpmac_set_phymode(fdt, 9, "sgmii"); ++ dpmac_set_phymode(fdt, 10, "sgmii"); ++ break; ++ case 8: ++ /* 3, 4, 5, 6, 7, 8, 9, 10 = xgmii */ ++ dpmac_set_phymode(fdt, 3, "xgmii"); ++ dpmac_set_phymode(fdt, 4, "xgmii"); ++ dpmac_set_phymode(fdt, 5, "xgmii"); ++ dpmac_set_phymode(fdt, 6, "xgmii"); ++ if (is_lx2162) ++ break; ++ dpmac_set_phymode(fdt, 7, "xgmii"); ++ dpmac_set_phymode(fdt, 8, "xgmii"); ++ dpmac_set_phymode(fdt, 9, "xgmii"); ++ dpmac_set_phymode(fdt, 10, "xgmii"); ++ break; ++ case 9: ++ /* 4, 5, 6, 8, 9, 10 = sgmii */ ++ dpmac_set_phymode(fdt, 4, "sgmii"); ++ dpmac_set_phymode(fdt, 5, "sgmii"); ++ dpmac_set_phymode(fdt, 6, "sgmii"); ++ if (is_lx2162) ++ break; ++ dpmac_set_phymode(fdt, 8, "sgmii"); ++ dpmac_set_phymode(fdt, 9, "sgmii"); ++ dpmac_set_phymode(fdt, 10, "sgmii"); ++ break; ++ case 10: ++ /* 4, 5, 6, 8, 9, 10 = xgmii */ ++ dpmac_set_phymode(fdt, 4, "xgmii"); ++ dpmac_set_phymode(fdt, 5, "xgmii"); ++ dpmac_set_phymode(fdt, 6, "xgmii"); ++ if (is_lx2162) ++ break; ++ dpmac_set_phymode(fdt, 8, "xgmii"); ++ dpmac_set_phymode(fdt, 9, "xgmii"); ++ dpmac_set_phymode(fdt, 10, "xgmii"); ++ break; ++ case 11: ++ /* 5, 6, 9, 10 = sgmii */ ++ dpmac_set_phymode(fdt, 5, "sgmii"); ++ dpmac_set_phymode(fdt, 6, "sgmii"); ++ if (is_lx2162) ++ break; ++ dpmac_set_phymode(fdt, 9, "sgmii"); ++ dpmac_set_phymode(fdt, 10, "sgmii"); ++ break; ++ case 12: ++ /* 9, 10 = sgmii */ ++ if (is_lx2162) ++ break; ++ dpmac_set_phymode(fdt, 9, "sgmii"); ++ dpmac_set_phymode(fdt, 10, "sgmii"); ++ break; ++ case 13: ++ /* 1, 2 = caui4 */ ++ dpmac_set_phymode(fdt, 1, "caui4"); ++ if (is_lx2162) ++ break; ++ dpmac_set_phymode(fdt, 2, "caui4"); ++ break; ++ case 14: ++ /* 1 = caui4 */ ++ dpmac_set_phymode(fdt, 1, "caui4"); ++ break; ++ case 15: ++ /* 1, 2 = caui2 */ ++ dpmac_set_phymode(fdt, 1, "caui2"); ++ dpmac_set_phymode(fdt, 2, "caui2"); ++ break; ++ case 16: ++ /* 1 = caui2; 5, 6 = 25g-aui */ ++ dpmac_set_phymode(fdt, 1, "caui2"); ++ dpmac_set_phymode(fdt, 5, "25g-aui"); ++ dpmac_set_phymode(fdt, 6, "25g-aui"); ++ break; ++ case 17: ++ /* 3, 4, 5, 6 = 25g-aui */ ++ dpmac_set_phymode(fdt, 3, "25g-aui"); ++ dpmac_set_phymode(fdt, 4, "25g-aui"); ++ dpmac_set_phymode(fdt, 5, "25g-aui"); ++ dpmac_set_phymode(fdt, 6, "25g-aui"); ++ break; ++ case 18: ++ /* 3, 4, 7, 8, 9, 10 = xgmii; 5, 6 = 25g-aui */ ++ dpmac_set_phymode(fdt, 3, "xgmii"); ++ dpmac_set_phymode(fdt, 4, "xgmii"); ++ dpmac_set_phymode(fdt, 5, "25g-aui"); ++ dpmac_set_phymode(fdt, 6, "25g-aui"); ++ if (is_lx2162) ++ break; ++ dpmac_set_phymode(fdt, 7, "xgmii"); ++ dpmac_set_phymode(fdt, 8, "xgmii"); ++ dpmac_set_phymode(fdt, 9, "xgmii"); ++ dpmac_set_phymode(fdt, 10, "xgmii"); ++ break; ++ case 19: ++ /* 2 = xlaui4; 3, 4 = xgmii; 5, 6 = 25g-aui */ ++ dpmac_set_phymode(fdt, 3, "xgmii"); ++ dpmac_set_phymode(fdt, 4, "xgmii"); ++ dpmac_set_phymode(fdt, 5, "25g-aui"); ++ dpmac_set_phymode(fdt, 6, "25g-aui"); ++ if (is_lx2162) ++ break; ++ dpmac_set_phymode(fdt, 2, "xlaui4"); ++ break; ++ case 20: ++ /* 1, 2 = xlaui4 */ ++ dpmac_set_phymode(fdt, 1, "xlaui4"); ++ if (is_lx2162) ++ break; ++ dpmac_set_phymode(fdt, 2, "xlaui4"); ++ break; ++ case 21: ++ /* 3, 4, 5, 6, 9, 10 = 25g-aui */ ++ dpmac_set_phymode(fdt, 3, "25g-aui"); ++ dpmac_set_phymode(fdt, 4, "25g-aui"); ++ dpmac_set_phymode(fdt, 5, "25g-aui"); ++ dpmac_set_phymode(fdt, 6, "25g-aui"); ++ if (is_lx2162) ++ break; ++ dpmac_set_phymode(fdt, 9, "25g-aui"); ++ dpmac_set_phymode(fdt, 10, "25g-aui"); ++ break; ++ case 22: ++ /* 3, 4, 5, 6, 9, 10 = xgmii */ ++ dpmac_set_phymode(fdt, 3, "xgmii"); ++ dpmac_set_phymode(fdt, 4, "xgmii"); ++ dpmac_set_phymode(fdt, 5, "xgmii"); ++ dpmac_set_phymode(fdt, 6, "xgmii"); ++ if (is_lx2162) ++ break; ++ dpmac_set_phymode(fdt, 9, "xgmii"); ++ dpmac_set_phymode(fdt, 10, "xgmii"); ++ break; ++ } ++ ++ switch (srds_s2) { ++ case 0: ++ case 1: ++ case 2: ++ case 3: ++ case 4: ++ case 5: ++ break; ++ case 6: ++ /* 13, 14 = xgmii; 15, 16 = sgmii */ ++ dpmac_set_phymode(fdt, 13, "xgmii"); ++ dpmac_set_phymode(fdt, 14, "xgmii"); ++ dpmac_set_phymode(fdt, 15, "sgmii"); ++ dpmac_set_phymode(fdt, 16, "sgmii"); ++ break; ++ case 7: ++ /* 12, 16, 17, 18 = sgmii; 13, 14 = xgmii */ ++ dpmac_set_phymode(fdt, 12, "sgmii"); ++ dpmac_set_phymode(fdt, 13, "xgmii"); ++ dpmac_set_phymode(fdt, 14, "xgmii"); ++ dpmac_set_phymode(fdt, 16, "sgmii"); ++ dpmac_set_phymode(fdt, 17, "sgmii"); ++ dpmac_set_phymode(fdt, 18, "sgmii"); ++ break; ++ case 8: ++ /* 13, 14 = xgmii */ ++ dpmac_set_phymode(fdt, 13, "xgmii"); ++ dpmac_set_phymode(fdt, 14, "xgmii"); ++ break; ++ case 9: ++ /* 11, 12, 13, 14, 15, 16, 17, 18 = sgmii */ ++ dpmac_set_phymode(fdt, 11, "sgmii"); ++ dpmac_set_phymode(fdt, 12, "sgmii"); ++ dpmac_set_phymode(fdt, 13, "sgmii"); ++ dpmac_set_phymode(fdt, 14, "sgmii"); ++ dpmac_set_phymode(fdt, 15, "sgmii"); ++ dpmac_set_phymode(fdt, 16, "sgmii"); ++ dpmac_set_phymode(fdt, 17, "sgmii"); ++ dpmac_set_phymode(fdt, 18, "sgmii"); ++ break; ++ case 10: ++ /* 11, 12, 17, 18 = sgmii */ ++ dpmac_set_phymode(fdt, 11, "sgmii"); ++ dpmac_set_phymode(fdt, 12, "sgmii"); ++ dpmac_set_phymode(fdt, 17, "sgmii"); ++ dpmac_set_phymode(fdt, 18, "sgmii"); ++ break; ++ case 11: ++ /* 12, 13, 14, 16, 17, 18 = sgmii */ ++ dpmac_set_phymode(fdt, 12, "sgmii"); ++ dpmac_set_phymode(fdt, 13, "sgmii"); ++ dpmac_set_phymode(fdt, 14, "sgmii"); ++ dpmac_set_phymode(fdt, 16, "sgmii"); ++ dpmac_set_phymode(fdt, 17, "sgmii"); ++ dpmac_set_phymode(fdt, 18, "sgmii"); ++ break; ++ case 12: ++ /* 11, 12, 17, 18 = sgmii */ ++ dpmac_set_phymode(fdt, 11, "sgmii"); ++ dpmac_set_phymode(fdt, 12, "sgmii"); ++ dpmac_set_phymode(fdt, 17, "sgmii"); ++ dpmac_set_phymode(fdt, 18, "sgmii"); ++ break; ++ case 13: ++ /* 13, 14 = sgmii */ ++ dpmac_set_phymode(fdt, 13, "sgmii"); ++ dpmac_set_phymode(fdt, 14, "sgmii"); ++ break; ++ case 14: ++ /* 13, 14, 17, 18 = sgmii */ ++ dpmac_set_phymode(fdt, 13, "sgmii"); ++ dpmac_set_phymode(fdt, 14, "sgmii"); ++ dpmac_set_phymode(fdt, 17, "sgmii"); ++ dpmac_set_phymode(fdt, 18, "sgmii"); ++ break; ++ } ++} +diff --git a/board/solidrun/lx2160acex7/lx2160a.c b/board/solidrun/lx2160acex7/lx2160a.c +index 08fa6070672..af0a071488a 100644 +--- a/board/solidrun/lx2160acex7/lx2160a.c ++++ b/board/solidrun/lx2160acex7/lx2160a.c +@@ -65,6 +65,8 @@ int board_early_init_f(void) + } + + #ifdef CONFIG_OF_BOARD_FIXUP ++void board_fix_fdt_eth(void *fdt); ++ + int board_fix_fdt(void *fdt) + { + char *reg_names, *reg_name; +@@ -78,6 +80,8 @@ int board_fix_fdt(void *fdt) + }; + int off = -1, i = 0; + ++ board_fix_fdt_eth(fdt); ++ + if (IS_SVR_REV(get_svr(), 1, 0)) + return 0; + +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/uboot/0009-board-solidrun-lx2160acex7-enable-reading-tlv-eeprom.patch b/board/solidrun/lx2160acex7/patches/uboot/0009-board-solidrun-lx2160acex7-enable-reading-tlv-eeprom.patch new file mode 100644 index 000000000000..86f89a23f2d2 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/uboot/0009-board-solidrun-lx2160acex7-enable-reading-tlv-eeprom.patch @@ -0,0 +1,40 @@ +From 402f33f4a31ebfa8b4a03adee2b1940878cadc74 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sat, 2 Nov 2024 18:30:53 +0100 +Subject: [PATCH 09/10] board: solidrun: lx2160acex7: enable reading tlv eeprom + mac addresses + +Enable tlv eeprom support in u-boot configuration to execute +mac_read_from_eeprom and populate network interface mac addresses from +tlv data if available. + +Signed-off-by: Josua Mayer +--- + configs/lx2160acex7_tfa_defconfig | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig +index 8fd603cb87e..803ddb376f4 100644 +--- a/configs/lx2160acex7_tfa_defconfig ++++ b/configs/lx2160acex7_tfa_defconfig +@@ -28,6 +28,7 @@ CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" + CONFIG_DEFAULT_FDT_FILE="freescale/fsl-lx2160a-clearfog-cx.dtb" + CONFIG_MISC_INIT_R=y ++CONFIG_CMD_TLV_EEPROM=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y + CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +@@ -58,6 +59,9 @@ CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_MPC8XXX_GPIO=y + CONFIG_DM_I2C=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_I2C_MUX=y ++CONFIG_I2C_MUX_PCA954x=y ++CONFIG_I2C_EEPROM=y + CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_SUPPORT_EMMC_RPMB=y + CONFIG_SUPPORT_EMMC_BOOT=y +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/uboot/0010-board-solidrun-lx2160acex7-disable-second-usb-on-lx2.patch b/board/solidrun/lx2160acex7/patches/uboot/0010-board-solidrun-lx2160acex7-disable-second-usb-on-lx2.patch new file mode 100644 index 000000000000..6d2750c51792 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/uboot/0010-board-solidrun-lx2160acex7-disable-second-usb-on-lx2.patch @@ -0,0 +1,32 @@ +From 86421a6f1f41ea90124e4de2f8b73e43049bc1d4 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sat, 2 Nov 2024 19:52:31 +0100 +Subject: [PATCH 10/10] board: solidrun: lx2160acex7: disable second usb on + lx2162 + +LX2162 only has single USB controller, disable the second one from +board_fix_fdt. + +Signed-off-by: Josua Mayer +--- + board/solidrun/lx2160acex7/lx2160a.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/board/solidrun/lx2160acex7/lx2160a.c b/board/solidrun/lx2160acex7/lx2160a.c +index af0a071488a..e0a9e6c51eb 100644 +--- a/board/solidrun/lx2160acex7/lx2160a.c ++++ b/board/solidrun/lx2160acex7/lx2160a.c +@@ -79,6 +79,10 @@ int board_fix_fdt(void *fdt) + { "pf_ctrl", "ctrl" } + }; + int off = -1, i = 0; ++ u32 is_lx2162 = get_svr() & 0x800; ++ ++ if (is_lx2162) ++ do_fixup_by_path_string(fdt, "/usb3@3110000", "status", "disabled"); + + board_fix_fdt_eth(fdt); + +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/uboot/0011-board-solidrun-lx2160acex7-allocate-memory-before-pa.patch b/board/solidrun/lx2160acex7/patches/uboot/0011-board-solidrun-lx2160acex7-allocate-memory-before-pa.patch new file mode 100644 index 000000000000..bc31c155ae84 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/uboot/0011-board-solidrun-lx2160acex7-allocate-memory-before-pa.patch @@ -0,0 +1,39 @@ +From bcabe078a2a27eecaa592e1f2ea640a5f1fc6cda Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Mon, 4 Nov 2024 15:16:27 +0100 +Subject: [PATCH 11/13] board: solidrun: lx2160acex7: allocate memory before + patching lx2162 fdt + +Update of second usb controller fdt node during board_fix_fdt fails due +to lack of space in the fdt. + +Explicitly allocate some extra bytes before to repair this fixup on +lx2162 som. + +Signed-off-by: Josua Mayer +--- + board/solidrun/lx2160acex7/lx2160a.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/board/solidrun/lx2160acex7/lx2160a.c b/board/solidrun/lx2160acex7/lx2160a.c +index e0a9e6c51eb..17160d13154 100644 +--- a/board/solidrun/lx2160acex7/lx2160a.c ++++ b/board/solidrun/lx2160acex7/lx2160a.c +@@ -81,8 +81,13 @@ int board_fix_fdt(void *fdt) + int off = -1, i = 0; + u32 is_lx2162 = get_svr() & 0x800; + +- if (is_lx2162) ++ if (is_lx2162) { ++ /* allocate space for changes */ ++ fdt_increase_size(fdt, 32); ++ ++ /* LX2162 does not have second USB controller, disable */ + do_fixup_by_path_string(fdt, "/usb3@3110000", "status", "disabled"); ++ } + + board_fix_fdt_eth(fdt); + +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/uboot/0012-cmd-tlv_eeprom-support-specifying-tlv-eeprom-in-DT-a.patch b/board/solidrun/lx2160acex7/patches/uboot/0012-cmd-tlv_eeprom-support-specifying-tlv-eeprom-in-DT-a.patch new file mode 100644 index 000000000000..a961cf59e85f --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/uboot/0012-cmd-tlv_eeprom-support-specifying-tlv-eeprom-in-DT-a.patch @@ -0,0 +1,58 @@ +From bc8a68d153dcfd75153d81c52531743e43f23983 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Mon, 4 Nov 2024 15:08:01 +0100 +Subject: [PATCH 12/13] cmd: tlv_eeprom: support specifying tlv eeprom in DT + alias tlv[0-255] + +Systems might have many eeproms of which only some might be used for TLV +data. +If present, use aliases tlv0, tlv1, ... for finding tlv eeproms. + +If no eeproms are found by alias, fall back to current logic if using +first eeproms in the system. + +Signed-off-by: Josua Mayer +--- + cmd/tlv_eeprom.c | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c +index cbc11ebf421..546ede2dda2 100644 +--- a/cmd/tlv_eeprom.c ++++ b/cmd/tlv_eeprom.c +@@ -899,9 +899,32 @@ static void show_tlv_devices(void) + static int find_tlv_devices(struct udevice **tlv_devices_p) + { + int ret; ++ char alias_name[7]; + int count_dev = 0; ++ int i; ++ ofnode node; + struct udevice *dev; + ++ /* find by alias */ ++ for (int i = 0; i < ARRAY_SIZE(tlv_devices_p); i++) { ++ snprintf(alias_name, sizeof(alias_name), "tlv%d", i); ++ node = ofnode_get_aliases_node(alias_name); ++ if (!ofnode_valid(node)) ++ continue; ++ ++ ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, node, &dev); ++ if (ret) { ++ debug("get device \"%s\" failed with %d\n", alias_name, ret); ++ continue; ++ } ++ ++ tlv_devices_p[i] = dev; ++ count_dev++; ++ } ++ if (count_dev) ++ return 0; ++ ++ /* fall-back: find among all eeproms */ + for (ret = uclass_first_device_check(UCLASS_I2C_EEPROM, &dev); + dev; + ret = uclass_next_device_check(&dev)) { +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/uboot/0013-board-solidrun-lx2160acex7-use-dt-alias-for-tlv-eepr.patch b/board/solidrun/lx2160acex7/patches/uboot/0013-board-solidrun-lx2160acex7-use-dt-alias-for-tlv-eepr.patch new file mode 100644 index 000000000000..5bfa6ff0337c --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/uboot/0013-board-solidrun-lx2160acex7-use-dt-alias-for-tlv-eepr.patch @@ -0,0 +1,90 @@ +From 38e36f6ceec2ecccc97369bec7e2589933001359 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Mon, 4 Nov 2024 15:12:04 +0100 +Subject: [PATCH 13/13] board: solidrun: lx2160acex7: use dt alias for tlv + eeprom + +LX2160A CEX-7 (and LX2162A SoM) have various eeproms competing for +tlv_eeprom command. + +Add tlv0 alias to u-boot dts identifying the correct eeprom. + +On LX2162 SoM the eeprom is directly on the bus without a mux. +Add dt patching logic fixing the alias and eeprom nodes when running on +lx2162 soc. + +Signed-off-by: Josua Mayer +--- + arch/arm/dts/fsl-lx2160a-cex7-u-boot.dtsi | 19 +++++++++---------- + arch/arm/dts/fsl-lx2160a-cex7.dtsi | 2 +- + board/solidrun/lx2160acex7/lx2160a.c | 5 +++++ + 3 files changed, 15 insertions(+), 11 deletions(-) + +diff --git a/arch/arm/dts/fsl-lx2160a-cex7-u-boot.dtsi b/arch/arm/dts/fsl-lx2160a-cex7-u-boot.dtsi +index 9855fcb31cc..5909af2b1b9 100644 +--- a/arch/arm/dts/fsl-lx2160a-cex7-u-boot.dtsi ++++ b/arch/arm/dts/fsl-lx2160a-cex7-u-boot.dtsi +@@ -1,6 +1,10 @@ + // SPDX-License-Identifier: GPL-2.0+ + + / { ++ aliases { ++ tlv0 = &com_eeprom; ++ }; ++ + fanctrl-override { + compatible = "solidrun,lx2160acex7-fanctrl-override"; + override-gpios = <&gpio2 2 0>; +@@ -8,15 +12,10 @@ + }; + + &i2c0 { +- u-boot,dm-pre-reloc; +- +- i2c-mux@77 { +- u-boot,dm-pre-reloc; +- +- i2c@0 { +- eeprom@57 { +- u-boot,dm-pre-reloc; +- }; +- }; ++ /* for LX2162 SoM */ ++ eeprom@57 { ++ compatible = "st,24c02", "atmel,24c02"; ++ reg = <0x57>; ++ status = "disabled"; + }; + }; +diff --git a/arch/arm/dts/fsl-lx2160a-cex7.dtsi b/arch/arm/dts/fsl-lx2160a-cex7.dtsi +index d32a52ab00a..ca87a21aaee 100644 +--- a/arch/arm/dts/fsl-lx2160a-cex7.dtsi ++++ b/arch/arm/dts/fsl-lx2160a-cex7.dtsi +@@ -80,7 +80,7 @@ + reg = <0x53>; + }; + +- eeprom@57 { ++ com_eeprom: eeprom@57 { + compatible = "atmel,24c02"; + reg = <0x57>; + }; +diff --git a/board/solidrun/lx2160acex7/lx2160a.c b/board/solidrun/lx2160acex7/lx2160a.c +index 17160d13154..dcd8d63ddf8 100644 +--- a/board/solidrun/lx2160acex7/lx2160a.c ++++ b/board/solidrun/lx2160acex7/lx2160a.c +@@ -87,6 +87,11 @@ int board_fix_fdt(void *fdt) + + /* LX2162 does not have second USB controller, disable */ + do_fixup_by_path_string(fdt, "/usb3@3110000", "status", "disabled"); ++ ++ /* LX2162 SoM has different tlv eeprom - enable and patch alias */ ++ do_fixup_by_path_string(fdt, "/aliases", "tlv0", "/i2c@2000000/eeprom@57"); ++ do_fixup_by_path_string(fdt, "/i2c@2000000/eeprom@57", "status", "okay"); ++ do_fixup_by_path_string(fdt, "/i2c@2000000/i2c-mux@77/i2c@0/eeprom@57", "status", "disabled"); + } + + board_fix_fdt_eth(fdt); +-- +2.43.0 + diff --git a/board/solidrun/lx2160acex7/patches/uboot/0014-cmd-tlv_eeprom-fix-alias-access-to-second-eeprom.patch b/board/solidrun/lx2160acex7/patches/uboot/0014-cmd-tlv_eeprom-fix-alias-access-to-second-eeprom.patch new file mode 100644 index 000000000000..58158e98cd11 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/uboot/0014-cmd-tlv_eeprom-fix-alias-access-to-second-eeprom.patch @@ -0,0 +1,32 @@ +From 413ad975194c929a09199e6a67cf3d2b2f0fb337 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Wed, 20 Nov 2024 13:43:02 +0100 +Subject: [PATCH] cmd: tlv_eeprom: fix alias access to second eeprom + +find function wrongly used ARRAY_SIZE function on a 2d pointer, always +returning 1. Thus second eeprom can not be found. + +Replace with defined constant MAX_TLV_DEVICES. + +Fixes: "cmd: tlv_eeprom: support specifying tlv eeprom in DT alias tlv[0-255]" +Signed-off-by: Josua Mayer +--- + cmd/tlv_eeprom.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c +index 546ede2dda2..881d7a8e3e6 100644 +--- a/cmd/tlv_eeprom.c ++++ b/cmd/tlv_eeprom.c +@@ -906,7 +906,7 @@ static int find_tlv_devices(struct udevice **tlv_devices_p) + struct udevice *dev; + + /* find by alias */ +- for (int i = 0; i < ARRAY_SIZE(tlv_devices_p); i++) { ++ for (int i = 0; i < MAX_TLV_DEVICES; i++) { + snprintf(alias_name, sizeof(alias_name), "tlv%d", i); + node = ofnode_get_aliases_node(alias_name); + if (!ofnode_valid(node)) +-- +2.43.0 + From patchwork Sun Dec 8 14:38:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 2019761 Return-Path: X-Original-To: incoming-buildroot@patchwork.ozlabs.org Delivered-To: patchwork-incoming-buildroot@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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dmarc=pass (p=none dis=none) header.from=gmail.com X-Mailman-Original-Authentication-Results: smtp1.osuosl.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=YwmIdvHF Subject: [Buildroot] [PATCH v2 11/11] board/freescale: get rid of common patch folder X-BeenThere: buildroot@buildroot.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: buildroot-bounces@buildroot.org Sender: "buildroot" Since commit 7cbc240ac2c3 ("configs/ls1028ardb: update to Linux 6.6"), no config file references this through BR2_GLOBAL_PATCH_DIR. Special case [PATCH] feat(build): add support for new binutils versions, which is symlinked by board/solidrun/lx2160acex7. Instead of removing this, just move it there and delete the symlink. Signed-off-by: Vladimir Oltean --- v1->v2: none ...dd-support-for-new-binutils-versions.patch | 61 ------------------ ...Makefile-Suppress-array-bounds-error.patch | 51 --------------- ...dd-support-for-new-binutils-versions.patch | 62 ++++++++++++++++++- 3 files changed, 61 insertions(+), 113 deletions(-) delete mode 100644 board/freescale/common/patches/arm-trusted-firmware/0001-feat-build-add-support-for-new-binutils-versions.patch delete mode 100644 board/freescale/common/patches/arm-trusted-firmware/0002-LF-7968-01-fix-Makefile-Suppress-array-bounds-error.patch mode change 120000 => 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0018-feat-build-add-support-for-new-binutils-versions.patch diff --git a/board/freescale/common/patches/arm-trusted-firmware/0001-feat-build-add-support-for-new-binutils-versions.patch b/board/freescale/common/patches/arm-trusted-firmware/0001-feat-build-add-support-for-new-binutils-versions.patch deleted file mode 100644 index 335c18553ac3..000000000000 --- a/board/freescale/common/patches/arm-trusted-firmware/0001-feat-build-add-support-for-new-binutils-versions.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 0f75b03c008eacb9818af3a56dc088e72a623d17 Mon Sep 17 00:00:00 2001 -From: Marco Felsch -Date: Wed, 9 Nov 2022 12:59:09 +0100 -Subject: [PATCH] feat(build): add support for new binutils versions - -Users of GNU ld (BPF) from binutils 2.39+ will observe multiple instaces -of a new warning when linking the bl*.elf in the form: - - ld.bfd: warning: stm32mp1_helper.o: missing .note.GNU-stack section implies executable stack - ld.bfd: NOTE: This behaviour is deprecated and will be removed in a future version of the linker - ld.bfd: warning: bl2.elf has a LOAD segment with RWX permissions - ld.bfd: warning: bl32.elf has a LOAD segment with RWX permissions - -These new warnings are enbaled by default to secure elf binaries: - - https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=ba951afb99912da01a6e8434126b8fac7aa75107 - - https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=0d38576a34ec64a1b4500c9277a8e9d0f07e6774 - -Fix it in a similar way to what the Linux kernel does, see: -https://lore.kernel.org/all/20220810222442.2296651-1-ndesaulniers@google.com/ - -Following the reasoning there, we set "-z noexecstack" for all linkers -(although LLVM's LLD defaults to it) and optional add ---no-warn-rwx-segments since this a ld.bfd related. - -Signed-off-by: Marco Felsch -Signed-off-by: Robert Schwebel -Change-Id: I9430f5fa5036ca88da46cd3b945754d62616b617 -Signed-off-by: Heiko Thiery -Upstream: https://github.com/ARM-software/arm-trusted-firmware/commit/1f49db5f25cdd4e43825c9bcc0575070b80f628c ---- - Makefile | 7 ++++++- - 1 file changed, 6 insertions(+), 1 deletion(-) - -diff --git a/Makefile b/Makefile -index 1ddb7b844..470956b19 100644 ---- a/Makefile -+++ b/Makefile -@@ -416,6 +416,8 @@ endif - - GCC_V_OUTPUT := $(shell $(CC) -v 2>&1) - -+TF_LDFLAGS += -z noexecstack -+ - # LD = armlink - ifneq ($(findstring armlink,$(notdir $(LD))),) - TF_LDFLAGS += --diag_error=warning --lto_level=O1 -@@ -442,7 +444,10 @@ TF_LDFLAGS += $(subst --,-Xlinker --,$(TF_LDFLAGS_$(ARCH))) - - # LD = gcc-ld (ld) or llvm-ld (ld.lld) or other - else --TF_LDFLAGS += --fatal-warnings -O1 -+# With ld.bfd version 2.39 and newer new warnings are added. Skip those since we -+# are not loaded by a elf loader. -+TF_LDFLAGS += $(call ld_option, --no-warn-rwx-segments) -+TF_LDFLAGS += -O1 - TF_LDFLAGS += --gc-sections - # ld.lld doesn't recognize the errata flags, - # therefore don't add those in that case --- -2.30.2 - diff --git a/board/freescale/common/patches/arm-trusted-firmware/0002-LF-7968-01-fix-Makefile-Suppress-array-bounds-error.patch b/board/freescale/common/patches/arm-trusted-firmware/0002-LF-7968-01-fix-Makefile-Suppress-array-bounds-error.patch deleted file mode 100644 index 7a7a7bbc2851..000000000000 --- a/board/freescale/common/patches/arm-trusted-firmware/0002-LF-7968-01-fix-Makefile-Suppress-array-bounds-error.patch +++ /dev/null @@ -1,51 +0,0 @@ -From b2a94de52ae4a940a87d569815b19d3fa92dd32a Mon Sep 17 00:00:00 2001 -From: Tom Hochstein -Date: Mon, 16 May 2022 13:45:16 -0500 -Subject: [PATCH] LF-7968-01 fix(Makefile): Suppress array-bounds error - -The array-bounds error is triggered now in cases where it was silent -before, causing errors like: - -``` -plat/imx/imx8m/hab.c: In function 'imx_hab_handler': -plat/imx/imx8m/hab.c:64:57: error: array subscript 0 is outside array bounds of 'uint32_t[0]' {aka 'unsigned int[]'} [-Werror=array-bounds] - 64 | #define HAB_RVT_CHECK_TARGET_ARM64 ((unsigned long)*(uint32_t *)(HAB_RVT_BASE + 0x18)) - | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -``` - -The error is a false-positive and is entered as a bug [1]. The problem -is fixed partially in GCC 12 and fully in GCC 13 [2]. - -The partial fix does not work here because the constant addresses used -are less than the 4kB boundary chosen for the partial fix, so suppress -the error until GCC is upgraded to 13. - -[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99578 -[2] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99578#c39 - -Upstream-Status: Inappropriate [other] -Signed-off-by: Tom Hochstein -Signed-off-by: Jacky Bai -Reviewed-by: Ye Li -Signed-off-by: Brandon Maier -Upstream: https://github.com/nxp-imx/imx-atf/commit/058bf0f104115037d03e277f079825ef3659c5b9 ---- - Makefile | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/Makefile b/Makefile -index c87c3ae08..2d6b90f47 100644 ---- a/Makefile -+++ b/Makefile -@@ -346,7 +346,7 @@ WARNINGS += -Wshift-overflow -Wshift-sign-overflow \ - endif - - ifneq (${E},0) --ERRORS := -Werror -+ERRORS := -Werror -Wno-error=array-bounds - endif - - CPPFLAGS = ${DEFINES} ${INCLUDES} ${MBEDTLS_INC} -nostdinc \ --- -2.41.0 - diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0018-feat-build-add-support-for-new-binutils-versions.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0018-feat-build-add-support-for-new-binutils-versions.patch deleted file mode 120000 index 5ef794304fba..000000000000 --- a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0018-feat-build-add-support-for-new-binutils-versions.patch +++ /dev/null @@ -1 +0,0 @@ -../../../../freescale/common/patches/arm-trusted-firmware/0001-feat-build-add-support-for-new-binutils-versions.patch \ No newline at end of file diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0018-feat-build-add-support-for-new-binutils-versions.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0018-feat-build-add-support-for-new-binutils-versions.patch new file mode 100644 index 000000000000..335c18553ac3 --- /dev/null +++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0018-feat-build-add-support-for-new-binutils-versions.patch @@ -0,0 +1,61 @@ +From 0f75b03c008eacb9818af3a56dc088e72a623d17 Mon Sep 17 00:00:00 2001 +From: Marco Felsch +Date: Wed, 9 Nov 2022 12:59:09 +0100 +Subject: [PATCH] feat(build): add support for new binutils versions + +Users of GNU ld (BPF) from binutils 2.39+ will observe multiple instaces +of a new warning when linking the bl*.elf in the form: + + ld.bfd: warning: stm32mp1_helper.o: missing .note.GNU-stack section implies executable stack + ld.bfd: NOTE: This behaviour is deprecated and will be removed in a future version of the linker + ld.bfd: warning: bl2.elf has a LOAD segment with RWX permissions + ld.bfd: warning: bl32.elf has a LOAD segment with RWX permissions + +These new warnings are enbaled by default to secure elf binaries: + - https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=ba951afb99912da01a6e8434126b8fac7aa75107 + - https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=0d38576a34ec64a1b4500c9277a8e9d0f07e6774 + +Fix it in a similar way to what the Linux kernel does, see: +https://lore.kernel.org/all/20220810222442.2296651-1-ndesaulniers@google.com/ + +Following the reasoning there, we set "-z noexecstack" for all linkers +(although LLVM's LLD defaults to it) and optional add +--no-warn-rwx-segments since this a ld.bfd related. + +Signed-off-by: Marco Felsch +Signed-off-by: Robert Schwebel +Change-Id: I9430f5fa5036ca88da46cd3b945754d62616b617 +Signed-off-by: Heiko Thiery +Upstream: https://github.com/ARM-software/arm-trusted-firmware/commit/1f49db5f25cdd4e43825c9bcc0575070b80f628c +--- + Makefile | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/Makefile b/Makefile +index 1ddb7b844..470956b19 100644 +--- a/Makefile ++++ b/Makefile +@@ -416,6 +416,8 @@ endif + + GCC_V_OUTPUT := $(shell $(CC) -v 2>&1) + ++TF_LDFLAGS += -z noexecstack ++ + # LD = armlink + ifneq ($(findstring armlink,$(notdir $(LD))),) + TF_LDFLAGS += --diag_error=warning --lto_level=O1 +@@ -442,7 +444,10 @@ TF_LDFLAGS += $(subst --,-Xlinker --,$(TF_LDFLAGS_$(ARCH))) + + # LD = gcc-ld (ld) or llvm-ld (ld.lld) or other + else +-TF_LDFLAGS += --fatal-warnings -O1 ++# With ld.bfd version 2.39 and newer new warnings are added. Skip those since we ++# are not loaded by a elf loader. ++TF_LDFLAGS += $(call ld_option, --no-warn-rwx-segments) ++TF_LDFLAGS += -O1 + TF_LDFLAGS += --gc-sections + # ld.lld doesn't recognize the errata flags, + # therefore don't add those in that case +-- +2.30.2 +