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Sat, 16 Nov 2024 08:01:12 +0000 Received: from smtpav02.wdc07v.mail.ibm.com (smtpav02.wdc07v.mail.ibm.com [10.39.53.229]) by smtprelay07.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 4AG81BbE51773848 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sat, 16 Nov 2024 08:01:11 GMT Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 433BF5805B; Sat, 16 Nov 2024 08:01:11 +0000 (GMT) Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B7AB65805C; Sat, 16 Nov 2024 08:01:10 +0000 (GMT) Received: from cowardly-lion.the-meissners.org (unknown [9.61.98.188]) by smtpav02.wdc07v.mail.ibm.com (Postfix) with ESMTPS; Sat, 16 Nov 2024 08:01:10 +0000 (GMT) Date: Sat, 16 Nov 2024 03:01:09 -0500 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , Peter Bergner Subject: [PATCH V4 1/5] Change TARGET_POPCNTB to TARGET_POWER5. Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , Peter Bergner References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: cKth6phAzf3P3D6cfU40ExJL6lbz7zZJ X-Proofpoint-GUID: cKth6phAzf3P3D6cfU40ExJL6lbz7zZJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 phishscore=0 clxscore=1015 suspectscore=0 spamscore=0 impostorscore=0 bulkscore=0 mlxscore=0 adultscore=0 lowpriorityscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411160066 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This patch changes TARGET_POPCNTB to TARGET_POWER5. The -mpopcntb switch is not being changed in this patch, just the name of the macros used to determine if the PowerPC processor supports ISA 2.2 (Power5). I have tested this on both big and little endian PowerPC systems and there is no regresion. Can I check it into GCC 15. 2024-11-15 Michael Meissner gcc/ * gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Change TARGET_POPCNTB to TARGET_POWER5. * gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal): Likewise. * gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise. (TARGET_POWER5): New macro. (TARGET_EXTRA_BUILTINS): Change TARGET_POPCNTB to TARGET_POWER5. (TARGET_FRE): Likewise. (TARGET_FRSQRTES): Likewise. * gcc/config/rs6000/rs6000.md (enabled attribute): Likewise. --- gcc/config/rs6000/rs6000-builtin.cc | 2 +- gcc/config/rs6000/rs6000.cc | 2 +- gcc/config/rs6000/rs6000.h | 11 +++++++---- gcc/config/rs6000/rs6000.md | 2 +- 4 files changed, 10 insertions(+), 7 deletions(-) diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index 9bdbae1ecf9..98a0545030c 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -155,7 +155,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) case ENB_ALWAYS: return true; case ENB_P5: - return TARGET_POPCNTB; + return TARGET_POWER5; case ENB_P6: return TARGET_CMPB; case ENB_P6_64: diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 950fd947fda..84b23f58d85 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3924,7 +3924,7 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks); else if (TARGET_FPRND) rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks); - else if (TARGET_POPCNTB) + else if (TARGET_POWER5) rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks); else if (TARGET_ALTIVEC) rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks); diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index d460eb06544..80d954e1178 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -448,7 +448,7 @@ extern int rs6000_vector_align[]; Enable 32-bit fcfid's on any of the switches for newer ISA machines. */ #define TARGET_FCFID (TARGET_POWERPC64 \ || TARGET_PPC_GPOPT /* 970/power4 */ \ - || TARGET_POPCNTB /* ISA 2.02 */ \ + || TARGET_POWER5 /* ISA 2.02 */ \ || TARGET_CMPB /* ISA 2.05 */ \ || TARGET_POPCNTD) /* ISA 2.06 */ @@ -501,6 +501,9 @@ extern int rs6000_vector_align[]; #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ && (TARGET_P9_MINMAX || !flag_trapping_math)) +/* Convert ISA bits like POPCNTB to PowerPC processors like POWER5. */ +#define TARGET_POWER5 TARGET_POPCNTB + /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_ instead of MASK_. The MASK_ options that have not yet been replaced by their OPTION_MASK_ @@ -527,7 +530,7 @@ extern int rs6000_vector_align[]; #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \ || TARGET_PPC_GPOPT /* 970/power4 */ \ - || TARGET_POPCNTB /* ISA 2.02 */ \ + || TARGET_POWER5 /* ISA 2.02 */ \ || TARGET_CMPB /* ISA 2.05 */ \ || TARGET_POPCNTD /* ISA 2.06 */ \ || TARGET_ALTIVEC \ @@ -543,9 +546,9 @@ extern int rs6000_vector_align[]; #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT) #define TARGET_FRE (TARGET_HARD_FLOAT \ - && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) + && (TARGET_POWER5 || VECTOR_UNIT_VSX_P (DFmode))) -#define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ +#define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POWER5 \ && TARGET_PPC_GFXOPT) #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 8eda2f7bb0d..9c7e92d5fe2 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -379,7 +379,7 @@ (define_attr "enabled" "" (const_int 1) (and (eq_attr "isa" "p5") - (match_test "TARGET_POPCNTB")) + (match_test "TARGET_POWER5")) (const_int 1) (and (eq_attr "isa" "p6") From patchwork Sat Nov 16 08:02:56 2024 Content-Type: text/plain; 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Sat, 16 Nov 2024 08:03:00 +0000 Received: from smtpav02.dal12v.mail.ibm.com (smtpav02.dal12v.mail.ibm.com [10.241.53.101]) by smtprelay03.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 4AG82w1X66978098 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sat, 16 Nov 2024 08:02:58 GMT Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7C95858051; Sat, 16 Nov 2024 08:02:58 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 272445805E; Sat, 16 Nov 2024 08:02:58 +0000 (GMT) Received: from cowardly-lion.the-meissners.org (unknown [9.61.98.188]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTPS; Sat, 16 Nov 2024 08:02:58 +0000 (GMT) Date: Sat, 16 Nov 2024 03:02:56 -0500 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , Peter Bergner Subject: [PATCH V4 2/5] Change TARGET_FPRND to TARGET_POWER5X. Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , Peter Bergner References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: fNFpzD4IunuX6OmWgj0EuHKMYXPd20ZG X-Proofpoint-GUID: fNFpzD4IunuX6OmWgj0EuHKMYXPd20ZG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 phishscore=0 clxscore=1015 suspectscore=0 spamscore=0 impostorscore=0 bulkscore=0 mlxscore=0 adultscore=0 lowpriorityscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411160066 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This patch changes TARGET_POWER5X to TARGET_POWER5. The -mfprnd switch is not being changed, just the name of the macros used to determine if the PowerPC processor supports ISA 2.4 (Power5x). I have GCC with this patch on both big and little endian systems and there were no regressions. Can I check this patch into GCC 15? 2024-11-15 Michael Meissner gcc/ * gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal): Change TARGET_FPRND to TARGET_POWER5X. * gcc/config/rs6000/rs6000.h (TARGET_POWERP5X): New macro. * gcc/config/rs6000/rs6000.md (fmod3): Change TARGET_FPRND to TARGET_POWER5X. (remainder3): Likewise. (fctiwuz_): Likewise. (ceil2): Likewise. (floor2): Likewise. (round2): Likewise. --- gcc/config/rs6000/rs6000.cc | 4 ++-- gcc/config/rs6000/rs6000.h | 1 + gcc/config/rs6000/rs6000.md | 14 +++++++------- 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 84b23f58d85..8dfaea5df07 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3922,7 +3922,7 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks); else if (TARGET_CMPB) rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks); - else if (TARGET_FPRND) + else if (TARGET_POWER5X) rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks); else if (TARGET_POWER5) rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks); @@ -3949,7 +3949,7 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags &= ~OPTION_MASK_CRYPTO; } - if (!TARGET_FPRND && TARGET_VSX) + if (!TARGET_POWER5X && TARGET_VSX) { if (rs6000_isa_flags_explicit & OPTION_MASK_FPRND) /* TARGET_VSX = 1 implies Power 7 and newer */ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 80d954e1178..8573b859405 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -503,6 +503,7 @@ extern int rs6000_vector_align[]; /* Convert ISA bits like POPCNTB to PowerPC processors like POWER5. */ #define TARGET_POWER5 TARGET_POPCNTB +#define TARGET_POWER5X TARGET_FPRND /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_ instead of MASK_. The MASK_ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 9c7e92d5fe2..e7c532fbaa0 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -5171,7 +5171,7 @@ (define_expand "fmod3" (use (match_operand:SFDF 1 "gpc_reg_operand")) (use (match_operand:SFDF 2 "gpc_reg_operand"))] "TARGET_HARD_FLOAT - && TARGET_FPRND + && TARGET_POWER5X && flag_unsafe_math_optimizations" { rtx div = gen_reg_rtx (mode); @@ -5189,7 +5189,7 @@ (define_expand "remainder3" (use (match_operand:SFDF 1 "gpc_reg_operand")) (use (match_operand:SFDF 2 "gpc_reg_operand"))] "TARGET_HARD_FLOAT - && TARGET_FPRND + && TARGET_POWER5X && flag_unsafe_math_optimizations" { rtx div = gen_reg_rtx (mode); @@ -6687,7 +6687,7 @@ (define_insn "fctiwuz_" (define_insn "*friz" [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa") (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"))))] - "TARGET_HARD_FLOAT && TARGET_FPRND + "TARGET_HARD_FLOAT && TARGET_POWER5X && flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ" "@ friz %0,%1 @@ -6815,7 +6815,7 @@ (define_insn "btrunc2" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")] UNSPEC_FRIZ))] - "TARGET_HARD_FLOAT && TARGET_FPRND" + "TARGET_HARD_FLOAT && TARGET_POWER5X" "@ friz %0,%1 xsrdpiz %x0,%x1" @@ -6825,7 +6825,7 @@ (define_insn "ceil2" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")] UNSPEC_FRIP))] - "TARGET_HARD_FLOAT && TARGET_FPRND" + "TARGET_HARD_FLOAT && TARGET_POWER5X" "@ frip %0,%1 xsrdpip %x0,%x1" @@ -6835,7 +6835,7 @@ (define_insn "floor2" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")] UNSPEC_FRIM))] - "TARGET_HARD_FLOAT && TARGET_FPRND" + "TARGET_HARD_FLOAT && TARGET_POWER5X" "@ frim %0,%1 xsrdpim %x0,%x1" @@ -6846,7 +6846,7 @@ (define_insn "round2" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=") (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")] UNSPEC_FRIN))] - "TARGET_HARD_FLOAT && TARGET_FPRND" + "TARGET_HARD_FLOAT && TARGET_POWER5X" "frin %0,%1" [(set_attr "type" "fp")]) From patchwork Sat Nov 16 08:04:53 2024 Content-Type: text/plain; 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Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , Peter Bergner References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: i1C3dTjJ0tKVm6RhyIJL_ZnPCd46-hrH X-Proofpoint-GUID: i1C3dTjJ0tKVm6RhyIJL_ZnPCd46-hrH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 phishscore=0 clxscore=1015 suspectscore=0 spamscore=0 impostorscore=0 bulkscore=0 mlxscore=0 adultscore=0 lowpriorityscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411160066 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This patch changes TARGET_CMPB to TARGET_POWER6. The -mcmpb switch is not being changed, just the name of the macros used to determine if the PowerPC processor supports ISA 2.5 (Power6). I have built GCC on both big end little endian systems and there were no regressions. Can I check this into GCC 15? 2024-11-16 Michael Meissner gcc/ * gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Change TARGET_CMPB to TARGET_POWER6. * gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal): Likewise. (rs6000_rtx_costs): Likewise. (rs6000_emit_parity): Likewise. * gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise. (TARGET_LFIWAX): Likewise. (TARGET_POWER6): New macro. (TARGET_EXTRA_BUILTINS): Change TARGET_CMPB to TARGET_POWER6. * gcc/config/rs6000/rs6000.md (enabled attribute): Likewise. (parity2_cmp): Likewise. (cmpb3): Likewise. (copysign3): Likewise. (copysign3_fcpsgn): Likewise. (cmpstrnsi): Likewise. (cmpstrsi): Likewise. --- gcc/config/rs6000/rs6000-builtin.cc | 4 ++-- gcc/config/rs6000/rs6000.cc | 8 ++++---- gcc/config/rs6000/rs6000.h | 7 ++++--- gcc/config/rs6000/rs6000.md | 16 ++++++++-------- 4 files changed, 18 insertions(+), 17 deletions(-) diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index 98a0545030c..76421bd1de0 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -157,9 +157,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) case ENB_P5: return TARGET_POWER5; case ENB_P6: - return TARGET_CMPB; + return TARGET_POWER6; case ENB_P6_64: - return TARGET_CMPB && TARGET_POWERPC64; + return TARGET_POWER6 && TARGET_POWERPC64; case ENB_P7: return TARGET_POPCNTD; case ENB_P7_64: diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 8dfaea5df07..ca5d66beb37 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3920,7 +3920,7 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks); else if (TARGET_DFP) rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks); - else if (TARGET_CMPB) + else if (TARGET_POWER6) rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks); else if (TARGET_POWER5X) rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks); @@ -4796,7 +4796,7 @@ rs6000_option_override_internal (bool global_init_p) DERAT mispredict penalty. However the LVE and STVE altivec instructions need indexed accesses and the type used is the scalar type of the element being loaded or stored. */ - TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB + TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_POWER6 && !TARGET_ALTIVEC); /* Set the -mrecip options. */ @@ -22435,7 +22435,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code, return false; case PARITY: - *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6); + *total = COSTS_N_INSNS (TARGET_POWER6 ? 2 : 6); return false; case NOT: @@ -23262,7 +23262,7 @@ rs6000_emit_parity (rtx dst, rtx src) tmp = gen_reg_rtx (mode); /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */ - if (TARGET_CMPB) + if (TARGET_POWER6) { if (mode == SImode) { diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 8573b859405..1b10802a87f 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -449,12 +449,12 @@ extern int rs6000_vector_align[]; #define TARGET_FCFID (TARGET_POWERPC64 \ || TARGET_PPC_GPOPT /* 970/power4 */ \ || TARGET_POWER5 /* ISA 2.02 */ \ - || TARGET_CMPB /* ISA 2.05 */ \ + || TARGET_POWER6 /* ISA 2.05 */ \ || TARGET_POPCNTD) /* ISA 2.06 */ #define TARGET_FCTIDZ TARGET_FCFID #define TARGET_STFIWX TARGET_PPC_GFXOPT -#define TARGET_LFIWAX TARGET_CMPB +#define TARGET_LFIWAX TARGET_POWER6 #define TARGET_LFIWZX TARGET_POPCNTD #define TARGET_FCFIDS TARGET_POPCNTD #define TARGET_FCFIDU TARGET_POPCNTD @@ -504,6 +504,7 @@ extern int rs6000_vector_align[]; /* Convert ISA bits like POPCNTB to PowerPC processors like POWER5. */ #define TARGET_POWER5 TARGET_POPCNTB #define TARGET_POWER5X TARGET_FPRND +#define TARGET_POWER6 TARGET_CMPB /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_ instead of MASK_. The MASK_ @@ -532,7 +533,7 @@ extern int rs6000_vector_align[]; #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \ || TARGET_PPC_GPOPT /* 970/power4 */ \ || TARGET_POWER5 /* ISA 2.02 */ \ - || TARGET_CMPB /* ISA 2.05 */ \ + || TARGET_POWER6 /* ISA 2.05 */ \ || TARGET_POPCNTD /* ISA 2.06 */ \ || TARGET_ALTIVEC \ || TARGET_VSX \ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index e7c532fbaa0..07eae9ca0c5 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -383,7 +383,7 @@ (define_attr "enabled" "" (const_int 1) (and (eq_attr "isa" "p6") - (match_test "TARGET_CMPB")) + (match_test "TARGET_POWER6")) (const_int 1) (and (eq_attr "isa" "p7") @@ -2544,7 +2544,7 @@ (define_expand "parity2" (define_insn "parity2_cmpb" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))] - "TARGET_CMPB && TARGET_POPCNTB" + "TARGET_POWER6 && TARGET_POPCNTB" "prty %0,%1" [(set_attr "type" "popcnt")]) @@ -2597,7 +2597,7 @@ (define_insn "cmpb3" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r") (match_operand:GPR 2 "gpc_reg_operand" "r")] UNSPEC_CMPB))] - "TARGET_CMPB" + "TARGET_POWER6" "cmpb %0,%1,%2" [(set_attr "type" "cmp")]) @@ -5401,7 +5401,7 @@ (define_expand "copysign3" && ((TARGET_PPC_GFXOPT && !HONOR_NANS (mode) && !HONOR_SIGNED_ZEROS (mode)) - || TARGET_CMPB + || TARGET_POWER6 || VECTOR_UNIT_VSX_P (mode))" { /* Middle-end canonicalizes -fabs (x) to copysign (x, -1), @@ -5422,7 +5422,7 @@ (define_expand "copysign3" if (!gpc_reg_operand (operands[2], mode)) operands[2] = copy_to_mode_reg (mode, operands[2]); - if (TARGET_CMPB || VECTOR_UNIT_VSX_P (mode)) + if (TARGET_POWER6 || VECTOR_UNIT_VSX_P (mode)) { emit_insn (gen_copysign3_fcpsgn (operands[0], operands[1], operands[2])); @@ -5438,7 +5438,7 @@ (define_insn "copysign3_fcpsgn" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") (copysign:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa") (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))] - "TARGET_HARD_FLOAT && (TARGET_CMPB || VECTOR_UNIT_VSX_P (mode))" + "TARGET_HARD_FLOAT && (TARGET_POWER6 || VECTOR_UNIT_VSX_P (mode))" "@ fcpsgn %0,%2,%1 xscpsgndp %x0,%x2,%x1" @@ -10122,7 +10122,7 @@ (define_expand "cmpstrnsi" (match_operand:BLK 2))) (use (match_operand:SI 3)) (use (match_operand:SI 4))])] - "TARGET_CMPB && (BYTES_BIG_ENDIAN || TARGET_LDBRX)" + "TARGET_POWER6 && (BYTES_BIG_ENDIAN || TARGET_LDBRX)" { if (optimize_insn_for_size_p ()) FAIL; @@ -10144,7 +10144,7 @@ (define_expand "cmpstrsi" (compare:SI (match_operand:BLK 1) (match_operand:BLK 2))) (use (match_operand:SI 3))])] - "TARGET_CMPB && (BYTES_BIG_ENDIAN || TARGET_LDBRX)" + "TARGET_POWER6 && (BYTES_BIG_ENDIAN || TARGET_LDBRX)" { if (optimize_insn_for_size_p ()) FAIL; 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Sat, 16 Nov 2024 08:06:45 +0000 Received: from smtpav02.dal12v.mail.ibm.com (smtpav02.dal12v.mail.ibm.com [10.241.53.101]) by smtprelay07.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 4AG86h5n26477168 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sat, 16 Nov 2024 08:06:44 GMT Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B255058051; Sat, 16 Nov 2024 08:06:43 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 51F185805A; Sat, 16 Nov 2024 08:06:43 +0000 (GMT) Received: from cowardly-lion.the-meissners.org (unknown [9.61.98.188]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTPS; Sat, 16 Nov 2024 08:06:43 +0000 (GMT) Date: Sat, 16 Nov 2024 03:06:41 -0500 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , Peter Bergner Subject: [PATCH V4 4/5] Change TARGET_POPCNTD to TARGET_POWER7. Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , Peter Bergner References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 3iGtGA3S0s_QmwNa9-IcOmMB4308WiLZ X-Proofpoint-GUID: 3iGtGA3S0s_QmwNa9-IcOmMB4308WiLZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 mlxscore=0 phishscore=0 malwarescore=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 priorityscore=1501 adultscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411160066 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This patch changes TARGET_POPCNTD to TARGET_POWER7. The -mpopcntd switch is not being changed, just the name of the macros used to determine if the PowerPC processor supports ISA 2.6 (Power7). I have built GCC on both big and little endian systems and there were no regressions. Can I check this patch into GCC 15? 2024-11-16 Michael Meissner gcc/ * gcc/config/rs6000/dfp.md (cmp_internal1): Change TARGET_POPCNTD to TARGET_POWER7. * gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Likewise. * gcc/config/rs6000/rs6000-string.cc (expand_block_compare): Likewise. * gcc/config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Likewise. (rs6000_option_override_internal): Likewise. (rs6000_rtx_costs): Likewise. * gcc/config/rs6000/rs6000.h (TARGET_LDBRX): Likewise. (TARGET_FCFID): Likewise. (TARGET_LFIWZX): Likewise. (TARGET_FCFIDS): Likewise. (TARGET_FCFIDU): Likewise. (TARGET_FCFIDUS): Likewise. (TARGET_FCTIDUZ): Likewise. (TARGET_FCTIWUZ): Likewise. (TARGET_FCTIDUZ): Likewise. (TARGET_POWER7): New macro. (TARGET_EXTRA_BUILTINS): Change TARGET_POPCNTD to TARGET_POWER7. (CTZ_DEFINED_VALUE_AT_ZERO): Likewise. * gcc/config/rs6000/rs6000.md (enabled attribute): Likewise. (lrintsi2): Likewise. (lrintsi): Likewise. (lrintsi_di): Likewise. (cmpmemsi): Likewise. (bpermd_): Likewise. (addg6s): Likewise. (cdtbcd): Likewise. (cbcdtd): Likewise. (div_): Likewise. --- gcc/config/rs6000/dfp.md | 2 +- gcc/config/rs6000/rs6000-builtin.cc | 4 ++-- gcc/config/rs6000/rs6000-string.cc | 2 +- gcc/config/rs6000/rs6000.cc | 8 ++++---- gcc/config/rs6000/rs6000.h | 21 +++++++++++---------- gcc/config/rs6000/rs6000.md | 20 ++++++++++---------- 6 files changed, 29 insertions(+), 28 deletions(-) diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md index fa9d7dd45dd..b8189390d41 100644 --- a/gcc/config/rs6000/dfp.md +++ b/gcc/config/rs6000/dfp.md @@ -214,7 +214,7 @@ (define_insn "*cmp_internal1" (define_insn "floatdidd2" [(set (match_operand:DD 0 "gpc_reg_operand" "=d") (float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))] - "TARGET_DFP && TARGET_POPCNTD" + "TARGET_DFP && TARGET_POWER7" "dcffix %0,%1" [(set_attr "type" "dfp")]) diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index 76421bd1de0..dae43b672ea 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -161,9 +161,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) case ENB_P6_64: return TARGET_POWER6 && TARGET_POWERPC64; case ENB_P7: - return TARGET_POPCNTD; + return TARGET_POWER7; case ENB_P7_64: - return TARGET_POPCNTD && TARGET_POWERPC64; + return TARGET_POWER7 && TARGET_POWERPC64; case ENB_P8: return TARGET_POWER8; case ENB_P8V: diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc index de618da9b5d..b633d80110d 100644 --- a/gcc/config/rs6000/rs6000-string.cc +++ b/gcc/config/rs6000/rs6000-string.cc @@ -1949,7 +1949,7 @@ bool expand_block_compare (rtx operands[]) { /* TARGET_POPCNTD is already guarded at expand cmpmemsi. */ - gcc_assert (TARGET_POPCNTD); + gcc_assert (TARGET_POWER7); /* For P8, this case is complicated to handle because the subtract with carry instructions do not generate the 64-bit carry and so diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index ca5d66beb37..2683fff80cf 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1922,7 +1922,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode) if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD) return 1; - if (TARGET_POPCNTD && mode == SImode) + if (TARGET_POWER7 && mode == SImode) return 1; if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode)) @@ -3916,7 +3916,7 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks); else if (TARGET_VSX) rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks); - else if (TARGET_POPCNTD) + else if (TARGET_POWER7) rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks); else if (TARGET_DFP) rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks); @@ -4129,7 +4129,7 @@ rs6000_option_override_internal (bool global_init_p) else if (TARGET_LONG_DOUBLE_128) { if (global_options.x_rs6000_ieeequad - && (!TARGET_POPCNTD || !TARGET_VSX)) + && (!TARGET_POWER7 || !TARGET_VSX)) error ("%qs requires full ISA 2.06 support", "-mabi=ieeelongdouble"); if (rs6000_ieeequad != TARGET_IEEEQUAD_DEFAULT) @@ -22431,7 +22431,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code, return false; case POPCOUNT: - *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6); + *total = COSTS_N_INSNS (TARGET_POWER7 ? 1 : 6); return false; case PARITY: diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 1b10802a87f..94853e11fc8 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -442,7 +442,7 @@ extern int rs6000_vector_align[]; #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64) #define TARGET_IEEEQUAD rs6000_ieeequad #define TARGET_ALTIVEC_ABI rs6000_altivec_abi -#define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) +#define TARGET_LDBRX (TARGET_POWER7 || rs6000_cpu == PROCESSOR_CELL) /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. Enable 32-bit fcfid's on any of the switches for newer ISA machines. */ @@ -450,17 +450,17 @@ extern int rs6000_vector_align[]; || TARGET_PPC_GPOPT /* 970/power4 */ \ || TARGET_POWER5 /* ISA 2.02 */ \ || TARGET_POWER6 /* ISA 2.05 */ \ - || TARGET_POPCNTD) /* ISA 2.06 */ + || TARGET_POWER7) /* ISA 2.06 */ #define TARGET_FCTIDZ TARGET_FCFID #define TARGET_STFIWX TARGET_PPC_GFXOPT #define TARGET_LFIWAX TARGET_POWER6 -#define TARGET_LFIWZX TARGET_POPCNTD -#define TARGET_FCFIDS TARGET_POPCNTD -#define TARGET_FCFIDU TARGET_POPCNTD -#define TARGET_FCFIDUS TARGET_POPCNTD -#define TARGET_FCTIDUZ TARGET_POPCNTD -#define TARGET_FCTIWUZ TARGET_POPCNTD +#define TARGET_LFIWZX TARGET_POWER7 +#define TARGET_FCFIDS TARGET_POWER7 +#define TARGET_FCFIDU TARGET_POWER7 +#define TARGET_FCFIDUS TARGET_POWER7 +#define TARGET_FCTIDUZ TARGET_POWER7 +#define TARGET_FCTIWUZ TARGET_POWER7 /* Only powerpc64 and powerpc476 support fctid. */ #define TARGET_FCTID (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476) #define TARGET_CTZ TARGET_MODULO @@ -505,6 +505,7 @@ extern int rs6000_vector_align[]; #define TARGET_POWER5 TARGET_POPCNTB #define TARGET_POWER5X TARGET_FPRND #define TARGET_POWER6 TARGET_CMPB +#define TARGET_POWER7 TARGET_POPCNTD /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_ instead of MASK_. The MASK_ @@ -534,7 +535,7 @@ extern int rs6000_vector_align[]; || TARGET_PPC_GPOPT /* 970/power4 */ \ || TARGET_POWER5 /* ISA 2.02 */ \ || TARGET_POWER6 /* ISA 2.05 */ \ - || TARGET_POPCNTD /* ISA 2.06 */ \ + || TARGET_POWER7 /* ISA 2.06 */ \ || TARGET_ALTIVEC \ || TARGET_VSX \ || TARGET_HARD_FLOAT) @@ -1743,7 +1744,7 @@ typedef struct rs6000_args zero. The hardware instructions added in Power9 and the sequences using popcount return 32 or 64. */ #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ - (TARGET_CTZ || TARGET_POPCNTD \ + (TARGET_CTZ || TARGET_POWER7 \ ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \ : ((VALUE) = -1, 2)) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 07eae9ca0c5..b88254bb6ae 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -387,7 +387,7 @@ (define_attr "enabled" "" (const_int 1) (and (eq_attr "isa" "p7") - (match_test "TARGET_POPCNTD")) + (match_test "TARGET_POWER7")) (const_int 1) (and (eq_attr "isa" "p7v") @@ -6784,7 +6784,7 @@ (define_expand "lrintsi2" /* For those old archs in which SImode can't be hold in float registers, call lrintsi_di to put the result in DImode then convert it via stack. */ - if (!TARGET_POPCNTD) + if (!TARGET_POWER7) { rtx tmp = gen_reg_rtx (DImode); emit_insn (gen_lrintsi_di (tmp, operands[1])); @@ -6799,7 +6799,7 @@ (define_insn "*lrintsi" [(set (match_operand:SI 0 "gpc_reg_operand" "=d") (unspec:SI [(match_operand:SFDF 1 "gpc_reg_operand" "")] UNSPEC_FCTIW))] - "TARGET_HARD_FLOAT && TARGET_POPCNTD" + "TARGET_HARD_FLOAT && TARGET_POWER7" "fctiw %0,%1" [(set_attr "type" "fp")]) @@ -6807,7 +6807,7 @@ (define_insn "lrintsi_di" [(set (match_operand:DI 0 "gpc_reg_operand" "=d") (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "")] UNSPEC_FCTIW))] - "TARGET_HARD_FLOAT && !TARGET_POPCNTD" + "TARGET_HARD_FLOAT && !TARGET_POWER7" "fctiw %0,%1" [(set_attr "type" "fp")]) @@ -10168,7 +10168,7 @@ (define_expand "cmpmemsi" (match_operand:BLK 2))) (use (match_operand:SI 3)) (use (match_operand:SI 4))])] - "TARGET_POPCNTD" + "TARGET_POWER7" { if (optimize_insn_for_size_p ()) FAIL; @@ -14435,7 +14435,7 @@ (define_insn "bpermd_" [(set (match_operand:P 0 "gpc_reg_operand" "=r") (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r") (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))] - "TARGET_POPCNTD" + "TARGET_POWER7" "bpermd %0,%1,%2" [(set_attr "type" "popcnt")]) @@ -14813,7 +14813,7 @@ (define_insn "addg6s" (unspec:SI [(match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "register_operand" "r")] UNSPEC_ADDG6S))] - "TARGET_POPCNTD" + "TARGET_POWER7" "addg6s %0,%1,%2" [(set_attr "type" "integer")]) @@ -14821,7 +14821,7 @@ (define_insn "cdtbcd" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_CDTBCD))] - "TARGET_POPCNTD" + "TARGET_POWER7" "cdtbcd %0,%1" [(set_attr "type" "integer")]) @@ -14829,7 +14829,7 @@ (define_insn "cbcdtd" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_CBCDTD))] - "TARGET_POPCNTD" + "TARGET_POWER7" "cbcdtd %0,%1" [(set_attr "type" "integer")]) @@ -14844,7 +14844,7 @@ (define_insn "div_" (unspec:GPR [(match_operand:GPR 1 "register_operand" "r") (match_operand:GPR 2 "register_operand" "r")] UNSPEC_DIV_EXTEND))] - "TARGET_POPCNTD" + "TARGET_POWER7" "div %0,%1,%2" [(set_attr "type" "div") (set_attr "size" "")]) From patchwork Sat Nov 16 08:08:19 2024 Content-Type: text/plain; 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Sat, 16 Nov 2024 08:08:22 +0000 Received: from smtpav02.wdc07v.mail.ibm.com (smtpav02.wdc07v.mail.ibm.com [10.39.53.229]) by smtprelay01.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 4AG88LeG46662126 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sat, 16 Nov 2024 08:08:21 GMT Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 76C6E5805C; Sat, 16 Nov 2024 08:08:21 +0000 (GMT) Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EBA8958058; Sat, 16 Nov 2024 08:08:20 +0000 (GMT) Received: from cowardly-lion.the-meissners.org (unknown [9.61.98.188]) by smtpav02.wdc07v.mail.ibm.com (Postfix) with ESMTPS; Sat, 16 Nov 2024 08:08:20 +0000 (GMT) Date: Sat, 16 Nov 2024 03:08:19 -0500 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , Peter Bergner Subject: [PATCH V4 5/5] Change TARGET_MODULO to TARGET_POWER9. Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , Peter Bergner References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: pPwMTpRkZ0j_pxxrnCJnGNuwozyIepOA X-Proofpoint-GUID: pPwMTpRkZ0j_pxxrnCJnGNuwozyIepOA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=999 clxscore=1015 malwarescore=0 spamscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 mlxscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411160066 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This patch changes TARGET_MODULO to TARGET_POWER9. The -mmodulo switch is not being changed, just the name of the macros used to determine if the PowerPC processor supports ISA 3.0 (Power9). I have built GCC for both big and little endian systems and there were no regressions. Can I check this patch into GCC 15? 2024-11-15 Michael Meissner gcc/ * gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Change TARGET_MODULO to TARGET_POWER9. * gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal): Likewise. * gcc/config/rs6000/rs6000.h (TARGET_CTZ): Likewise. (TARGET_EXTSWSLI): Likewise. (TARGET_MADDLD): Likewise. (TARGET_POWER9): New macro. * gcc/config/rs6000/rs6000.md (enabled attribute): Change TARGET_MODULO to TARGET_POWER9. (mod3): Likewise. (umod3): Likewise. (divide/modulo peephole2): Likewise. --- gcc/config/rs6000/rs6000-builtin.cc | 4 ++-- gcc/config/rs6000/rs6000.cc | 4 ++-- gcc/config/rs6000/rs6000.h | 7 ++++--- gcc/config/rs6000/rs6000.md | 14 +++++++------- 4 files changed, 15 insertions(+), 14 deletions(-) diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index dae43b672ea..b6093b3cb64 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -169,9 +169,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) case ENB_P8V: return TARGET_P8_VECTOR; case ENB_P9: - return TARGET_MODULO; + return TARGET_POWER9; case ENB_P9_64: - return TARGET_MODULO && TARGET_POWERPC64; + return TARGET_POWER9 && TARGET_POWERPC64; case ENB_P9V: return TARGET_P9_VECTOR; case ENB_P10: diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 2683fff80cf..2b185165610 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3886,7 +3886,7 @@ rs6000_option_override_internal (bool global_init_p) /* For the newer switches (vsx, dfp, etc.) set some of the older options, unless the user explicitly used the -mno-