From patchwork Thu Oct 24 07:15:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Billy Tsai X-Patchwork-Id: 2001492 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=linux-aspeed+bounces-22-incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=patchwork.ozlabs.org) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XYxzL25Wdz1xwy for ; Thu, 24 Oct 2024 18:16:14 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [127.0.0.1]) by lists.ozlabs.org (Postfix) with ESMTP id 4XYxzH2VD1z2yNs; Thu, 24 Oct 2024 18:16:11 +1100 (AEDT) X-Original-To: linux-aspeed@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; arc=none smtp.remote-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707; t=1729754171; cv=none; b=ewJPxxSkH+TrnfzmKAxLK03iB+f+TiQjtfgJg7DR/5pN3k27p+i9cNBZG6FAo1Wq/CHzFSjisPyATpviSKloqLc7qzDRF1VXt0yFzhLNtEiSv1LFWnQ1s1gUQ6a67v9fVNs9CEK/Jb+vGoNHB+uvtQF/SxSQGPIGLhk9mUPHMOTlk2+GY8PF9LMXsXh4m3lwLoDy1osE1TpPM2PB2LsoGP6Xj/G/uS0vJoUCucTaVZrGQsDlBCG+2087jPZbyVx+oK1nvfp/2jJKXf6JUYP9fx2VBcTo/gaPvX5ueyizOs60XgQt/q69RSYseHcP+f03A4gJIV36ev5exHtdgk5d3w== ARC-Message-Signature: i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707; t=1729754171; c=relaxed/relaxed; bh=NV4BJB1hebCHxZfRKBVABAwnVrIkc01gp5Jshymh+3M=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=C79/cYwqTiFQ0SyrXS1Eo8cCg5kM05EnswjOn9WUpTRCgf9TheWWlr2WMUNO77PktlhNdhvhPEHSha+uKaBXpzkLq3SdPZ3ZJ57myu5rLR+FMeWRenAe7lbljbVO3XCxdHUlrh6kJ2CwSZeb6hZbRuYQC10fwG59mIj0y7mymuf411wzkKkAG1cXhU4JOOl23swGzfWLv24v1/8rDuhp73jo55d3ZldGPmeDjHpZejIUTyPaJ0JeETVjcgKVVlGjGtPcKXwCKjQROgAzTK2FVgFp6Wf7fNJY8x2BY/BKwONgu/uNk10uY3FUk/C8SC3oI7D+9J7aXDgU3fjYR2Ting== ARC-Authentication-Results: i=1; lists.ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass (client-ip=211.20.114.72; helo=twmbx01.aspeed.com; envelope-from=billy_tsai@aspeedtech.com; receiver=lists.ozlabs.org) smtp.mailfrom=aspeedtech.com Authentication-Results: lists.ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com (client-ip=211.20.114.72; helo=twmbx01.aspeed.com; envelope-from=billy_tsai@aspeedtech.com; receiver=lists.ozlabs.org) Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4XYxzG4TxMz2yF4 for ; Thu, 24 Oct 2024 18:16:10 +1100 (AEDT) Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 24 Oct 2024 15:15:48 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 24 Oct 2024 15:15:48 +0800 From: Billy Tsai To: , , , , , , , , , , , , , , , Subject: [PATCH v1 1/2] hwmon: (aspeed-g6-pwm-tacho): Extend the #pwm-cells to 4 Date: Thu, 24 Oct 2024 15:15:47 +0800 Message-ID: <20241024071548.3370363-2-billy_tsai@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241024071548.3370363-1-billy_tsai@aspeedtech.com> References: <20241024071548.3370363-1-billy_tsai@aspeedtech.com> X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_FAIL,SPF_PASS autolearn=disabled version=4.0.0 X-Spam-Checker-Version: SpamAssassin 4.0.0 (2022-12-13) on lists.ozlabs.org Add an option to support #pwm-cells up to 4. The additional cell is used to enable the WDT reset feature, which is specific to the ASPEED PWM controller. Signed-off-by: Billy Tsai Change-Id: Iefcc9622ac3dc684441d3e77aeb53c00f2ce4097 --- .../bindings/hwmon/aspeed,g6-pwm-tach.yaml | 25 ++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/hwmon/aspeed,g6-pwm-tach.yaml b/Documentation/devicetree/bindings/hwmon/aspeed,g6-pwm-tach.yaml index 9e5ed901ae54..0cc92ce29ece 100644 --- a/Documentation/devicetree/bindings/hwmon/aspeed,g6-pwm-tach.yaml +++ b/Documentation/devicetree/bindings/hwmon/aspeed,g6-pwm-tach.yaml @@ -31,7 +31,11 @@ properties: maxItems: 1 "#pwm-cells": - const: 3 + enum: [3, 4] + description: | + The value should be 4 to enable the WDT reload feature, which will change the duty cycle to + a preprogrammed value after WDT/EXTRST#. + The range for the fourth cell value supported by this binding is 0 to 255. patternProperties: "^fan-[0-9]+$": @@ -69,3 +73,22 @@ examples: pwms = <&pwm_tach 1 40000 0>; }; }; + - | + #include + pwm_tach: pwm-tach-controller@1e610000 { + compatible = "aspeed,ast2600-pwm-tach"; + reg = <0x1e610000 0x100>; + clocks = <&syscon ASPEED_CLK_AHB>; + resets = <&syscon ASPEED_RESET_PWM>; + #pwm-cells = <4>; + + fan-0 { + tach-ch = /bits/ 8 <0x0>; + pwms = <&pwm_tach 0 40000 0 128>; + }; + + fan-1 { + tach-ch = /bits/ 8 <0x1 0x2>; + pwms = <&pwm_tach 1 40000 0 160>; + }; + }; From patchwork Thu Oct 24 07:15:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Billy Tsai X-Patchwork-Id: 2001491 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=linux-aspeed+bounces-23-incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=patchwork.ozlabs.org) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XYxzJ5qRtz1xx6 for ; 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Thu, 24 Oct 2024 15:15:48 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 24 Oct 2024 15:15:48 +0800 From: Billy Tsai To: , , , , , , , , , , , , , , , Subject: [PATCH v1 2/2] hwmon: (aspeed-g6-pwm-tacho): Support the WDT reload Date: Thu, 24 Oct 2024 15:15:48 +0800 Message-ID: <20241024071548.3370363-3-billy_tsai@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241024071548.3370363-1-billy_tsai@aspeedtech.com> References: <20241024071548.3370363-1-billy_tsai@aspeedtech.com> X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_FAIL,SPF_PASS autolearn=disabled version=4.0.0 X-Spam-Checker-Version: SpamAssassin 4.0.0 (2022-12-13) on lists.ozlabs.org Use the DTS property #pwm-cells to determine if the PWM controller needs to enable the WDT reload feature, which changes the duty cycle to a preprogrammed value after a WDT/EXTRST#. When #pwm-cells = <4>, the feature will be enabled, and the PWM consumer can use the 4th argument to set the reload duty cycle [0-255]. Signed-off-by: Billy Tsai Change-Id: Ided520f73220581e3b37819a106ec81ebf9bb5a6 --- drivers/hwmon/aspeed-g6-pwm-tach.c | 49 ++++++++++++++++++++++++++++++ drivers/pwm/core.c | 6 ++-- include/linux/pwm.h | 10 ++++++ 3 files changed, 62 insertions(+), 3 deletions(-) diff --git a/drivers/hwmon/aspeed-g6-pwm-tach.c b/drivers/hwmon/aspeed-g6-pwm-tach.c index 75eadda738ab..df47f9aa8ee6 100644 --- a/drivers/hwmon/aspeed-g6-pwm-tach.c +++ b/drivers/hwmon/aspeed-g6-pwm-tach.c @@ -56,6 +56,7 @@ #include #include #include +#include #include #include @@ -452,6 +453,51 @@ static void aspeed_pwm_tach_reset_assert(void *data) reset_control_assert(rst); } +static void aspeed_pwm_set_wdt_reload(struct pwm_chip *chip, + struct pwm_device *pwm, + u64 reload_duty_cycle) +{ + struct aspeed_pwm_tach_data *priv = aspeed_pwm_chip_to_data(chip); + u32 hwpwm = pwm->hwpwm, val; + + val = readl(priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm)); + val &= ~PWM_ASPEED_DUTY_CYCLE_POINT_AS_WDT; + val |= FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_POINT_AS_WDT, + reload_duty_cycle); + writel(val, priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm)); + + val = readl(priv->base + PWM_ASPEED_CTRL(hwpwm)); + val |= PWM_ASPEED_CTRL_DUTY_LOAD_AS_WDT_ENABLE; + writel(val, priv->base + PWM_ASPEED_CTRL(hwpwm)); +} + +static struct pwm_device * +aspeed_pwm_xlate(struct pwm_chip *chip, const struct of_phandle_args *args) +{ + struct pwm_device *pwm; + + /* flags in the fourth cell are optional */ + if (args->args_count < 3) + return ERR_PTR(-EINVAL); + + if (args->args[0] >= chip->npwm) + return ERR_PTR(-EINVAL); + + pwm = pwm_request_from_chip(chip, args->args[0], NULL); + if (IS_ERR(pwm)) + return pwm; + + pwm->args.period = args->args[1]; + pwm->args.polarity = PWM_POLARITY_NORMAL; + if (args->args[2] & PWM_POLARITY_INVERTED) + pwm->args.polarity = PWM_POLARITY_INVERSED; + + if (args->args_count > 3 && args->args[3] < U8_MAX) + aspeed_pwm_set_wdt_reload(chip, pwm, args->args[3]); + + return pwm; +} + static int aspeed_pwm_tach_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev, *hwmon; @@ -493,6 +539,9 @@ static int aspeed_pwm_tach_probe(struct platform_device *pdev) pwmchip_set_drvdata(chip, priv); chip->ops = &aspeed_pwm_ops; + if (IS_ENABLED(CONFIG_OF)) + chip->of_xlate = aspeed_pwm_xlate; + ret = devm_pwmchip_add(dev, chip); if (ret) return dev_err_probe(dev, ret, "Failed to add PWM chip\n"); diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c index 6e752e148b98..8251f7b361ab 100644 --- a/drivers/pwm/core.c +++ b/drivers/pwm/core.c @@ -422,9 +422,8 @@ static int pwm_device_request(struct pwm_device *pwm, const char *label) * chip. A negative error code is returned if the index is not valid for the * specified PWM chip or if the PWM device cannot be requested. */ -static struct pwm_device *pwm_request_from_chip(struct pwm_chip *chip, - unsigned int index, - const char *label) +struct pwm_device *pwm_request_from_chip(struct pwm_chip *chip, + unsigned int index, const char *label) { struct pwm_device *pwm; int err; @@ -442,6 +441,7 @@ static struct pwm_device *pwm_request_from_chip(struct pwm_chip *chip, return pwm; } +EXPORT_SYMBOL_GPL(pwm_request_from_chip); struct pwm_device * of_pwm_xlate_with_flags(struct pwm_chip *chip, const struct of_phandle_args *args) diff --git a/include/linux/pwm.h b/include/linux/pwm.h index 8acd60b53f58..95ae885f65c3 100644 --- a/include/linux/pwm.h +++ b/include/linux/pwm.h @@ -405,6 +405,8 @@ void pwmchip_remove(struct pwm_chip *chip); int __devm_pwmchip_add(struct device *dev, struct pwm_chip *chip, struct module *owner); #define devm_pwmchip_add(dev, chip) __devm_pwmchip_add(dev, chip, THIS_MODULE) +struct pwm_device *pwm_request_from_chip(struct pwm_chip *chip, + unsigned int index, const char *label); struct pwm_device *of_pwm_xlate_with_flags(struct pwm_chip *chip, const struct of_phandle_args *args); struct pwm_device *of_pwm_single_xlate(struct pwm_chip *chip, @@ -504,6 +506,14 @@ static inline void pwm_put(struct pwm_device *pwm) might_sleep(); } +static inline struct pwm_device *pwm_request_from_chip(struct pwm_chip *chip, + unsigned int index, + const char *label) +{ + might_sleep(); + return ERR_PTR(-ENODEV); +} + static inline struct pwm_device *devm_pwm_get(struct device *dev, const char *consumer) {