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Fri, 4 Oct 2024 12:12:31 +0200 Date: Fri, 4 Oct 2024 12:12:30 +0200 From: Jakub Jelinek To: Uros Bizjak , Hongtao Liu Cc: gcc-patches@gcc.gnu.org Subject: [PATCH] i386: Fix up ix86_expand_int_compare with TImode comparisons of SUBREGs from V8{H,B}Fmode against zero [PR116921] Message-ID: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Disposition: inline X-Spam-Status: No, score=-3.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Jakub Jelinek Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Hi! The following testcase ICEs, because the ix86_expand_int_compare optimization to use {,v}ptest assumes there are instructions for all 16-byte vector modes. That isn't the case, we only have one for V16QI, V8HI, V4SI, V2DI, V1TI, V4SF and V2DF, not for V8HF nor V8BF. The following patch fixes that by using the V8HI instruction instead for those 2 modes. tmp can't be a SUBREG, because it is SUBREG_REG of another SUBREG, so we don't need to worry about gen_lowpart failing. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2024-10-04 Jakub Jelinek PR target/116921 * config/i386/i386-expand.cc (ix86_expand_int_compare): Add a SUBREG to V8HImode from V8HFmode or V8BFmode before generating a ptest. * gcc.target/i386/pr116921.c: New test. Jakub --- gcc/config/i386/i386-expand.cc.jj 2024-10-03 17:27:28.328227793 +0200 +++ gcc/config/i386/i386-expand.cc 2024-10-03 18:11:18.514076904 +0200 @@ -3095,6 +3095,9 @@ ix86_expand_int_compare (enum rtx_code c && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))) == 16) { tmp = SUBREG_REG (op0); + if (GET_MODE_INNER (GET_MODE (tmp)) == HFmode + || GET_MODE_INNER (GET_MODE (tmp)) == BFmode) + tmp = gen_lowpart (V8HImode, tmp); tmp = gen_rtx_UNSPEC (CCZmode, gen_rtvec (2, tmp, tmp), UNSPEC_PTEST); } else --- gcc/testsuite/gcc.target/i386/pr116921.c.jj 2024-10-03 18:16:36.368711747 +0200 +++ gcc/testsuite/gcc.target/i386/pr116921.c 2024-10-03 18:17:25.702034243 +0200 @@ -0,0 +1,12 @@ +/* PR target/116921 */ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -msse4" } */ + +long x; +_Float16 __attribute__((__vector_size__ (16))) f; + +void +foo (void) +{ + x -= !(__int128) (f / 2); +}