From patchwork Wed Oct 2 17:13:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 1992117 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XJhJt6mYfz1xt3 for ; Thu, 3 Oct 2024 03:15:26 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CB57A385DDCE for ; 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bh=+lac/pzqVvtuwJNj1IPe3pjmzaLQUjWvT+9CnZ5EORk=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=PaBTuTGInk8soT8Wzy0lZQTmpX+pCdX0loOsiKO1Z8JWG7SEYT+/tD+/+/WE/CY19bamgSFm++Ft1s0yOO8BHt8xNPgf3sIhtN8cPIa/H07XA7b+jHWXl8sEH7R3jCsNHUj3qFwGdKuxPG2fSOw7uLUsF+maxMl7901R/qY+9GA= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 840C8339; Wed, 2 Oct 2024 10:14:32 -0700 (PDT) Received: from e107157-lin.cambridge.arm.com (e107157-lin.cambridge.arm.com [10.2.78.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 60D553F64C; Wed, 2 Oct 2024 10:14:02 -0700 (PDT) From: Andre Vieira To: gcc-patches@gcc.gnu.org Cc: richard.sandiford@arm.com, Andre Vieira Subject: [PATCH 1/2] aarch64: Split FCMA feature bit from Armv8.3-A Date: Wed, 2 Oct 2024 18:13:38 +0100 Message-Id: <20241002171339.299940-2-andre.simoesdiasvieira@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241002171339.299940-1-andre.simoesdiasvieira@arm.com> References: <20241002171339.299940-1-andre.simoesdiasvieira@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This patch splits out FCMA as a feature from Armv8.3-A and adds it as a separate feature bit which now controls 'TARGET_COMPLEX'. gcc/ChangeLog: * config/aarch64/aarch64-arches.def (FCMA): New feature bit, can not be used as an extension in the command-line. * config/aarch64/aarch64.h (TARGET_COMPLEX): Use FCMA feature bit rather than ARMV8_3. --- gcc/config/aarch64/aarch64-arches.def | 2 +- gcc/config/aarch64/aarch64-option-extensions.def | 1 + gcc/config/aarch64/aarch64.h | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/gcc/config/aarch64/aarch64-arches.def b/gcc/config/aarch64/aarch64-arches.def index 4634b272e28..fadf9c36b03 100644 --- a/gcc/config/aarch64/aarch64-arches.def +++ b/gcc/config/aarch64/aarch64-arches.def @@ -33,7 +33,7 @@ AARCH64_ARCH("armv8-a", generic_armv8_a, V8A, 8, (SIMD)) AARCH64_ARCH("armv8.1-a", generic_armv8_a, V8_1A, 8, (V8A, LSE, CRC, RDMA)) AARCH64_ARCH("armv8.2-a", generic_armv8_a, V8_2A, 8, (V8_1A)) -AARCH64_ARCH("armv8.3-a", generic_armv8_a, V8_3A, 8, (V8_2A, PAUTH, RCPC)) +AARCH64_ARCH("armv8.3-a", generic_armv8_a, V8_3A, 8, (V8_2A, PAUTH, RCPC, FCMA)) AARCH64_ARCH("armv8.4-a", generic_armv8_a, V8_4A, 8, (V8_3A, F16FML, DOTPROD, FLAGM)) AARCH64_ARCH("armv8.5-a", generic_armv8_a, V8_5A, 8, (V8_4A, SB, SSBS, PREDRES)) AARCH64_ARCH("armv8.6-a", generic_armv8_a, V8_6A, 8, (V8_5A, I8MM, BF16)) diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index 6998627f377..4732c20ec96 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -193,6 +193,7 @@ AARCH64_OPT_EXTENSION("sve2-sm4", SVE2_SM4, (SVE2, SM4), (), (), "svesm4") AARCH64_FMV_FEATURE("sve2-sm4", SVE_SM4, (SVE2_SM4)) AARCH64_OPT_FMV_EXTENSION("sme", SME, (BF16, SVE2), (), (), "sme") +AARCH64_OPT_EXTENSION("", FCMA, (), (), (), "fcma") AARCH64_OPT_EXTENSION("memtag", MEMTAG, (), (), (), "") diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index a99e7bb6c47..c0ad305e324 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -362,7 +362,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED #define TARGET_JSCVT (TARGET_FLOAT && TARGET_ARMV8_3) /* Armv8.3-a Complex number extension to AdvSIMD extensions. */ -#define TARGET_COMPLEX (TARGET_SIMD && TARGET_ARMV8_3) +#define TARGET_COMPLEX (TARGET_SIMD && AARCH64_HAVE_ISA (FCMA)) /* Floating-point rounding instructions from Armv8.5-a. */ #define TARGET_FRINT (AARCH64_HAVE_ISA (V8_5A) && TARGET_FLOAT) From patchwork Wed Oct 2 17:13:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 1992116 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XJhHr70zYz1xtY for ; Thu, 3 Oct 2024 03:14:32 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B2D5D38650FD for ; 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bh=NdOKCIPYH9P/qSG4/MHlUHfcnF4CGRAyMau6WG6WQ/w=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=b4ml+mX34ewGtgwb38TXWPlC6Mw+c6OVTAWIFc8G14UCcJCrIsRWKrr8VBmKG+YOr7yBgmN+r3grqacuyweiwGr2/qmdzS6e9n5DVMmDGmnBeZd6xeuRnencZd1STYrB/O2xVAU4Ch5dkKbeWck5q4QoMAi3y780cyLwr0jPA5w= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BD559497; Wed, 2 Oct 2024 10:14:34 -0700 (PDT) Received: from e107157-lin.cambridge.arm.com (e107157-lin.cambridge.arm.com [10.2.78.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 728E43F64C; Wed, 2 Oct 2024 10:14:04 -0700 (PDT) From: Andre Vieira To: gcc-patches@gcc.gnu.org Cc: richard.sandiford@arm.com, Andre Vieira Subject: [PATCH 2/2] aarch64: remove SVE2 requirement from SME and diagnose it as unsupported Date: Wed, 2 Oct 2024 18:13:39 +0100 Message-Id: <20241002171339.299940-3-andre.simoesdiasvieira@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241002171339.299940-1-andre.simoesdiasvieira@arm.com> References: <20241002171339.299940-1-andre.simoesdiasvieira@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org As per the AArch64 ISA FEAT_SME does not require FEAT_SVE2, so we are removing that false dependency in GCC. However, we chose for now to not support this combination of features and will diagnose the combination of FEAT_SME without FEAT_SVE2 as unsupported by GCC. We may choose to support this in the future. gcc/ChangeLog: * config/aarch64/aarch64-arches.def (SME): Remove SVE2 as prerequisite and add in FCMA and F16FML. * config/aarch64/aarch64.cc (aarch64_override_options): Diagnose use of SME without SVE2. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve/acle/general-c/binary_int_opt_single_n_2.c: Pass +sve2 to existing +sme pragma. * gcc.target/aarch64/sve/acle/general-c/binary_opt_single_n_2.c: Likewise. * gcc.target/aarch64/sve/acle/general-c/binary_single_1.c: Likewise. * gcc.target/aarch64/sve/acle/general-c/binaryxn_2.c: Likewise. * gcc.target/aarch64/sve/acle/general-c/clamp_1.c: Likewise. * gcc.target/aarch64/sve/acle/general-c/compare_scalar_count_1.c: Likewise. * gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowxn_1.c: Likewise. * gcc.target/aarch64/sve/acle/general-c/storexn_1.c: Likewise. * gcc.target/aarch64/sve/acle/general-c/ternary_qq_or_011_lane_1.c: Likewise. * gcc.target/aarch64/sve/acle/general-c/unary_convertxn_1.c: Likewise. * gcc.target/aarch64/sve/acle/general-c/unaryxn_1.c: Likewise. --- gcc/config/aarch64/aarch64-option-extensions.def | 3 ++- gcc/config/aarch64/aarch64.cc | 4 ++++ .../aarch64/sve/acle/general-c/binary_int_opt_single_n_2.c | 2 +- .../aarch64/sve/acle/general-c/binary_opt_single_n_2.c | 2 +- .../gcc.target/aarch64/sve/acle/general-c/binary_single_1.c | 2 +- .../gcc.target/aarch64/sve/acle/general-c/binaryxn_2.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/clamp_1.c | 2 +- .../aarch64/sve/acle/general-c/compare_scalar_count_1.c | 2 +- .../aarch64/sve/acle/general-c/shift_right_imm_narrowxn_1.c | 2 +- .../gcc.target/aarch64/sve/acle/general-c/storexn_1.c | 2 +- .../aarch64/sve/acle/general-c/ternary_qq_or_011_lane_1.c | 2 +- .../gcc.target/aarch64/sve/acle/general-c/unary_convertxn_1.c | 2 +- .../gcc.target/aarch64/sve/acle/general-c/unaryxn_1.c | 2 +- 13 files changed, 17 insertions(+), 12 deletions(-) diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index 4732c20ec96..e38a4ab3f78 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -192,9 +192,10 @@ AARCH64_OPT_EXTENSION("sve2-sm4", SVE2_SM4, (SVE2, SM4), (), (), "svesm4") AARCH64_FMV_FEATURE("sve2-sm4", SVE_SM4, (SVE2_SM4)) -AARCH64_OPT_FMV_EXTENSION("sme", SME, (BF16, SVE2), (), (), "sme") AARCH64_OPT_EXTENSION("", FCMA, (), (), (), "fcma") +AARCH64_OPT_FMV_EXTENSION("sme", SME, (BF16, FCMA, F16FML), (), (), "sme") + AARCH64_OPT_EXTENSION("memtag", MEMTAG, (), (), (), "") AARCH64_OPT_FMV_EXTENSION("sb", SB, (), (), (), "sb") diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 68913beaee2..bc2023da180 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -18998,6 +18998,10 @@ aarch64_override_options (void) while processing functions with potential target attributes. */ target_option_default_node = target_option_current_node = build_target_option_node (&global_options, &global_options_set); + + if (TARGET_SME && !TARGET_SVE2) + warning (0, "this gcc version does not guarantee full support for +sme" + " without +sve2"); } /* Implement targetm.override_options_after_change. */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_int_opt_single_n_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_int_opt_single_n_2.c index 976d5af7f23..7150d37a2aa 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_int_opt_single_n_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_int_opt_single_n_2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" #include diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_opt_single_n_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_opt_single_n_2.c index 5cc8a4c5c50..2823264edbd 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_opt_single_n_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_opt_single_n_2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" #include diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_single_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_single_1.c index aa7633bb322..52f2c090f57 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_single_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_single_1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" #include diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binaryxn_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binaryxn_2.c index 600b7fc7959..4f8ebf8c2c7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binaryxn_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binaryxn_2.c @@ -2,7 +2,7 @@ #include -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void f1 (svbool_t pg, svcount_t pn, svuint8_t u8, svint16_t s16, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/clamp_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/clamp_1.c index 07e22d2dd71..958c40a2fc6 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/clamp_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/clamp_1.c @@ -2,7 +2,7 @@ #include -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void f1 (svcount_t pn, svfloat16_t f16, svint16_t s16, svfloat32_t f32, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/compare_scalar_count_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/compare_scalar_count_1.c index 47077f7a4e5..4a4222c1e82 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/compare_scalar_count_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/compare_scalar_count_1.c @@ -3,7 +3,7 @@ #include #include -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" enum signed_enum { SA = -1, SB }; enum unsigned_enum { UA, UB }; diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowxn_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowxn_1.c index ab5602f0aa6..685d0700400 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowxn_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowxn_1.c @@ -2,7 +2,7 @@ #include -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svboolx2_t pgx2, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/storexn_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/storexn_1.c index 7ad4ca8a580..ba0096b4b4b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/storexn_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/storexn_1.c @@ -3,7 +3,7 @@ #include -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" struct s { signed char x; }; diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_qq_or_011_lane_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_qq_or_011_lane_1.c index b8968c878e1..5579e0d11b0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_qq_or_011_lane_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_qq_or_011_lane_1.c @@ -2,7 +2,7 @@ #include -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void f1 (svbool_t pg, svint8_t s8, svuint8_t u8, svint16_t s16, svuint16_t u16, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_1.c index 85f8b45032d..e14ec71f0c3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_1.c @@ -1,6 +1,6 @@ #include -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void test (svbool_t pg, float f, svint8_t s8, svfloat32_t f32, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unaryxn_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unaryxn_1.c index f478945562c..e9656bc69af 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unaryxn_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unaryxn_1.c @@ -1,6 +1,6 @@ #include -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void test (svfloat32_t f32, svfloat32x2_t f32x2, svfloat32x3_t f32x3,