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Tue, 1 Oct 2024 12:09:40 +0000 From: To: CC: , , Saurabh Jha Subject: [PATCH v2 1/3] aarch64: Add SVE2 faminmax intrinsics Date: Tue, 1 Oct 2024 13:09:31 +0100 Message-ID: <20241001120933.1269122-2-saurabh.jha@arm.com> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20241001120933.1269122-1-saurabh.jha@arm.com> References: <20241001120933.1269122-1-saurabh.jha@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM2PEPF0001C711:EE_|AS8PR08MB8061:EE_|DU2PEPF00028D01:EE_|VI0PR08MB11083:EE_ X-MS-Office365-Filtering-Correlation-Id: c765bc3e-8651-438d-19b3-08dce211f423 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info-Original: AFJIAnxwDNVB5Y10HMJGw9JnvyUQoe4ZNyqhJIAit/6y5EWNRfnvOHiCrQWvp/qAbRIYW+8iYOGZxKSReCxdMl7iBuMUM31dVhIySQQ63ZdVdAy36ylusALpXpXT9/+fO0bEFw3XmXNPU7D4ihmxygUJMMwllUq9WM41FZ69N3Tp5bGN7KVa7q0lmqrn4pPheUlcgBQfRlWyRu9rvpAMrnrLfiuqJx2esLGkFsxJAmqy0E7WGmHvtJgThht5cUz82Hi/d6K0HOXLCJ8MlvQoaDgD97MPW38bLPaF1y5yZW7SH8dh/A9w5+Vt6sU48tudf6rxhGShvPVBHVB3xuDCK3Rc4Sj7d87oDgglaRQo3vFP1EpHzehS8ygy3NpJVnMUNBUVOQNiqR/qRcj/GR/nEwH3+bNyG6I/Hqh9GR/OULWusPgukHK8AEUM/s8lnSEhoou7V5c4qMyz9q27VrFBN0aJWC+/req180Nxj1zwhDVxgg87GI5Ca6I86Z5AzBP85qd9+fIkgH3qs5ZMCAeNSgGk9d5TUnMb2XnFxs7EG6GF5q2uC9/q7hrUC9BUq8orpv/tzmSveW9dgvBcpQwVeCCGb0+EVTIicZ+OyrvUlmZ97NPFqQw1YGqtajgFeH9ULlxnFfCF/wPmsa67DvGLZ4F2BHbC2WLk3nu5Qlr1eFEoUe/pgU8+B5EcHQ+pW3jR0QBPi9qe/w49b+SiVggLLxa0UwnGvphmNSrooBzhdQLcnXgnZ+I4M3vvNF1vbw+/MyPhpxmA7xxMo6GlwY4rZuyIRpeR9IbU492q3cY/+HoRhzrNudd/ngYLdkuFy9mfVH2H78yeNGOmhv0Q8Rxun0+R2STm3/MoLNuBuOoCrdlIX+LqTL+oWB26OiHAqfF3fg4An4fOQIGPkWvcopWSqiNfD5nwlFYubOVaSVmTqS6dSXhdIrDhby6+8clBWuNFgRxRMEo5+9RJ32aO+u8b8VnG2hFBcHO6+IGI8chH48x1sZ/Dl7HW2SybuQ6WycI2KzdDgeujQElUEnJohGpKh5IFb+4G6SXab0zJEQ/Gwp2qJtKCuznj5A4sP9Sr83UfThcMzPEGFxWSgR7ZQXTW8Egfml3rrXAlaSCX0hsTBXM4hmZ4SL2pedFVX8Hmyu8XZZp3sAlfeAn+o5FOeDzflCYn74AQLQOlAZg9YPcXR5Z+lMprYHTHwUzHcXmhaYNYLQ1Ws1V8vhiSAjYAxUgz7Xx9DQyv8hh2AbmdxGfYstmricUKjb5OWjfIKYDBWp60Xq76FZMiB3DJu6mT3TGtI1wqFUz5TLnK/t9bXZj4cjqHvu1oy6wuvKOTIV6DcaarsiJH1QmJVsfHjFz51lkrIekAA9HkwdGFmWFO3mExmjfEQN7AfyjgzT7rgHZlZchTpwFEp06WZZiPN2Qk5VOT9A== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230040)(376014)(36860700013)(35042699022)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2024 12:09:51.8030 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c765bc3e-8651-438d-19b3-08dce211f423 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF00028D01.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI0PR08MB11083 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, KAM_SHORT, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org The AArch64 FEAT_FAMINMAX extension introduces instructions for computing the floating point absolute maximum and minimum of the two vectors element-wise. This patch introduces SVE2 faminmax intrinsics. The intrinsics of this extension are implemented as the following builtin functions: * sva[max|min]_[m|x|z] * sva[max|min]_[f16|f32|f64]_[m|x|z] * sva[max|min]_n_[f16|f32|f64]_[m|x|z] gcc/ChangeLog: * config/aarch64/aarch64-sve-builtins-base.cc (svamax): Absolute maximum declaration. (svamin): Absolute minimum declaration. * config/aarch64/aarch64-sve-builtins-base.def (REQUIRED_EXTENSIONS): Add faminmax intrinsics behind a flag. (svamax): Absolute maximum declaration. (svamin): Absolute minimum declaration. * config/aarch64/aarch64-sve-builtins-base.h: Declaring function bases for the new intrinsics. * config/aarch64/aarch64.h (TARGET_SVE_FAMINMAX): New flag for SVE2 faminmax. * config/aarch64/iterators.md: New unspecs, iterators, and attrs for the new intrinsics. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve2/acle/asm/amax_f16.c: New test. * gcc.target/aarch64/sve2/acle/asm/amax_f32.c: New test. * gcc.target/aarch64/sve2/acle/asm/amax_f64.c: New test. * gcc.target/aarch64/sve2/acle/asm/amin_f16.c: New test. * gcc.target/aarch64/sve2/acle/asm/amin_f32.c: New test. * gcc.target/aarch64/sve2/acle/asm/amin_f64.c: New test. --- .../aarch64/aarch64-sve-builtins-base.cc | 4 + .../aarch64/aarch64-sve-builtins-base.def | 5 + .../aarch64/aarch64-sve-builtins-base.h | 2 + gcc/config/aarch64/aarch64.h | 1 + gcc/config/aarch64/iterators.md | 40 +++-- .../aarch64/sve2/acle/asm/amax_f16.c | 142 ++++++++++++++++++ .../aarch64/sve2/acle/asm/amax_f32.c | 142 ++++++++++++++++++ .../aarch64/sve2/acle/asm/amax_f64.c | 142 ++++++++++++++++++ .../aarch64/sve2/acle/asm/amin_f16.c | 142 ++++++++++++++++++ .../aarch64/sve2/acle/asm/amin_f32.c | 142 ++++++++++++++++++ .../aarch64/sve2/acle/asm/amin_f64.c | 142 ++++++++++++++++++ 11 files changed, 893 insertions(+), 11 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f64.c diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc index afce52a7e8d..dd4efdf6ca5 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc @@ -3070,6 +3070,10 @@ FUNCTION (svadrb, svadr_bhwd_impl, (0)) FUNCTION (svadrd, svadr_bhwd_impl, (3)) FUNCTION (svadrh, svadr_bhwd_impl, (1)) FUNCTION (svadrw, svadr_bhwd_impl, (2)) +FUNCTION (svamax, cond_or_uncond_unspec_function, + (UNSPEC_COND_FAMAX, UNSPEC_FAMAX)) +FUNCTION (svamin, cond_or_uncond_unspec_function, + (UNSPEC_COND_FAMIN, UNSPEC_FAMIN)) FUNCTION (svand, rtx_code_function, (AND, AND)) FUNCTION (svandv, reduction, (UNSPEC_ANDV)) FUNCTION (svasr, rtx_code_function, (ASHIFTRT, ASHIFTRT)) diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.def b/gcc/config/aarch64/aarch64-sve-builtins-base.def index 65fcba91586..95e04e4393d 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-base.def +++ b/gcc/config/aarch64/aarch64-sve-builtins-base.def @@ -379,3 +379,8 @@ DEF_SVE_FUNCTION (svzip2q, binary, all_data, none) DEF_SVE_FUNCTION (svld1ro, load_replicate, all_data, implicit) DEF_SVE_FUNCTION (svmmla, mmla, d_float, none) #undef REQUIRED_EXTENSIONS + +#define REQUIRED_EXTENSIONS AARCH64_FL_SVE | AARCH64_FL_FAMINMAX +DEF_SVE_FUNCTION (svamax, binary_opt_single_n, all_float, mxz) +DEF_SVE_FUNCTION (svamin, binary_opt_single_n, all_float, mxz) +#undef REQUIRED_EXTENSIONS diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.h b/gcc/config/aarch64/aarch64-sve-builtins-base.h index 5bbf3569c4b..978cf7013f9 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-base.h +++ b/gcc/config/aarch64/aarch64-sve-builtins-base.h @@ -37,6 +37,8 @@ namespace aarch64_sve extern const function_base *const svadrd; extern const function_base *const svadrh; extern const function_base *const svadrw; + extern const function_base *const svamax; + extern const function_base *const svamin; extern const function_base *const svand; extern const function_base *const svandv; extern const function_base *const svasr; diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 43819adb48c..a496235db42 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -470,6 +470,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED /* Floating Point Absolute Maximum/Minimum extension instructions are enabled through +faminmax. */ #define TARGET_FAMINMAX AARCH64_HAVE_ISA (FAMINMAX) +#define TARGET_SVE_FAMINMAX (TARGET_SVE && TARGET_FAMINMAX) /* Prefer different predicate registers for the output of a predicated operation over re-using an existing input predicate. */ diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index c2fcd18306e..cf9ee2639a9 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -841,6 +841,8 @@ UNSPEC_COND_CMPNE_WIDE ; Used in aarch64-sve.md. UNSPEC_COND_FABS ; Used in aarch64-sve.md. UNSPEC_COND_FADD ; Used in aarch64-sve.md. + UNSPEC_COND_FAMAX ; Used in aarch64-sve.md. + UNSPEC_COND_FAMIN ; Used in aarch64-sve.md. UNSPEC_COND_FCADD90 ; Used in aarch64-sve.md. UNSPEC_COND_FCADD270 ; Used in aarch64-sve.md. UNSPEC_COND_FCMEQ ; Used in aarch64-sve.md. @@ -3081,15 +3083,18 @@ (define_int_iterator SVE_COND_FCVTI [UNSPEC_COND_FCVTZS UNSPEC_COND_FCVTZU]) (define_int_iterator SVE_COND_ICVTF [UNSPEC_COND_SCVTF UNSPEC_COND_UCVTF]) -(define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_FADD - UNSPEC_COND_FDIV - UNSPEC_COND_FMAX - UNSPEC_COND_FMAXNM - UNSPEC_COND_FMIN - UNSPEC_COND_FMINNM - UNSPEC_COND_FMUL - UNSPEC_COND_FMULX - UNSPEC_COND_FSUB]) +(define_int_iterator SVE_COND_FP_BINARY + [UNSPEC_COND_FADD + (UNSPEC_COND_FAMAX "TARGET_SVE_FAMINMAX") + (UNSPEC_COND_FAMIN "TARGET_SVE_FAMINMAX") + UNSPEC_COND_FDIV + UNSPEC_COND_FMAX + UNSPEC_COND_FMAXNM + UNSPEC_COND_FMIN + UNSPEC_COND_FMINNM + UNSPEC_COND_FMUL + UNSPEC_COND_FMULX + UNSPEC_COND_FSUB]) ;; Same as SVE_COND_FP_BINARY, but without codes that have a dedicated ;; 3 expander. @@ -3114,8 +3119,11 @@ UNSPEC_COND_FMINNM UNSPEC_COND_FMUL]) -(define_int_iterator SVE_COND_FP_BINARY_REG [UNSPEC_COND_FDIV - UNSPEC_COND_FMULX]) +(define_int_iterator SVE_COND_FP_BINARY_REG + [(UNSPEC_COND_FAMAX "TARGET_SVE_FAMINMAX") + (UNSPEC_COND_FAMIN "TARGET_SVE_FAMINMAX") + UNSPEC_COND_FDIV + UNSPEC_COND_FMULX]) (define_int_iterator SVE_COND_FCADD [UNSPEC_COND_FCADD90 UNSPEC_COND_FCADD270]) @@ -3694,6 +3702,8 @@ (UNSPEC_ZIP2Q "zip2q") (UNSPEC_COND_FABS "abs") (UNSPEC_COND_FADD "add") + (UNSPEC_COND_FAMAX "famax") + (UNSPEC_COND_FAMIN "famin") (UNSPEC_COND_FCADD90 "cadd90") (UNSPEC_COND_FCADD270 "cadd270") (UNSPEC_COND_FCMLA "fcmla") @@ -4230,6 +4240,8 @@ (UNSPEC_FTSSEL "ftssel") (UNSPEC_COND_FABS "fabs") (UNSPEC_COND_FADD "fadd") + (UNSPEC_COND_FAMAX "famax") + (UNSPEC_COND_FAMIN "famin") (UNSPEC_COND_FCVTLT "fcvtlt") (UNSPEC_COND_FCVTX "fcvtx") (UNSPEC_COND_FDIV "fdiv") @@ -4254,6 +4266,8 @@ (UNSPEC_COND_FSUB "fsub")]) (define_int_attr sve_fp_op_rev [(UNSPEC_COND_FADD "fadd") + (UNSPEC_COND_FAMAX "famax") + (UNSPEC_COND_FAMIN "famin") (UNSPEC_COND_FDIV "fdivr") (UNSPEC_COND_FMAX "fmax") (UNSPEC_COND_FMAXNM "fmaxnm") @@ -4390,6 +4404,8 @@ ;; 3 pattern. (define_int_attr sve_pred_fp_rhs1_operand [(UNSPEC_COND_FADD "register_operand") + (UNSPEC_COND_FAMAX "register_operand") + (UNSPEC_COND_FAMIN "register_operand") (UNSPEC_COND_FDIV "register_operand") (UNSPEC_COND_FMAX "register_operand") (UNSPEC_COND_FMAXNM "register_operand") @@ -4403,6 +4419,8 @@ ;; 3 pattern. (define_int_attr sve_pred_fp_rhs2_operand [(UNSPEC_COND_FADD "aarch64_sve_float_arith_with_sub_operand") + (UNSPEC_COND_FAMAX "aarch64_sve_float_maxmin_operand") + (UNSPEC_COND_FAMIN "aarch64_sve_float_maxmin_operand") (UNSPEC_COND_FDIV "register_operand") (UNSPEC_COND_FMAX "aarch64_sve_float_maxmin_operand") (UNSPEC_COND_FMAXNM "aarch64_sve_float_maxmin_operand") diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f16.c new file mode 100644 index 00000000000..e5681a0733e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f16.c @@ -0,0 +1,142 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ +#include "test_sve_acle.h" + +#pragma GCC target "+sve+faminmax" + +/* +** amax_f16_m_tied1: +** famax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (amax_f16_m_tied1, svfloat16_t, + z0 = svamax_f16_m (p0, z0, z1), + z0 = svamax_m (p0, z0, z1)) +/* +** amax_f16_m_tied2: +** mov z31\.d, z0\.d +** movprfx z0, z1 +** famax z0\.h, p0/m, z0\.h, z31\.h +** ret +*/ +TEST_UNIFORM_Z (amax_f16_m_tied2, svfloat16_t, + z0 = svamax_f16_m (p0, z1, z0), + z0 = svamax_m (p0, z1, z0)) +/* +** amax_f16_m_untied: +** movprfx z0, z1 +** famax z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (amax_f16_m_untied, svfloat16_t, + z0 = svamax_f16_m (p0, z1, z2), + z0 = svamax_m (p0, z1, z2)) +/* +** amax_f16_x_tied1: +** famax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (amax_f16_x_tied1, svfloat16_t, + z0 = svamax_f16_x (p0, z0, z1), + z0 = svamax_x (p0, z0, z1)) +/* +** amax_f16_x_tied2: +** famax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (amax_f16_x_tied2, svfloat16_t, + z0 = svamax_f16_x (p0, z1, z0), + z0 = svamax_x (p0, z1, z0)) +/* +** amax_f16_x_untied: +** movprfx z0, z1 +** famax z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (amax_f16_x_untied, svfloat16_t, + z0 = svamax_f16_x (p0, z1, z2), + z0 = svamax_x (p0, z1, z2)) +/* +** amax_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** famax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (amax_f16_z_tied1, svfloat16_t, + z0 = svamax_f16_z (p0, z0, z1), + z0 = svamax_z (p0, z0, z1)) +/* +** amax_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** famax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (amax_f16_z_tied2, svfloat16_t, + z0 = svamax_f16_z (p0, z1, z0), + z0 = svamax_z (p0, z1, z0)) +/* +** amax_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** famax z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (amax_f16_z_untied, svfloat16_t, + z0 = svamax_f16_z (p0, z1, z2), + z0 = svamax_z (p0, z1, z2)) +/* +** amax_n_f16_m_tied1: +** mov z7\.h, h7 +** famax z0\.h, p0/m, z0\.h, z7\.h +** ret +*/ +TEST_DUAL_ZD (amax_n_f16_m_tied1, svfloat16_t, svfloat16_t, float16_t, + z0 = svamax_n_f16_m (p0, z0, d7), + z0 = svamax_m (p0, z0, d7)) +/* +** amax_n_f16_m_untied: +** mov z7\.h, h7 +** movprfx z0, z4 +** famax z0\.h, p0/m, z0\.h, z7\.h +** ret +*/ +TEST_DUAL_ZD (amax_n_f16_m_untied, svfloat16_t, svfloat16_t, float16_t, + z0 = svamax_n_f16_m (p0, z4, d7), + z0 = svamax_m (p0, z4, d7)) +/* +** amax_n_f16_x_tied1: +** mov z7\.h, h7 +** famax z0\.h, p0/m, z0\.h, z7\.h +** ret +*/ +TEST_DUAL_ZD (amax_n_f16_x_tied1, svfloat16_t, svfloat16_t, float16_t, + z0 = svamax_n_f16_x (p0, z0, d7), + z0 = svamax_x (p0, z0, d7)) +/* +** amax_n_f16_x_untied: +** mov z0\.h, h7 +** famax z0\.h, p0/m, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_ZD (amax_n_f16_x_untied, svfloat16_t, svfloat16_t, float16_t, + z0 = svamax_n_f16_x (p0, z4, d7), + z0 = svamax_x (p0, z4, d7)) +/* +** amax_n_f16_z_tied1: +** mov z7\.h, h7 +** movprfx z0\.h, p0/z, z0\.h +** famax z0\.h, p0/m, z0\.h, z7\.h +** ret +*/ +TEST_DUAL_ZD (amax_n_f16_z_tied1, svfloat16_t, svfloat16_t, float16_t, + z0 = svamax_n_f16_z (p0, z0, d7), + z0 = svamax_z (p0, z0, d7)) +/* +** amax_n_f16_z_untied: +** mov z7\.h, h7 +** movprfx z0\.h, p0/z, z4\.h +** famax z0\.h, p0/m, z0\.h, z7\.h +** ret +*/ +TEST_DUAL_ZD (amax_n_f16_z_untied, svfloat16_t, svfloat16_t, float16_t, + z0 = svamax_n_f16_z (p0, z4, d7), + z0 = svamax_z (p0, z4, d7)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f32.c new file mode 100644 index 00000000000..ac6fd227b52 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f32.c @@ -0,0 +1,142 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ +#include "test_sve_acle.h" + +#pragma GCC target "+sve+faminmax" + +/* +** amax_f32_m_tied1: +** famax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (amax_f32_m_tied1, svfloat32_t, + z0 = svamax_f32_m (p0, z0, z1), + z0 = svamax_m (p0, z0, z1)) +/* +** amax_f32_m_tied2: +** mov z31\.d, z0\.d +** movprfx z0, z1 +** famax z0\.s, p0/m, z0\.s, z31\.s +** ret +*/ +TEST_UNIFORM_Z (amax_f32_m_tied2, svfloat32_t, + z0 = svamax_f32_m (p0, z1, z0), + z0 = svamax_m (p0, z1, z0)) +/* +** amax_f32_m_untied: +** movprfx z0, z1 +** famax z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (amax_f32_m_untied, svfloat32_t, + z0 = svamax_f32_m (p0, z1, z2), + z0 = svamax_m (p0, z1, z2)) +/* +** amax_f32_x_tied1: +** famax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (amax_f32_x_tied1, svfloat32_t, + z0 = svamax_f32_x (p0, z0, z1), + z0 = svamax_x (p0, z0, z1)) +/* +** amax_f32_x_tied2: +** famax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (amax_f32_x_tied2, svfloat32_t, + z0 = svamax_f32_x (p0, z1, z0), + z0 = svamax_x (p0, z1, z0)) +/* +** amax_f32_x_untied: +** movprfx z0, z1 +** famax z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (amax_f32_x_untied, svfloat32_t, + z0 = svamax_f32_x (p0, z1, z2), + z0 = svamax_x (p0, z1, z2)) +/* +** amax_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** famax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (amax_f32_z_tied1, svfloat32_t, + z0 = svamax_f32_z (p0, z0, z1), + z0 = svamax_z (p0, z0, z1)) +/* +** amax_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** famax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (amax_f32_z_tied2, svfloat32_t, + z0 = svamax_f32_z (p0, z1, z0), + z0 = svamax_z (p0, z1, z0)) +/* +** amax_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** famax z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (amax_f32_z_untied, svfloat32_t, + z0 = svamax_f32_z (p0, z1, z2), + z0 = svamax_z (p0, z1, z2)) +/* +** amax_n_f32_m_tied1: +** mov z7\.s, s7 +** famax z0\.s, p0/m, z0\.s, z7\.s +** ret +*/ +TEST_DUAL_ZD (amax_n_f32_m_tied1, svfloat32_t, svfloat32_t, float32_t, + z0 = svamax_n_f32_m (p0, z0, d7), + z0 = svamax_m (p0, z0, d7)) +/* +** amax_n_f32_m_untied: +** mov z7\.s, s7 +** movprfx z0, z4 +** famax z0\.s, p0/m, z0\.s, z7\.s +** ret +*/ +TEST_DUAL_ZD (amax_n_f32_m_untied, svfloat32_t, svfloat32_t, float32_t, + z0 = svamax_n_f32_m (p0, z4, d7), + z0 = svamax_m (p0, z4, d7)) +/* +** amax_n_f32_x_tied1: +** mov z7\.s, s7 +** famax z0\.s, p0/m, z0\.s, z7\.s +** ret +*/ +TEST_DUAL_ZD (amax_n_f32_x_tied1, svfloat32_t, svfloat32_t, float32_t, + z0 = svamax_n_f32_x (p0, z0, d7), + z0 = svamax_x (p0, z0, d7)) +/* +** amax_n_f32_x_untied: +** mov z0\.s, s7 +** famax z0\.s, p0/m, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_ZD (amax_n_f32_x_untied, svfloat32_t, svfloat32_t, float32_t, + z0 = svamax_n_f32_x (p0, z4, d7), + z0 = svamax_x (p0, z4, d7)) +/* +** amax_n_f32_z_tied1: +** mov z7\.s, s7 +** movprfx z0\.s, p0/z, z0\.s +** famax z0\.s, p0/m, z0\.s, z7\.s +** ret +*/ +TEST_DUAL_ZD (amax_n_f32_z_tied1, svfloat32_t, svfloat32_t, float32_t, + z0 = svamax_n_f32_z (p0, z0, d7), + z0 = svamax_z (p0, z0, d7)) +/* +** amax_n_f32_z_untied: +** mov z7\.s, s7 +** movprfx z0\.s, p0/z, z4\.s +** famax z0\.s, p0/m, z0\.s, z7\.s +** ret +*/ +TEST_DUAL_ZD (amax_n_f32_z_untied, svfloat32_t, svfloat32_t, float32_t, + z0 = svamax_n_f32_z (p0, z4, d7), + z0 = svamax_z (p0, z4, d7)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f64.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f64.c new file mode 100644 index 00000000000..9e711674ea5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f64.c @@ -0,0 +1,142 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ +#include "test_sve_acle.h" + +#pragma GCC target "+sve+faminmax" + +/* +** amax_f64_m_tied1: +** famax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (amax_f64_m_tied1, svfloat64_t, + z0 = svamax_f64_m (p0, z0, z1), + z0 = svamax_m (p0, z0, z1)) +/* +** amax_f64_m_tied2: +** mov z31\.d, z0\.d +** movprfx z0, z1 +** famax z0\.d, p0/m, z0\.d, z31\.d +** ret +*/ +TEST_UNIFORM_Z (amax_f64_m_tied2, svfloat64_t, + z0 = svamax_f64_m (p0, z1, z0), + z0 = svamax_m (p0, z1, z0)) +/* +** amax_f64_m_untied: +** movprfx z0, z1 +** famax z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (amax_f64_m_untied, svfloat64_t, + z0 = svamax_f64_m (p0, z1, z2), + z0 = svamax_m (p0, z1, z2)) +/* +** amax_f64_x_tied1: +** famax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (amax_f64_x_tied1, svfloat64_t, + z0 = svamax_f64_x (p0, z0, z1), + z0 = svamax_x (p0, z0, z1)) +/* +** amax_f64_x_tied2: +** famax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (amax_f64_x_tied2, svfloat64_t, + z0 = svamax_f64_x (p0, z1, z0), + z0 = svamax_x (p0, z1, z0)) +/* +** amax_f64_x_untied: +** movprfx z0, z1 +** famax z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (amax_f64_x_untied, svfloat64_t, + z0 = svamax_f64_x (p0, z1, z2), + z0 = svamax_x (p0, z1, z2)) +/* +** amax_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** famax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (amax_f64_z_tied1, svfloat64_t, + z0 = svamax_f64_z (p0, z0, z1), + z0 = svamax_z (p0, z0, z1)) +/* +** amax_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** famax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (amax_f64_z_tied2, svfloat64_t, + z0 = svamax_f64_z (p0, z1, z0), + z0 = svamax_z (p0, z1, z0)) +/* +** amax_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** famax z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (amax_f64_z_untied, svfloat64_t, + z0 = svamax_f64_z (p0, z1, z2), + z0 = svamax_z (p0, z1, z2)) +/* +** amax_n_f64_m_tied1: +** mov z7\.d, d7 +** famax z0\.d, p0/m, z0\.d, z7\.d +** ret +*/ +TEST_DUAL_ZD (amax_n_f64_m_tied1, svfloat64_t, svfloat64_t, float64_t, + z0 = svamax_n_f64_m (p0, z0, d7), + z0 = svamax_m (p0, z0, d7)) +/* +** amax_n_f64_m_untied: +** mov z7\.d, d7 +** movprfx z0, z4 +** famax z0\.d, p0/m, z0\.d, z7\.d +** ret +*/ +TEST_DUAL_ZD (amax_n_f64_m_untied, svfloat64_t, svfloat64_t, float64_t, + z0 = svamax_n_f64_m (p0, z4, d7), + z0 = svamax_m (p0, z4, d7)) +/* +** amax_n_f64_x_tied1: +** mov z7\.d, d7 +** famax z0\.d, p0/m, z0\.d, z7\.d +** ret +*/ +TEST_DUAL_ZD (amax_n_f64_x_tied1, svfloat64_t, svfloat64_t, float64_t, + z0 = svamax_n_f64_x (p0, z0, d7), + z0 = svamax_x (p0, z0, d7)) +/* +** amax_n_f64_x_untied: +** mov z0\.d, d7 +** famax z0\.d, p0/m, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_ZD (amax_n_f64_x_untied, svfloat64_t, svfloat64_t, float64_t, + z0 = svamax_n_f64_x (p0, z4, d7), + z0 = svamax_x (p0, z4, d7)) +/* +** amax_n_f64_z_tied1: +** mov z7\.d, d7 +** movprfx z0\.d, p0/z, z0\.d +** famax z0\.d, p0/m, z0\.d, z7\.d +** ret +*/ +TEST_DUAL_ZD (amax_n_f64_z_tied1, svfloat64_t, svfloat64_t, float64_t, + z0 = svamax_n_f64_z (p0, z0, d7), + z0 = svamax_z (p0, z0, d7)) +/* +** amax_n_f64_z_untied: +** mov z7\.d, d7 +** movprfx z0\.d, p0/z, z4\.d +** famax z0\.d, p0/m, z0\.d, z7\.d +** ret +*/ +TEST_DUAL_ZD (amax_n_f64_z_untied, svfloat64_t, svfloat64_t, float64_t, + z0 = svamax_n_f64_z (p0, z4, d7), + z0 = svamax_z (p0, z4, d7)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f16.c new file mode 100644 index 00000000000..3c949df023c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f16.c @@ -0,0 +1,142 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ +#include "test_sve_acle.h" + +#pragma GCC target "+sve+faminmax" + +/* +** amin_f16_m_tied1: +** famin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (amin_f16_m_tied1, svfloat16_t, + z0 = svamin_f16_m (p0, z0, z1), + z0 = svamin_m (p0, z0, z1)) +/* +** amin_f16_m_tied2: +** mov z31\.d, z0\.d +** movprfx z0, z1 +** famin z0\.h, p0/m, z0\.h, z31\.h +** ret +*/ +TEST_UNIFORM_Z (amin_f16_m_tied2, svfloat16_t, + z0 = svamin_f16_m (p0, z1, z0), + z0 = svamin_m (p0, z1, z0)) +/* +** amin_f16_m_untied: +** movprfx z0, z1 +** famin z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (amin_f16_m_untied, svfloat16_t, + z0 = svamin_f16_m (p0, z1, z2), + z0 = svamin_m (p0, z1, z2)) +/* +** amin_f16_x_tied1: +** famin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (amin_f16_x_tied1, svfloat16_t, + z0 = svamin_f16_x (p0, z0, z1), + z0 = svamin_x (p0, z0, z1)) +/* +** amin_f16_x_tied2: +** famin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (amin_f16_x_tied2, svfloat16_t, + z0 = svamin_f16_x (p0, z1, z0), + z0 = svamin_x (p0, z1, z0)) +/* +** amin_f16_x_untied: +** movprfx z0, z1 +** famin z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (amin_f16_x_untied, svfloat16_t, + z0 = svamin_f16_x (p0, z1, z2), + z0 = svamin_x (p0, z1, z2)) +/* +** amin_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** famin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (amin_f16_z_tied1, svfloat16_t, + z0 = svamin_f16_z (p0, z0, z1), + z0 = svamin_z (p0, z0, z1)) +/* +** amin_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** famin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (amin_f16_z_tied2, svfloat16_t, + z0 = svamin_f16_z (p0, z1, z0), + z0 = svamin_z (p0, z1, z0)) +/* +** amin_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** famin z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (amin_f16_z_untied, svfloat16_t, + z0 = svamin_f16_z (p0, z1, z2), + z0 = svamin_z (p0, z1, z2)) +/* +** amin_n_f16_m_tied1: +** mov z7\.h, h7 +** famin z0\.h, p0/m, z0\.h, z7\.h +** ret +*/ +TEST_DUAL_ZD (amin_n_f16_m_tied1, svfloat16_t, svfloat16_t, float16_t, + z0 = svamin_n_f16_m (p0, z0, d7), + z0 = svamin_m (p0, z0, d7)) +/* +** amin_n_f16_m_untied: +** mov z7\.h, h7 +** movprfx z0, z4 +** famin z0\.h, p0/m, z0\.h, z7\.h +** ret +*/ +TEST_DUAL_ZD (amin_n_f16_m_untied, svfloat16_t, svfloat16_t, float16_t, + z0 = svamin_n_f16_m (p0, z4, d7), + z0 = svamin_m (p0, z4, d7)) +/* +** amin_n_f16_x_tied1: +** mov z7\.h, h7 +** famin z0\.h, p0/m, z0\.h, z7\.h +** ret +*/ +TEST_DUAL_ZD (amin_n_f16_x_tied1, svfloat16_t, svfloat16_t, float16_t, + z0 = svamin_n_f16_x (p0, z0, d7), + z0 = svamin_x (p0, z0, d7)) +/* +** amin_n_f16_x_untied: +** mov z0\.h, h7 +** famin z0\.h, p0/m, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_ZD (amin_n_f16_x_untied, svfloat16_t, svfloat16_t, float16_t, + z0 = svamin_n_f16_x (p0, z4, d7), + z0 = svamin_x (p0, z4, d7)) +/* +** amin_n_f16_z_tied1: +** mov z7\.h, h7 +** movprfx z0\.h, p0/z, z0\.h +** famin z0\.h, p0/m, z0\.h, z7\.h +** ret +*/ +TEST_DUAL_ZD (amin_n_f16_z_tied1, svfloat16_t, svfloat16_t, float16_t, + z0 = svamin_n_f16_z (p0, z0, d7), + z0 = svamin_z (p0, z0, d7)) +/* +** amin_n_f16_z_untied: +** mov z7\.h, h7 +** movprfx z0\.h, p0/z, z4\.h +** famin z0\.h, p0/m, z0\.h, z7\.h +** ret +*/ +TEST_DUAL_ZD (amin_n_f16_z_untied, svfloat16_t, svfloat16_t, float16_t, + z0 = svamin_n_f16_z (p0, z4, d7), + z0 = svamin_z (p0, z4, d7)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f32.c new file mode 100644 index 00000000000..b606c448ea6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f32.c @@ -0,0 +1,142 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ +#include "test_sve_acle.h" + +#pragma GCC target "+sve+faminmax" + +/* +** amin_f32_m_tied1: +** famin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (amin_f32_m_tied1, svfloat32_t, + z0 = svamin_f32_m (p0, z0, z1), + z0 = svamin_m (p0, z0, z1)) +/* +** amin_f32_m_tied2: +** mov z31\.d, z0\.d +** movprfx z0, z1 +** famin z0\.s, p0/m, z0\.s, z31\.s +** ret +*/ +TEST_UNIFORM_Z (amin_f32_m_tied2, svfloat32_t, + z0 = svamin_f32_m (p0, z1, z0), + z0 = svamin_m (p0, z1, z0)) +/* +** amin_f32_m_untied: +** movprfx z0, z1 +** famin z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (amin_f32_m_untied, svfloat32_t, + z0 = svamin_f32_m (p0, z1, z2), + z0 = svamin_m (p0, z1, z2)) +/* +** amin_f32_x_tied1: +** famin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (amin_f32_x_tied1, svfloat32_t, + z0 = svamin_f32_x (p0, z0, z1), + z0 = svamin_x (p0, z0, z1)) +/* +** amin_f32_x_tied2: +** famin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (amin_f32_x_tied2, svfloat32_t, + z0 = svamin_f32_x (p0, z1, z0), + z0 = svamin_x (p0, z1, z0)) +/* +** amin_f32_x_untied: +** movprfx z0, z1 +** famin z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (amin_f32_x_untied, svfloat32_t, + z0 = svamin_f32_x (p0, z1, z2), + z0 = svamin_x (p0, z1, z2)) +/* +** amin_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** famin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (amin_f32_z_tied1, svfloat32_t, + z0 = svamin_f32_z (p0, z0, z1), + z0 = svamin_z (p0, z0, z1)) +/* +** amin_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** famin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (amin_f32_z_tied2, svfloat32_t, + z0 = svamin_f32_z (p0, z1, z0), + z0 = svamin_z (p0, z1, z0)) +/* +** amin_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** famin z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (amin_f32_z_untied, svfloat32_t, + z0 = svamin_f32_z (p0, z1, z2), + z0 = svamin_z (p0, z1, z2)) +/* +** amin_n_f32_m_tied1: +** mov z7\.s, s7 +** famin z0\.s, p0/m, z0\.s, z7\.s +** ret +*/ +TEST_DUAL_ZD (amin_n_f32_m_tied1, svfloat32_t, svfloat32_t, float32_t, + z0 = svamin_n_f32_m (p0, z0, d7), + z0 = svamin_m (p0, z0, d7)) +/* +** amin_n_f32_m_untied: +** mov z7\.s, s7 +** movprfx z0, z4 +** famin z0\.s, p0/m, z0\.s, z7\.s +** ret +*/ +TEST_DUAL_ZD (amin_n_f32_m_untied, svfloat32_t, svfloat32_t, float32_t, + z0 = svamin_n_f32_m (p0, z4, d7), + z0 = svamin_m (p0, z4, d7)) +/* +** amin_n_f32_x_tied1: +** mov z7\.s, s7 +** famin z0\.s, p0/m, z0\.s, z7\.s +** ret +*/ +TEST_DUAL_ZD (amin_n_f32_x_tied1, svfloat32_t, svfloat32_t, float32_t, + z0 = svamin_n_f32_x (p0, z0, d7), + z0 = svamin_x (p0, z0, d7)) +/* +** amin_n_f32_x_untied: +** mov z0\.s, s7 +** famin z0\.s, p0/m, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_ZD (amin_n_f32_x_untied, svfloat32_t, svfloat32_t, float32_t, + z0 = svamin_n_f32_x (p0, z4, d7), + z0 = svamin_x (p0, z4, d7)) +/* +** amin_n_f32_z_tied1: +** mov z7\.s, s7 +** movprfx z0\.s, p0/z, z0\.s +** famin z0\.s, p0/m, z0\.s, z7\.s +** ret +*/ +TEST_DUAL_ZD (amin_n_f32_z_tied1, svfloat32_t, svfloat32_t, float32_t, + z0 = svamin_n_f32_z (p0, z0, d7), + z0 = svamin_z (p0, z0, d7)) +/* +** amin_n_f32_z_untied: +** mov z7\.s, s7 +** movprfx z0\.s, p0/z, z4\.s +** famin z0\.s, p0/m, z0\.s, z7\.s +** ret +*/ +TEST_DUAL_ZD (amin_n_f32_z_untied, svfloat32_t, svfloat32_t, float32_t, + z0 = svamin_n_f32_z (p0, z4, d7), + z0 = svamin_z (p0, z4, d7)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f64.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f64.c new file mode 100644 index 00000000000..d91b7200c18 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f64.c @@ -0,0 +1,142 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ +#include "test_sve_acle.h" + +#pragma GCC target "+sve+faminmax" + +/* +** amin_f64_m_tied1: +** famin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (amin_f64_m_tied1, svfloat64_t, + z0 = svamin_f64_m (p0, z0, z1), + z0 = svamin_m (p0, z0, z1)) +/* +** amin_f64_m_tied2: +** mov z31\.d, z0\.d +** movprfx z0, z1 +** famin z0\.d, p0/m, z0\.d, z31\.d +** ret +*/ +TEST_UNIFORM_Z (amin_f64_m_tied2, svfloat64_t, + z0 = svamin_f64_m (p0, z1, z0), + z0 = svamin_m (p0, z1, z0)) +/* +** amin_f64_m_untied: +** movprfx z0, z1 +** famin z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (amin_f64_m_untied, svfloat64_t, + z0 = svamin_f64_m (p0, z1, z2), + z0 = svamin_m (p0, z1, z2)) +/* +** amin_f64_x_tied1: +** famin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (amin_f64_x_tied1, svfloat64_t, + z0 = svamin_f64_x (p0, z0, z1), + z0 = svamin_x (p0, z0, z1)) +/* +** amin_f64_x_tied2: +** famin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (amin_f64_x_tied2, svfloat64_t, + z0 = svamin_f64_x (p0, z1, z0), + z0 = svamin_x (p0, z1, z0)) +/* +** amin_f64_x_untied: +** movprfx z0, z1 +** famin z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (amin_f64_x_untied, svfloat64_t, + z0 = svamin_f64_x (p0, z1, z2), + z0 = svamin_x (p0, z1, z2)) +/* +** amin_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** famin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (amin_f64_z_tied1, svfloat64_t, + z0 = svamin_f64_z (p0, z0, z1), + z0 = svamin_z (p0, z0, z1)) +/* +** amin_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** famin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (amin_f64_z_tied2, svfloat64_t, + z0 = svamin_f64_z (p0, z1, z0), + z0 = svamin_z (p0, z1, z0)) +/* +** amin_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** famin z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (amin_f64_z_untied, svfloat64_t, + z0 = svamin_f64_z (p0, z1, z2), + z0 = svamin_z (p0, z1, z2)) +/* +** amin_n_f64_m_tied1: +** mov z7\.d, d7 +** famin z0\.d, p0/m, z0\.d, z7\.d +** ret +*/ +TEST_DUAL_ZD (amin_n_f64_m_tied1, svfloat64_t, svfloat64_t, float64_t, + z0 = svamin_n_f64_m (p0, z0, d7), + z0 = svamin_m (p0, z0, d7)) +/* +** amin_n_f64_m_untied: +** mov z7\.d, d7 +** movprfx z0, z4 +** famin z0\.d, p0/m, z0\.d, z7\.d +** ret +*/ +TEST_DUAL_ZD (amin_n_f64_m_untied, svfloat64_t, svfloat64_t, float64_t, + z0 = svamin_n_f64_m (p0, z4, d7), + z0 = svamin_m (p0, z4, d7)) +/* +** amin_n_f64_x_tied1: +** mov z7\.d, d7 +** famin z0\.d, p0/m, z0\.d, z7\.d +** ret +*/ +TEST_DUAL_ZD (amin_n_f64_x_tied1, svfloat64_t, svfloat64_t, float64_t, + z0 = svamin_n_f64_x (p0, z0, d7), + z0 = svamin_x (p0, z0, d7)) +/* +** amin_n_f64_x_untied: +** mov z0\.d, d7 +** famin z0\.d, p0/m, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_ZD (amin_n_f64_x_untied, svfloat64_t, svfloat64_t, float64_t, + z0 = svamin_n_f64_x (p0, z4, d7), + z0 = svamin_x (p0, z4, d7)) +/* +** amin_n_f64_z_tied1: +** mov z7\.d, d7 +** movprfx z0\.d, p0/z, z0\.d +** famin z0\.d, p0/m, z0\.d, z7\.d +** ret +*/ +TEST_DUAL_ZD (amin_n_f64_z_tied1, svfloat64_t, svfloat64_t, float64_t, + z0 = svamin_n_f64_z (p0, z0, d7), + z0 = svamin_z (p0, z0, d7)) +/* +** amin_n_f64_z_untied: +** mov z7\.d, d7 +** movprfx z0\.d, p0/z, z4\.d +** famin z0\.d, p0/m, z0\.d, z7\.d +** ret +*/ +TEST_DUAL_ZD (amin_n_f64_z_untied, svfloat64_t, svfloat64_t, float64_t, + z0 = svamin_n_f64_z (p0, z4, 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gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Introduce two new unspecs, UNSPEC_COND_SMAX and UNSPEC_COND_SMIN, corresponding to rtl operators smax and smin. UNSPEC_COND_SMAX is used to generate fmaxnm instruction and UNSPEC_COND_SMIN is used to generate fminnm instruction. With these new unspecs, we can generate SVE2 max/min instructions using existing generic unpredicated and predicated instruction patterns that use optab attribute. Thus, we have removed specialised instruction patterns for max/min instructions that were using SVE_COND_FP_MAXMIN_PUBLIC iterator. No new test cases as the existing test cases should be enough to test this refactoring. gcc/ChangeLog: * config/aarch64/aarch64-sve.md (3): Remove this instruction pattern. (cond_): Remove this instruction pattern. * config/aarch64/iterators.md: New unspecs and changes to iterators and attrs to use the new unspecs --- gcc/config/aarch64/aarch64-sve.md | 33 ------------------- gcc/config/aarch64/iterators.md | 55 ++++++++++++++++++++----------- 2 files changed, 35 insertions(+), 53 deletions(-) diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index bfa28849adf..989ba9546d7 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -6600,39 +6600,6 @@ ;; - FMINNM ;; ------------------------------------------------------------------------- -;; Unpredicated fmax/fmin (the libm functions). The optabs for the -;; smax/smin rtx codes are handled in the generic section above. -(define_expand "3" - [(set (match_operand:SVE_FULL_F 0 "register_operand") - (unspec:SVE_FULL_F - [(match_dup 3) - (const_int SVE_RELAXED_GP) - (match_operand:SVE_FULL_F 1 "register_operand") - (match_operand:SVE_FULL_F 2 "aarch64_sve_float_maxmin_operand")] - SVE_COND_FP_MAXMIN_PUBLIC))] - "TARGET_SVE" - { - operands[3] = aarch64_ptrue_reg (mode); - } -) - -;; Predicated fmax/fmin (the libm functions). The optabs for the -;; smax/smin rtx codes are handled in the generic section above. -(define_expand "cond_" - [(set (match_operand:SVE_FULL_F 0 "register_operand") - (unspec:SVE_FULL_F - [(match_operand: 1 "register_operand") - (unspec:SVE_FULL_F - [(match_dup 1) - (const_int SVE_RELAXED_GP) - (match_operand:SVE_FULL_F 2 "register_operand") - (match_operand:SVE_FULL_F 3 "aarch64_sve_float_maxmin_operand")] - SVE_COND_FP_MAXMIN_PUBLIC) - (match_operand:SVE_FULL_F 4 "aarch64_simd_reg_or_zero")] - UNSPEC_SEL))] - "TARGET_SVE" -) - ;; Predicated floating-point maximum/minimum. (define_insn "@aarch64_pred_" [(set (match_operand:SVE_FULL_F 0 "register_operand") diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index cf9ee2639a9..d3a457fc6d9 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -884,6 +884,8 @@ UNSPEC_COND_FSUB ; Used in aarch64-sve.md. UNSPEC_COND_SCVTF ; Used in aarch64-sve.md. UNSPEC_COND_UCVTF ; Used in aarch64-sve.md. + UNSPEC_COND_SMAX ; Used in aarch64-sve.md. + UNSPEC_COND_SMIN ; Used in aarch64-sve.md. UNSPEC_LASTA ; Used in aarch64-sve.md. UNSPEC_LASTB ; Used in aarch64-sve.md. UNSPEC_ASHIFT_WIDE ; Used in aarch64-sve.md. @@ -3094,7 +3096,9 @@ UNSPEC_COND_FMINNM UNSPEC_COND_FMUL UNSPEC_COND_FMULX - UNSPEC_COND_FSUB]) + UNSPEC_COND_FSUB + UNSPEC_COND_SMAX + UNSPEC_COND_SMIN]) ;; Same as SVE_COND_FP_BINARY, but without codes that have a dedicated ;; 3 expander. @@ -3105,7 +3109,9 @@ UNSPEC_COND_FMINNM UNSPEC_COND_FMUL UNSPEC_COND_FMULX - UNSPEC_COND_FSUB]) + UNSPEC_COND_FSUB + UNSPEC_COND_SMAX + UNSPEC_COND_SMIN]) (define_int_iterator SVE_COND_FP_BINARY_INT [UNSPEC_COND_FSCALE]) @@ -3117,13 +3123,17 @@ UNSPEC_COND_FMAXNM UNSPEC_COND_FMIN UNSPEC_COND_FMINNM - UNSPEC_COND_FMUL]) + UNSPEC_COND_FMUL + UNSPEC_COND_SMAX + UNSPEC_COND_SMIN]) (define_int_iterator SVE_COND_FP_BINARY_REG [(UNSPEC_COND_FAMAX "TARGET_SVE_FAMINMAX") (UNSPEC_COND_FAMIN "TARGET_SVE_FAMINMAX") UNSPEC_COND_FDIV - UNSPEC_COND_FMULX]) + UNSPEC_COND_FMULX + UNSPEC_COND_SMAX + UNSPEC_COND_SMIN]) (define_int_iterator SVE_COND_FCADD [UNSPEC_COND_FCADD90 UNSPEC_COND_FCADD270]) @@ -3133,11 +3143,6 @@ UNSPEC_COND_FMIN UNSPEC_COND_FMINNM]) -;; Floating-point max/min operations that correspond to optabs, -;; as opposed to those that are internal to the port. -(define_int_iterator SVE_COND_FP_MAXMIN_PUBLIC [UNSPEC_COND_FMAXNM - UNSPEC_COND_FMINNM]) - (define_int_iterator SVE_COND_FP_TERNARY [UNSPEC_COND_FMLA UNSPEC_COND_FMLS UNSPEC_COND_FNMLA @@ -3715,9 +3720,9 @@ (UNSPEC_COND_FCVTZU "fixuns_trunc") (UNSPEC_COND_FDIV "div") (UNSPEC_COND_FMAX "fmax_nan") - (UNSPEC_COND_FMAXNM "smax") + (UNSPEC_COND_FMAXNM "fmax") (UNSPEC_COND_FMIN "fmin_nan") - (UNSPEC_COND_FMINNM "smin") + (UNSPEC_COND_FMINNM "fmin") (UNSPEC_COND_FMLA "fma") (UNSPEC_COND_FMLS "fnma") (UNSPEC_COND_FMUL "mul") @@ -3737,16 +3742,16 @@ (UNSPEC_COND_FSQRT "sqrt") (UNSPEC_COND_FSUB "sub") (UNSPEC_COND_SCVTF "float") - (UNSPEC_COND_UCVTF "floatuns")]) + (UNSPEC_COND_UCVTF "floatuns") + (UNSPEC_COND_SMAX "smax") + (UNSPEC_COND_SMIN "smin")]) (define_int_attr fmaxmin [(UNSPEC_FMAX "fmax_nan") (UNSPEC_FMAXNM "fmax") (UNSPEC_FMAXNMV "fmax") (UNSPEC_FMIN "fmin_nan") (UNSPEC_FMINNM "fmin") - (UNSPEC_FMINNMV "fmin") - (UNSPEC_COND_FMAXNM "fmax") - (UNSPEC_COND_FMINNM "fmin")]) + (UNSPEC_FMINNMV "fmin")]) (define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax") (UNSPEC_UMINV "umin") @@ -4263,7 +4268,9 @@ (UNSPEC_COND_FRINTZ "frintz") (UNSPEC_COND_FSCALE "fscale") (UNSPEC_COND_FSQRT "fsqrt") - (UNSPEC_COND_FSUB "fsub")]) + (UNSPEC_COND_FSUB "fsub") + (UNSPEC_COND_SMAX "fmaxnm") + (UNSPEC_COND_SMIN "fminnm")]) (define_int_attr sve_fp_op_rev [(UNSPEC_COND_FADD "fadd") (UNSPEC_COND_FAMAX "famax") @@ -4275,7 +4282,9 @@ (UNSPEC_COND_FMINNM "fminnm") (UNSPEC_COND_FMUL "fmul") (UNSPEC_COND_FMULX "fmulx") - (UNSPEC_COND_FSUB "fsubr")]) + (UNSPEC_COND_FSUB "fsubr") + (UNSPEC_COND_SMAX "fmaxnm") + (UNSPEC_COND_SMIN "fminnm")]) (define_int_attr sme_int_op [(UNSPEC_SME_ADD_WRITE "add") (UNSPEC_SME_SUB_WRITE "sub")]) @@ -4413,7 +4422,9 @@ (UNSPEC_COND_FMINNM "register_operand") (UNSPEC_COND_FMUL "register_operand") (UNSPEC_COND_FMULX "register_operand") - (UNSPEC_COND_FSUB "aarch64_sve_float_arith_operand")]) + (UNSPEC_COND_FSUB "aarch64_sve_float_arith_operand") + (UNSPEC_COND_SMAX "register_operand") + (UNSPEC_COND_SMIN "register_operand")]) ;; The predicate to use for the second input operand in a floating-point ;; 3 pattern. @@ -4428,7 +4439,9 @@ (UNSPEC_COND_FMINNM "aarch64_sve_float_maxmin_operand") (UNSPEC_COND_FMUL "aarch64_sve_float_mul_operand") (UNSPEC_COND_FMULX "register_operand") - (UNSPEC_COND_FSUB "register_operand")]) + (UNSPEC_COND_FSUB "register_operand") + (UNSPEC_COND_SMAX "aarch64_sve_float_maxmin_operand") + (UNSPEC_COND_SMIN "aarch64_sve_float_maxmin_operand")]) ;; Likewise for immediates only. (define_int_attr sve_pred_fp_rhs2_immediate @@ -4436,7 +4449,9 @@ (UNSPEC_COND_FMAXNM "aarch64_sve_float_maxmin_immediate") (UNSPEC_COND_FMIN "aarch64_sve_float_maxmin_immediate") (UNSPEC_COND_FMINNM "aarch64_sve_float_maxmin_immediate") - (UNSPEC_COND_FMUL "aarch64_sve_float_mul_immediate")]) + (UNSPEC_COND_FMUL "aarch64_sve_float_mul_immediate") + (UNSPEC_COND_SMAX "aarch64_sve_float_maxmin_immediate") + (UNSPEC_COND_SMIN "aarch64_sve_float_maxmin_immediate")]) ;; The maximum number of element bits that an instruction can handle. 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(35042699022)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2024 12:10:00.8367 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 511d109a-648d-4374-894d-08dce211f985 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509FF.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR08MB10977 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_SHORT, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org The AArch64 FEAT_FAMINMAX extension introduces instructions for computing the floating point absolute maximum and minimum of the two vectors element-wise. This patch adds code generation for famax and famin in terms of existing unspecs. With this patch: 1. famax can be expressed as taking UNSPEC_COND_SMAX of the two operands and then taking absolute value of their result. 2. famin can be expressed as taking UNSPEC_COND_SMIN of the two operands and then taking absolute value of their result. This fusion of operators is only possible when -march=armv9-a+faminmax+sve flags are passed. We also need to pass -ffast-math flag; this is what enables compiler to use UNSPEC_COND_SMAX and UNSPEC_COND_SMIN. This code generation is only available on -O2 or -O3 as that is when auto-vectorization is enabled. gcc/ChangeLog: * config/aarch64/aarch64-sve2.md (*aarch64_pred_faminmax_fused): Instruction pattern for faminmax codegen. * config/aarch64/iterators.md: Iterator and attribute for faminmax codegen. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve/faminmax_1.c: New test. * gcc.target/aarch64/sve/faminmax_2.c: New test. --- gcc/config/aarch64/aarch64-sve2.md | 31 ++++ gcc/config/aarch64/iterators.md | 6 + .../gcc.target/aarch64/sve/faminmax_1.c | 85 ++++++++++ .../gcc.target/aarch64/sve/faminmax_2.c | 154 ++++++++++++++++++ 4 files changed, 276 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/faminmax_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/faminmax_2.c diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index 972b03a4fef..6a8e940e16d 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -2467,6 +2467,37 @@ [(set_attr "movprfx" "yes")] ) +;; ------------------------------------------------------------------------- +;; -- [FP] Absolute maximum and minimum +;; ------------------------------------------------------------------------- +;; Includes: +;; - FAMAX +;; - FAMIN +;; ------------------------------------------------------------------------- +;; Predicated floating-point absolute maximum and minimum. +(define_insn "*aarch64_pred_faminmax_fused" + [(set (match_operand:SVE_FULL_F 0 "register_operand") + (unspec:SVE_FULL_F + [(match_operand: 1 "register_operand") + (match_operand:SI 4 "aarch64_sve_gp_strictness") + (unspec:SVE_FULL_F + [(match_operand 5) + (const_int SVE_RELAXED_GP) + (match_operand:SVE_FULL_F 2 "register_operand")] + UNSPEC_COND_FABS) + (unspec:SVE_FULL_F + [(match_operand 6) + (const_int SVE_RELAXED_GP) + (match_operand:SVE_FULL_F 3 "register_operand")] + UNSPEC_COND_FABS)] + SVE_COND_FP_SMAXMIN))] + "TARGET_SVE_FAMINMAX" + {@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx ] + [ w , Upl , %0 , w ; * ] \t%0., %1/m, %0., %3. + [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %0., %3. + } +) + ;; ========================================================================= ;; == Complex arithmetic ;; ========================================================================= diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index d3a457fc6d9..e9adb4209da 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -3143,6 +3143,9 @@ UNSPEC_COND_FMIN UNSPEC_COND_FMINNM]) +(define_int_iterator SVE_COND_FP_SMAXMIN [UNSPEC_COND_SMAX + UNSPEC_COND_SMIN]) + (define_int_iterator SVE_COND_FP_TERNARY [UNSPEC_COND_FMLA UNSPEC_COND_FMLS UNSPEC_COND_FNMLA @@ -4503,6 +4506,9 @@ (define_int_iterator FAMINMAX_UNS [UNSPEC_FAMAX UNSPEC_FAMIN]) +(define_int_attr faminmax_cond_uns_op + [(UNSPEC_COND_SMAX "famax") (UNSPEC_COND_SMIN "famin")]) + (define_int_attr faminmax_uns_op [(UNSPEC_FAMAX "famax") (UNSPEC_FAMIN "famin")]) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/faminmax_1.c b/gcc/testsuite/gcc.target/aarch64/sve/faminmax_1.c new file mode 100644 index 00000000000..bdf077ab2f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/faminmax_1.c @@ -0,0 +1,85 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O3 -ffast-math" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_sve.h" + +#pragma GCC target "+sve+faminmax" + +#define TEST_FAMAX(TYPE) \ + void fn_famax_##TYPE (TYPE * restrict a, \ + TYPE * restrict b, \ + TYPE * restrict c, \ + int n) { \ + for (int i = 0; i < n; i++) { \ + TYPE temp1 = __builtin_fabs (a[i]); \ + TYPE temp2 = __builtin_fabs (b[i]); \ + c[i] = __builtin_fmax (temp1, temp2); \ + } \ + } \ + +#define TEST_FAMIN(TYPE) \ + void fn_famin_##TYPE (TYPE * restrict a, \ + TYPE * restrict b, \ + TYPE * restrict c, \ + int n) { \ + for (int i = 0; i < n; i++) { \ + TYPE temp1 = __builtin_fabs (a[i]); \ + TYPE temp2 = __builtin_fabs (b[i]); \ + c[i] = __builtin_fmin (temp1, temp2); \ + } \ + } \ + +/* +** fn_famax_float16_t: +** ... +** famax z30.h, p6/m, z30.h, z31.h +** ... +** ret +*/ +TEST_FAMAX (float16_t) + +/* +** fn_famax_float32_t: +** ... +** famax z30.s, p6/m, z30.s, z31.s +** ... +** ret +*/ +TEST_FAMAX (float32_t) + +/* +** fn_famax_float64_t: +** ... +** famax z30.d, p6/m, z30.d, z31.d +** ... +** ret +*/ +TEST_FAMAX (float64_t) + +/* +** fn_famin_float16_t: +** ... +** famin z30.h, p6/m, z30.h, z31.h +** ... +** ret +*/ +TEST_FAMIN (float16_t) + +/* +** fn_famin_float32_t: +** ... +** famin z30.s, p6/m, z30.s, z31.s +** ... +** ret +*/ +TEST_FAMIN (float32_t) + +/* +** fn_famin_float64_t: +** ... +** famin z30.d, p6/m, z30.d, z31.d +** ... +** ret +*/ +TEST_FAMIN (float64_t) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/faminmax_2.c b/gcc/testsuite/gcc.target/aarch64/sve/faminmax_2.c new file mode 100644 index 00000000000..26396979389 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/faminmax_2.c @@ -0,0 +1,154 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O3 -ffast-math" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_sve.h" + +#pragma GCC target "+sve+faminmax" + +#define TEST_WITH_SVMAX(TYPE) \ + TYPE fn_fmax_##TYPE (TYPE x, TYPE y) { \ + svbool_t pg = svptrue_b8(); \ + return svmax_x(pg, svabs_x(pg, x), svabs_x(pg, y)); \ + } \ + +#define TEST_WITH_SVMAXNM(TYPE) \ + TYPE fn_fmaxnm_##TYPE (TYPE x, TYPE y) { \ + svbool_t pg = svptrue_b8(); \ + return svmaxnm_x(pg, svabs_x(pg, x), svabs_x(pg, y)); \ + } \ + +#define TEST_WITH_SVMIN(TYPE) \ + TYPE fn_fmin_##TYPE (TYPE x, TYPE y) { \ + svbool_t pg = svptrue_b8(); \ + return svmin_x(pg, svabs_x(pg, x), svabs_x(pg, y)); \ + } \ + +#define TEST_WITH_SVMINNM(TYPE) \ + TYPE fn_fminnm_##TYPE (TYPE x, TYPE y) { \ + svbool_t pg = svptrue_b8(); \ + return svminnm_x(pg, svabs_x(pg, x), svabs_x(pg, y)); \ + } \ + +/* +** fn_fmax_svfloat16_t: +** ptrue p3.b, all +** fabs z0.h, p3/m, z0.h +** fabs z1.h, p3/m, z1.h +** fmax z0.h, p3/m, z0.h, z1.h +** ret +*/ +TEST_WITH_SVMAX (svfloat16_t) + +/* +** fn_fmax_svfloat32_t: +** ptrue p3.b, all +** fabs z0.s, p3/m, z0.s +** fabs z1.s, p3/m, z1.s +** fmax z0.s, p3/m, z0.s, z1.s +** ret +*/ +TEST_WITH_SVMAX (svfloat32_t) + +/* +** fn_fmax_svfloat64_t: +** ptrue p3.b, all +** fabs z0.d, p3/m, z0.d +** fabs z1.d, p3/m, z1.d +** fmax z0.d, p3/m, z0.d, z1.d +** ret +*/ +TEST_WITH_SVMAX (svfloat64_t) + +/* +** fn_fmaxnm_svfloat16_t: +** ptrue p3.b, all +** fabs z0.h, p3/m, z0.h +** fabs z1.h, p3/m, z1.h +** fmaxnm z0.h, p3/m, z0.h, z1.h +** ret +*/ +TEST_WITH_SVMAXNM (svfloat16_t) + +/* +** fn_fmaxnm_svfloat32_t: +** ptrue p3.b, all +** fabs z0.s, p3/m, z0.s +** fabs z1.s, p3/m, z1.s +** fmaxnm z0.s, p3/m, z0.s, z1.s +** ret +*/ +TEST_WITH_SVMAXNM (svfloat32_t) + +/* +** fn_fmaxnm_svfloat64_t: +** ptrue p3.b, all +** fabs z0.d, p3/m, z0.d +** fabs z1.d, p3/m, z1.d +** fmaxnm z0.d, p3/m, z0.d, z1.d +** ret +*/ +TEST_WITH_SVMAXNM (svfloat64_t) + +/* +** fn_fmin_svfloat16_t: +** ptrue p3.b, all +** fabs z0.h, p3/m, z0.h +** fabs z1.h, p3/m, z1.h +** fmin z0.h, p3/m, z0.h, z1.h +** ret +*/ +TEST_WITH_SVMIN (svfloat16_t) + +/* +** fn_fmin_svfloat32_t: +** ptrue p3.b, all +** fabs z0.s, p3/m, z0.s +** fabs z1.s, p3/m, z1.s +** fmin z0.s, p3/m, z0.s, z1.s +** ret +*/ +TEST_WITH_SVMIN (svfloat32_t) + +/* +** fn_fmin_svfloat64_t: +** ptrue p3.b, all +** fabs z0.d, p3/m, z0.d +** fabs z1.d, p3/m, z1.d +** fmin z0.d, p3/m, z0.d, z1.d +** ret +*/ +TEST_WITH_SVMIN (svfloat64_t) + +/* +** fn_fminnm_svfloat16_t: +** ptrue p3.b, all +** fabs z0.h, p3/m, z0.h +** fabs z1.h, p3/m, z1.h +** fminnm z0.h, p3/m, z0.h, z1.h +** ret +*/ +TEST_WITH_SVMINNM (svfloat16_t) + +/* +** fn_fminnm_svfloat32_t: +** ptrue p3.b, all +** fabs z0.s, p3/m, z0.s +** fabs z1.s, p3/m, z1.s +** fminnm z0.s, p3/m, z0.s, z1.s +** ret +*/ +TEST_WITH_SVMINNM (svfloat32_t) + +/* +** fn_fminnm_svfloat64_t: +** ptrue p3.b, all +** fabs z0.d, p3/m, z0.d +** fabs z1.d, p3/m, z1.d +** fminnm z0.d, p3/m, z0.d, z1.d +** ret +*/ +TEST_WITH_SVMINNM (svfloat64_t) + +/* { dg-final { scan-assembler-not {\tfamax\t} } } */ +/* { dg-final { scan-assembler-not {\tfamin\t} } } */