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([172.58.106.160]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3dd060b5388sm835591b6e.43.2024.08.10.23.03.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Aug 2024 23:03:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH 1/4] target/m68k: Introduce M68K_FEATURE_FPU_PACKED_DECIMAL Date: Sun, 11 Aug 2024 16:03:10 +1000 Message-ID: <20240811060313.730410-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240811060313.730410-1-richard.henderson@linaro.org> References: <20240811060313.730410-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Set for 68020 and 68030, but does nothing so far. Signed-off-by: Richard Henderson --- target/m68k/cpu.h | 2 ++ target/m68k/cpu.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index b5bbeedb7a..7114324e4d 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -553,6 +553,8 @@ enum m68k_features { M68K_FEATURE_MOVEFROMSR_PRIV, /* Exception frame with format+vector (from 68010) */ M68K_FEATURE_EXCEPTION_FORMAT_VEC, + /* FPU supports packed decimal real format */ + M68K_FEATURE_FPU_PACKED_DECIMAL, }; static inline bool m68k_feature(CPUM68KState *env, int feature) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 1d49f4cb23..65058dd052 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -182,6 +182,7 @@ static void m68020_cpu_initfn(Object *obj) m68k_set_feature(env, M68K_FEATURE_MSP); m68k_set_feature(env, M68K_FEATURE_UNALIGNED_DATA); m68k_set_feature(env, M68K_FEATURE_TRAPCC); + m68k_set_feature(env, M68K_FEATURE_FPU_PACKED_DECIMAL); } /* @@ -224,6 +225,7 @@ static void m68040_cpu_initfn(Object *obj) m68030_cpu_initfn(obj); m68k_unset_feature(env, M68K_FEATURE_M68030); + m68k_unset_feature(env, M68K_FEATURE_FPU_PACKED_DECIMAL); m68k_set_feature(env, M68K_FEATURE_M68040); } From patchwork Sun Aug 11 06:03:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1971237 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=cNS0RPzB; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WhRv62VLyz1yXh for ; Sun, 11 Aug 2024 16:04:50 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sd1g2-00020g-ND; Sun, 11 Aug 2024 02:03:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sd1fz-000202-RV for qemu-devel@nongnu.org; Sun, 11 Aug 2024 02:03:36 -0400 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sd1fy-0003LQ-0B for qemu-devel@nongnu.org; Sun, 11 Aug 2024 02:03:35 -0400 Received: by mail-oi1-x22b.google.com with SMTP id 5614622812f47-3db51b8ec15so2216459b6e.1 for ; Sat, 10 Aug 2024 23:03:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1723356212; x=1723961012; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1DmwpPh0HuvQouOcnmqzDiaoQNQqQeUssp+FOFv7Ick=; b=cNS0RPzBWcQGUMQ9Qa0+C8HnY4ljW4vqwQd8xjUvTWp53upJlBHUR492xqZ2SHjvYM 6UdI7GuMb/GCPgIxKFK+MzPZbWes4/PhtI9JkdMZ9C0FJDBHt7fh0Q8Q5hvs+Rvv5zv1 kxyyS3XSrEPmXupxUV5VsXVXKcQe7ppB9b72Me1wUm/eFRx49OQoFrBBa/JMNIVa4jAw cQxpSs6GaeRj62eQ/fV+JXAQGP6RNTnE+8yBjGHyuATVp1gm8mU22KLCxKrYgGu35Qc1 zgHzOnL+xU65el6lUU8O/Zj3ESZfrgucZSwuWsJGXfyOTd+z2cuyn1++54v01LljFETO cYGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723356212; x=1723961012; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1DmwpPh0HuvQouOcnmqzDiaoQNQqQeUssp+FOFv7Ick=; b=AwrKJs1uTBEckQlLz3yFQcMljKJAjpwj3AwTcalwIgUA1rVk0XjIOEiMfCmd+0Jky6 K+EspR5JeDMhMuCAzJj7DvSXWZ1VhOeCaZogPeJASUtFs/eElS70vLYH+l8e3RDPYhnX 9D+DjA8tdZSeDuXGDIT9eL9iHKduO87MN9Lhsy6BuMOxDt3hWl2dyLg87tVCpGSc9flF /eKncnEmrsZpkMfIdRTmk24OYAvPKsS8lVMWAQQuF5QZkcTFR6MBJjuQtSvPDkPtdEkp zoCoyCOXay4Rc+b8r7B1fpm9B6lZceJqGN+K3N2RL0MvjWGxG9AEhgqegmeQSx4mLEG1 3yXw== X-Gm-Message-State: AOJu0YwYQK1Vn+0SMCC4Fy9l72DQB7KGUV9vqywtIvaGYwUNypS3WZah 6ZE8M5h0cjX0wIedxfb2v7nMtI+5tUHhB6NaqyOycbEQovgr1n8Osj9F2CTDUVrA1EQsUeSuTaL DUHvDYw== X-Google-Smtp-Source: AGHT+IEAP00RJ15mKxZ9sN47LohN4fTLgAnX/FSxQ2BSXaSF//qZUJrGJVpJydTc8CvJJ51YM5bpBw== X-Received: by 2002:a05:6808:14c4:b0:3d9:2baa:9fd3 with SMTP id 5614622812f47-3dc417a7de8mr2439840b6e.20.1723356212448; Sat, 10 Aug 2024 23:03:32 -0700 (PDT) Received: from stoup.. ([172.58.106.160]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3dd060b5388sm835591b6e.43.2024.08.10.23.03.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Aug 2024 23:03:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH 2/4] target/m68k: Implement packed decimal real loads Date: Sun, 11 Aug 2024 16:03:11 +1000 Message-ID: <20240811060313.730410-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240811060313.730410-1-richard.henderson@linaro.org> References: <20240811060313.730410-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target/m68k/helper.h | 2 + target/m68k/fpu_helper.c | 137 +++++++++++++++++++++++++++++++++++++++ target/m68k/translate.c | 22 ++++--- 3 files changed, 151 insertions(+), 10 deletions(-) diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 95aa5e53bb..2c71361451 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -126,6 +126,8 @@ DEF_HELPER_FLAGS_4(bfffo_mem, TCG_CALL_NO_WG, i64, env, i32, s32, i32) DEF_HELPER_3(chk, void, env, s32, s32) DEF_HELPER_4(chk2, void, env, s32, s32, s32) +DEF_HELPER_FLAGS_3(load_pdr_to_fx80, TCG_CALL_NO_RWG, void, env, fp, tl) + #if !defined(CONFIG_USER_ONLY) DEF_HELPER_3(ptest, void, env, i32, i32) DEF_HELPER_3(pflush, void, env, i32, i32) diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index 8314791f50..dd80943153 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -749,3 +749,140 @@ void HELPER(fcosh)(CPUM68KState *env, FPReg *res, FPReg *val) { res->d = floatx80_cosh(val->d, &env->fp_status); } + +/* From m68k float.h, LDBL_MAX_10_EXP. */ +#define FX80_MAX_10_EXP 4932 + +/* 10**0 through 10**18 */ +static const int64_t i64_pow10[] = { + 1ll, + 10ll, + 100ll, + 1000ll, + 10000ll, + 100000ll, + 1000000ll, + 10000000ll, + 100000000ll, + 1000000000ll, + 10000000000ll, + 100000000000ll, + 1000000000000ll, + 10000000000000ll, + 100000000000000ll, + 1000000000000000ll, + 10000000000000000ll, + 100000000000000000ll, + 1000000000000000000ll, +}; + +/* Form 10**exp */ +static floatx80 floatx80_exp10i(int exp, float_status *status) +{ + static floatx80 cache[FX80_MAX_10_EXP + 1]; + + floatx80 ret; + + assert(exp >= 0 && exp <= FX80_MAX_10_EXP); + + ret = cache[exp]; + if (ret.high) { + if (exp >= ARRAY_SIZE(i64_pow10)) { + float_raise(float_flag_inexact, status); + } + } else { + FloatRoundMode old_round = get_float_rounding_mode(status); + set_float_rounding_mode(float_round_nearest_even, status); + + if (exp < ARRAY_SIZE(i64_pow10)) { + ret = int64_to_floatx80(i64_pow10[exp], status); + } else { + int e0 = exp / 2; + int e1 = exp - e0; + ret = floatx80_mul(floatx80_exp10i(e0, status), + floatx80_exp10i(e1, status), status); + } + + set_float_rounding_mode(old_round, status); + cache[exp] = ret; + } + return ret; +} + +void HELPER(load_pdr_to_fx80)(CPUM68KState *env, FPReg *res, target_ulong addr) +{ + uint64_t lo; + uint32_t hi; + int64_t mant; + int exp; + floatx80 fexp; + + hi = cpu_ldl_be_data_ra(env, addr, GETPC()); + lo = cpu_ldq_be_data_ra(env, addr + 4, GETPC()); + + if (unlikely((hi & 0x7fff0000) == 0x7fff0000)) { + /* NaN or Inf */ + res->l.lower = lo; + res->l.upper = hi >> 16; + return; + } + + /* Initialize mant with the integer digit. */ + mant = hi & 0xf; + if (!mant && !lo) { + /* +/- 0, regardless of exponent. */ + res->l.lower = 0; + res->l.upper = (hi >> 16) & 0x8000; + return; + } + + /* + * Accumulate the 16 decimal fraction digits into mant. + * With 17 decimal digits, the maximum value is 10**17 - 1, + * which is less than 2**57. + */ + for (int i = 60; i >= 0; i -= 4) { + /* + * From 1.6.6 Data Format and Type Summary: + * The fpu does not detect non-decimal digits in any of the exponent, + * integer, or fraction digits. These non-decimal digits are converted + * in the same manner as decimal digits; the result is probably useless + * although it is repeatable. + */ + mant = mant * 10 + ((lo >> i) & 0xf); + } + + /* Apply the mantissa sign. */ + if (hi & 0x80000000) { + mant = -mant; + } + + /* Convert the 3 digit decimal exponent to binary. */ + exp = ((hi >> 24) & 0xf) + + ((hi >> 20) & 0xf) * 10 + + ((hi >> 16) & 0xf) * 100; + + /* Apply the exponent sign. */ + if (hi & 0x40000000) { + exp = -exp; + } + + /* + * Our representation of mant is integral, whereas the decimal point + * belongs between the integer and fractional components. + * Adjust the exponent to compensate. + */ + exp -= 16; + + /* Convert mantissa. */ + res->d = int64_to_floatx80(mant, &env->fp_status); + + /* Apply exponent. */ + if (exp > 0) { + fexp = floatx80_exp10i(exp, &env->fp_status); + res->d = floatx80_mul(res->d, fexp, &env->fp_status); + } else if (exp < 0) { + fexp = floatx80_exp10i(-exp, &env->fp_status); + res->d = floatx80_div(res->d, fexp, &env->fp_status); + } +} diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 445966fb6a..59e7d27393 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -963,11 +963,11 @@ static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp, tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower)); break; case OS_PACKED: - /* - * unimplemented data type on 68040/ColdFire - * FIXME if needed for another FPU - */ - gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP); + if (!m68k_feature(s->env, M68K_FEATURE_FPU_PACKED_DECIMAL)) { + gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP); + break; + } + gen_helper_load_pdr_to_fx80(tcg_env, fp, addr); break; default: g_assert_not_reached(); @@ -1142,11 +1142,13 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode, tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower)); break; case OS_PACKED: - /* - * unimplemented data type on 68040/ColdFire - * FIXME if needed for another FPU - */ - gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP); + if (!m68k_feature(s->env, M68K_FEATURE_FPU_PACKED_DECIMAL)) { + gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP); + break; + } + tmp = tcg_constant_tl(s->pc); + s->pc += 12; + gen_helper_load_pdr_to_fx80(tcg_env, fp, tmp); break; default: g_assert_not_reached(); From patchwork Sun Aug 11 06:03:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1971233 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=o8/qsg41; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WhRts05N0z1yXh for ; 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([172.58.106.160]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3dd060b5388sm835591b6e.43.2024.08.10.23.03.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Aug 2024 23:03:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH 3/4] target/m68k: Implement packed decimal real stores Date: Sun, 11 Aug 2024 16:03:12 +1000 Message-ID: <20240811060313.730410-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240811060313.730410-1-richard.henderson@linaro.org> References: <20240811060313.730410-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2488 Signed-off-by: Richard Henderson --- target/m68k/helper.h | 1 + target/m68k/fpu_helper.c | 100 +++++++++++++++++++++++++++++++++++++++ target/m68k/translate.c | 27 +++++++++-- 3 files changed, 125 insertions(+), 3 deletions(-) diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 2c71361451..21af6adb39 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -127,6 +127,7 @@ DEF_HELPER_3(chk, void, env, s32, s32) DEF_HELPER_4(chk2, void, env, s32, s32, s32) DEF_HELPER_FLAGS_3(load_pdr_to_fx80, TCG_CALL_NO_RWG, void, env, fp, tl) +DEF_HELPER_FLAGS_4(store_fx80_to_pdr, TCG_CALL_NO_RWG, void, env, tl, fp, int) #if !defined(CONFIG_USER_ONLY) DEF_HELPER_3(ptest, void, env, i32, i32) diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index dd80943153..6f37a165e2 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -886,3 +886,103 @@ void HELPER(load_pdr_to_fx80)(CPUM68KState *env, FPReg *res, target_ulong addr) res->d = floatx80_div(res->d, fexp, &env->fp_status); } } + +static floatx80 floatx80_scale10i(floatx80 x, int e, float_status *status) +{ + floatx80 t; + if (e >= 0) { + t = floatx80_exp10i(e, status); + t = floatx80_mul(x, t, status); + } else { + t = floatx80_exp10i(-e, status); + t = floatx80_div(x, t, status); + } + return t; +} + +void HELPER(store_fx80_to_pdr)(CPUM68KState *env, target_ulong addr, + FPReg *srcp, int kfactor) +{ + floatx80 t, x = srcp->d; + int len, exp2, exp10; + uint64_t res_lo; + uint32_t res_hi; + int64_t y; + + res_lo = x.low; + exp2 = x.high & 0x7fff; + if (unlikely(exp2 == 0x7fff)) { + /* NaN and Inf */ + res_hi = (uint32_t)x.high << 16; + goto done; + } + + /* Copy the sign bit to the output, and then x = abs(x). */ + res_hi = (x.high & 0x8000u) << 16; + x.high &= 0x7fff; + + if (exp2 == 0) { + if (res_lo == 0) { + /* +/- 0 */ + goto done; + } + /* denormal */ + exp2 = -0x3fff - clz64(res_lo); + } else { + exp2 -= 0x3fff; + } + + /* + * Begin with an approximation of log2(x) via the base 2 exponent. + * Adjust, so that we compute the value scaled by 10**17, which will + * allows an integer to be extracted to match the output digits. + */ + exp10 = (exp2 * 30102) / 100000; + while (1) { + /* kfactor controls the number of output digits */ + if (kfactor <= 0) { + /* kfactor is number of digits right of the decimal point. */ + len = exp10 - kfactor; + } else { + /* kfactor is number of significant digits */ + len = kfactor; + } + len = MIN(MAX(len, 1), 17); + + /* + * Scale, so that we have the requested number of digits + * left of the decimal point. Convert to integer, which + * handles the rounding (and may force adjustment of exp10). + */ + t = floatx80_scale10i(x, len - 1 - exp10, &env->fp_status); + y = floatx80_to_int64(t, &env->fp_status); + if (y < i64_pow10[len - 1]) { + exp10--; + } else if (y < i64_pow10[len]) { + break; + } else { + exp10++; + } + } + + /* Output the mantissa. */ + res_hi |= y / i64_pow10[len - 1]; + res_lo = 0; + for (int i = 1; i < len; ++i) { + int64_t d = (y / i64_pow10[len - 1 - i]) % 10; + res_lo |= d << (64 - i * 4); + } + + /* Output the exponent. */ + if (exp10 < 0) { + res_hi |= 0x40000000; + exp10 = -exp10; + } + for (int i = 24; exp10; i -= 4, exp10 /= 10) { + res_hi |= (exp10 % 10) << i; + } + + done: + cpu_stl_be_data_ra(env, addr, res_hi, GETPC()); + cpu_stq_be_data_ra(env, addr + 4, res_lo, GETPC()); +} diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 59e7d27393..fb5ecce0c3 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -119,6 +119,8 @@ typedef struct DisasContext { int done_mac; int writeback_mask; TCGv writeback[8]; + uint16_t insn; + uint16_t ext; bool ss_active; } DisasContext; @@ -671,6 +673,7 @@ static inline int ext_opsize(int ext, int pos) case 4: return OS_WORD; case 5: return OS_DOUBLE; case 6: return OS_BYTE; + case 7: return OS_PACKED; /* store, dynamic k-factor */ default: g_assert_not_reached(); } @@ -1010,11 +1013,25 @@ static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp, tcg_gen_qemu_st_i64(t64, tmp, index, MO_TEUQ); break; case OS_PACKED: + if (!m68k_feature(s->env, M68K_FEATURE_FPU_PACKED_DECIMAL)) { + gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP); + break; + } /* - * unimplemented data type on 68040/ColdFire - * FIXME if needed for another FPU + * For stores we must recover k-factor, either from an + * immediate or the low 7 bits of a D register. */ - gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP); + switch ((s->ext >> 10) & 7) { + case 3: + tcg_gen_movi_i32(tmp, sextract32(s->ext, 0, 7)); + break; + case 7: + tcg_gen_sextract_i32(tmp, DREG(s->ext, 4), 0, 7); + break; + default: + g_assert_not_reached(); + } + gen_helper_store_fx80_to_pdr(tcg_env, addr, fp, tmp); break; default: g_assert_not_reached(); @@ -4940,6 +4957,8 @@ DISAS_INSN(fpu) TCGv_ptr cpu_src, cpu_dest; ext = read_im16(env, s); + s->ext = ext; + opmode = ext & 0x7f; switch ((ext >> 13) & 7) { case 0: @@ -6042,6 +6061,8 @@ static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) CPUM68KState *env = cpu_env(cpu); uint16_t insn = read_im16(env, dc); + dc->insn = insn; + dc->ext = 0; opcode_table[insn](env, dc, insn); do_writebacks(dc);