From patchwork Sun Jul 7 08:58:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?In=C3=A8s_Varhol?= X-Patchwork-Id: 1957667 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=telecom-paris.fr header.i=@telecom-paris.fr header.a=rsa-sha256 header.s=A35C7578-1106-11E5-A17F-C303FDDA8F2E header.b=uqvB/3Qz; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WH1S41rC2z1xr7 for ; Sun, 7 Jul 2024 19:00:36 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sQNkJ-0002aR-Aq; Sun, 07 Jul 2024 04:59:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sQNkG-0002Yz-9P; Sun, 07 Jul 2024 04:59:44 -0400 Received: from zproxy4.enst.fr ([2001:660:330f:2::df]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sQNkE-0006J1-Bc; Sun, 07 Jul 2024 04:59:44 -0400 Received: from localhost (localhost [IPv6:::1]) by zproxy4.enst.fr (Postfix) with ESMTP id BB88D2075D; Sun, 7 Jul 2024 10:59:36 +0200 (CEST) Received: from zproxy4.enst.fr ([IPv6:::1]) by localhost (zproxy4.enst.fr [IPv6:::1]) (amavis, port 10032) with ESMTP id 91whTsW1Ly2u; Sun, 7 Jul 2024 10:59:36 +0200 (CEST) Received: from localhost (localhost [IPv6:::1]) by zproxy4.enst.fr (Postfix) with ESMTP id 1BB6F206F0; Sun, 7 Jul 2024 10:59:36 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.10.3 zproxy4.enst.fr 1BB6F206F0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=telecom-paris.fr; s=A35C7578-1106-11E5-A17F-C303FDDA8F2E; t=1720342776; bh=BeaFKQuGG4jIe49CkCds4F/v3CiIYtAA1KyJr5W9pOs=; h=From:To:Date:Message-ID:MIME-Version; b=uqvB/3QzPqXdItqEfSGsNE18OUPMyLz4ARrqZ7/9Cp87kZ6Bx2ExklHFpMJsgjjNr H8BUjPIXO9sVY9i5utAU5tP1xw+JUpzLV+2zJ3Rgxb2Ofj0GihZ/JtT5Rhn1pbypa1 N0RpxPxv1HkBqfA9cnoURuBDvMA4iyVIya6MMlPM= X-Virus-Scanned: amavis at enst.fr Received: from zproxy4.enst.fr ([IPv6:::1]) by localhost (zproxy4.enst.fr [IPv6:::1]) (amavis, port 10026) with ESMTP id k15C758iKCTk; Sun, 7 Jul 2024 10:59:35 +0200 (CEST) Received: from inesv-Inspiron-3501.enst.fr (unknown [IPv6:2a04:8ec0:0:124::190c]) by zproxy4.enst.fr (Postfix) with ESMTPSA id 3BCC52075C; Sun, 7 Jul 2024 10:59:35 +0200 (CEST) From: =?utf-8?q?In=C3=A8s_Varhol?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Alistair Francis , =?utf-8?q?In=C3=A8s_Varhol?= , Arnaud Minier , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= , Peter Maydell Subject: [PATCH v3 1/3] hw/misc: In STM32L4x5 EXTI, consolidate 2 constants Date: Sun, 7 Jul 2024 10:58:53 +0200 Message-ID: <20240707085927.122867-2-ines.varhol@telecom-paris.fr> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240707085927.122867-1-ines.varhol@telecom-paris.fr> References: <20240707085927.122867-1-ines.varhol@telecom-paris.fr> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:660:330f:2::df; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy4.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Up until now, the EXTI implementation had 16 inbound GPIOs connected to the 16 outbound GPIOs of STM32L4x5 SYSCFG. The EXTI actually handles 40 lines (namely 5 from STM32L4x5 USART devices which are already implemented in QEMU). In order to connect USART devices to EXTI, this commit consolidates constants `EXTI_NUM_INTERRUPT_OUT_LINES` (40) and `EXTI_NUM_GPIO_EVENT_IN_LINES` (16) into `EXTI_NUM_LINES` (40). Signed-off-by: Inès Varhol Reviewed-by: Peter Maydell --- include/hw/misc/stm32l4x5_exti.h | 4 ++-- hw/misc/stm32l4x5_exti.c | 6 ++---- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/include/hw/misc/stm32l4x5_exti.h b/include/hw/misc/stm32l4x5_exti.h index 55f763fa37..62f79362f2 100644 --- a/include/hw/misc/stm32l4x5_exti.h +++ b/include/hw/misc/stm32l4x5_exti.h @@ -30,7 +30,7 @@ #define TYPE_STM32L4X5_EXTI "stm32l4x5-exti" OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5ExtiState, STM32L4X5_EXTI) -#define EXTI_NUM_INTERRUPT_OUT_LINES 40 +#define EXTI_NUM_LINES 40 #define EXTI_NUM_REGISTER 2 struct Stm32l4x5ExtiState { @@ -47,7 +47,7 @@ struct Stm32l4x5ExtiState { /* used for edge detection */ uint32_t irq_levels[EXTI_NUM_REGISTER]; - qemu_irq irq[EXTI_NUM_INTERRUPT_OUT_LINES]; + qemu_irq irq[EXTI_NUM_LINES]; }; #endif diff --git a/hw/misc/stm32l4x5_exti.c b/hw/misc/stm32l4x5_exti.c index 6a2ec62d78..b9a69a69f6 100644 --- a/hw/misc/stm32l4x5_exti.c +++ b/hw/misc/stm32l4x5_exti.c @@ -42,7 +42,6 @@ #define EXTI_SWIER2 0x30 #define EXTI_PR2 0x34 -#define EXTI_NUM_GPIO_EVENT_IN_LINES 16 #define EXTI_MAX_IRQ_PER_BANK 32 #define EXTI_IRQS_BANK0 32 #define EXTI_IRQS_BANK1 8 @@ -238,7 +237,7 @@ static void stm32l4x5_exti_init(Object *obj) { Stm32l4x5ExtiState *s = STM32L4X5_EXTI(obj); - for (size_t i = 0; i < EXTI_NUM_INTERRUPT_OUT_LINES; i++) { + for (size_t i = 0; i < EXTI_NUM_LINES; i++) { sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]); } @@ -246,8 +245,7 @@ static void stm32l4x5_exti_init(Object *obj) TYPE_STM32L4X5_EXTI, 0x400); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); - qdev_init_gpio_in(DEVICE(obj), stm32l4x5_exti_set_irq, - EXTI_NUM_GPIO_EVENT_IN_LINES); + qdev_init_gpio_in(DEVICE(obj), stm32l4x5_exti_set_irq, EXTI_NUM_LINES); } static const VMStateDescription vmstate_stm32l4x5_exti = { From patchwork Sun Jul 7 08:58:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?In=C3=A8s_Varhol?= X-Patchwork-Id: 1957664 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=telecom-paris.fr header.i=@telecom-paris.fr header.a=rsa-sha256 header.s=A35C7578-1106-11E5-A17F-C303FDDA8F2E header.b=BbJ/Ms7/; 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Sun, 7 Jul 2024 10:59:36 +0200 (CEST) Received: from inesv-Inspiron-3501.enst.fr (unknown [IPv6:2a04:8ec0:0:124::190c]) by zproxy4.enst.fr (Postfix) with ESMTPSA id 08DD02076A; Sun, 7 Jul 2024 10:59:35 +0200 (CEST) From: =?utf-8?q?In=C3=A8s_Varhol?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Alistair Francis , =?utf-8?q?In=C3=A8s_Varhol?= , Arnaud Minier , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= , Peter Maydell Subject: [PATCH v3 2/3] hw/misc: In STM32L4x5 EXTI, handle direct interrupts Date: Sun, 7 Jul 2024 10:58:54 +0200 Message-ID: <20240707085927.122867-3-ines.varhol@telecom-paris.fr> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240707085927.122867-1-ines.varhol@telecom-paris.fr> References: <20240707085927.122867-1-ines.varhol@telecom-paris.fr> MIME-Version: 1.0 Received-SPF: pass client-ip=137.194.2.223; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy4.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The previous implementation for EXTI interrupts only handled "configurable" interrupts, like those originating from STM32L4x5 SYSCFG (the only device currently connected to the EXTI up until now). In order to connect STM32L4x5 USART to the EXTI, this commit adds handling for direct interrupts (interrupts without configurable edge). Signed-off-by: Inès Varhol --- hw/misc/stm32l4x5_exti.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/misc/stm32l4x5_exti.c b/hw/misc/stm32l4x5_exti.c index b9a69a69f6..e281841dcf 100644 --- a/hw/misc/stm32l4x5_exti.c +++ b/hw/misc/stm32l4x5_exti.c @@ -113,6 +113,13 @@ static void stm32l4x5_exti_set_irq(void *opaque, int irq, int level) return; } + /* In case of a direct line interrupt */ + if (extract32(exti_romask[bank], irq, 1)) { + qemu_set_irq(s->irq[oirq], level); + return; + } + + /* In case of a configurable interrupt */ if ((level && extract32(s->rtsr[bank], irq, 1)) || (!level && extract32(s->ftsr[bank], irq, 1))) { From patchwork Sun Jul 7 08:58:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?In=C3=A8s_Varhol?= X-Patchwork-Id: 1957665 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Sun, 7 Jul 2024 10:59:37 +0200 (CEST) Received: from inesv-Inspiron-3501.enst.fr (unknown [IPv6:2a04:8ec0:0:124::190c]) by zproxy4.enst.fr (Postfix) with ESMTPSA id C9A9120775; Sun, 7 Jul 2024 10:59:36 +0200 (CEST) From: =?utf-8?q?In=C3=A8s_Varhol?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Alistair Francis , =?utf-8?q?In=C3=A8s_Varhol?= , Arnaud Minier , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= , Peter Maydell Subject: [PATCH v3 3/3] hw/arm: In STM32L4x5 SOC, connect USART devices to EXTI Date: Sun, 7 Jul 2024 10:58:55 +0200 Message-ID: <20240707085927.122867-4-ines.varhol@telecom-paris.fr> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240707085927.122867-1-ines.varhol@telecom-paris.fr> References: <20240707085927.122867-1-ines.varhol@telecom-paris.fr> MIME-Version: 1.0 Received-SPF: pass client-ip=137.194.2.223; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy4.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The USART devices were previously connecting their outbound IRQs directly to the CPU because the EXTI wasn't handling direct lines interrupts. Now the USART connects to the EXTI inbound GPIOs, and the EXTI connects its IRQs to the CPU. The existing QTest for the USART (tests/qtest/stm32l4x5_usart-test.c) checks that USART1_IRQ in the CPU is pending when expected so it confirms that the connection through the EXTI still works. Signed-off-by: Inès Varhol Reviewed-by: Peter Maydell --- hw/arm/stm32l4x5_soc.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c index 38f7a2d5d9..fac83d349c 100644 --- a/hw/arm/stm32l4x5_soc.c +++ b/hw/arm/stm32l4x5_soc.c @@ -81,6 +81,10 @@ static const int exti_irq[NUM_EXTI_IRQ] = { #define RCC_BASE_ADDRESS 0x40021000 #define RCC_IRQ 5 +#define EXTI_USART1_IRQ 26 +#define EXTI_UART4_IRQ 29 +#define EXTI_LPUART1_IRQ 31 + static const int exti_or_gates_out[NUM_EXTI_OR_GATES] = { 23, 40, 63, 1, }; @@ -129,10 +133,6 @@ static const hwaddr uart_addr[] = { #define LPUART_BASE_ADDRESS 0x40008000 -static const int usart_irq[] = { 37, 38, 39 }; -static const int uart_irq[] = { 52, 53 }; -#define LPUART_IRQ 70 - static void stm32l4x5_soc_initfn(Object *obj) { Stm32l4x5SocState *s = STM32L4X5_SOC(obj); @@ -297,6 +297,7 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) } } + /* Connect SYSCFG to EXTI */ for (unsigned i = 0; i < GPIO_NUM_PINS; i++) { qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(DEVICE(&s->exti), i)); @@ -322,15 +323,10 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) return; } sysbus_mmio_map(busdev, 0, usart_addr[i]); - sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i])); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->exti), + EXTI_USART1_IRQ + i)); } - /* - * TODO: Connect the USARTs, UARTs and LPUART to the EXTI once the EXTI - * can handle other gpio-in than the gpios. (e.g. Direct Lines for the - * usarts) - */ - /* UART devices */ for (int i = 0; i < STM_NUM_UARTS; i++) { g_autofree char *name = g_strdup_printf("uart%d-out", STM_NUM_USARTS + i + 1); @@ -343,7 +339,8 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) return; } sysbus_mmio_map(busdev, 0, uart_addr[i]); - sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, uart_irq[i])); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->exti), + EXTI_UART4_IRQ + i)); } /* LPUART device*/ @@ -356,7 +353,8 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) return; } sysbus_mmio_map(busdev, 0, LPUART_BASE_ADDRESS); - sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, LPUART_IRQ)); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->exti), + EXTI_LPUART1_IRQ)); /* APB1 BUS */ create_unimplemented_device("TIM2", 0x40000000, 0x400);