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([49.37.251.185]) by smtp.gmail.com with ESMTPSA id e8-20020a170902784800b001dd1096e365sm2105732pln.281.2024.03.14.12.00.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Mar 2024 12:00:03 -0700 (PDT) From: Himanshu Chauhan To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: ajones@ventanamicro.com Subject: [PATCH v7 1/4] target/riscv: Check for valid itimer pointer before free Date: Fri, 15 Mar 2024 00:29:54 +0530 Message-Id: <20240314185957.36940-2-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240314185957.36940-1-hchauhan@ventanamicro.com> References: <20240314185957.36940-1-hchauhan@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=hchauhan@ventanamicro.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Check if each element of array of pointers for itimer contains a non-null pointer before freeing. Signed-off-by: Himanshu Chauhan Reviewed-by: Alistair Francis --- target/riscv/debug.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index e30d99cc2f..5f14b39b06 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -938,7 +938,10 @@ void riscv_trigger_reset_hold(CPURISCVState *env) env->tdata3[i] = 0; env->cpu_breakpoint[i] = NULL; env->cpu_watchpoint[i] = NULL; - timer_del(env->itrigger_timer[i]); + if (env->itrigger_timer[i]) { + timer_del(env->itrigger_timer[i]); + env->itrigger_timer[i] = NULL; + } } env->mcontext = 0; From patchwork Thu Mar 14 18:59:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Himanshu Chauhan X-Patchwork-Id: 1912213 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=DUsFJfmG; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TwcD85pVnz1yWn for ; Fri, 15 Mar 2024 06:01:12 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rkqJN-0000tz-IY; Thu, 14 Mar 2024 15:00:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rkqJG-0000rv-PU for qemu-devel@nongnu.org; Thu, 14 Mar 2024 15:00:11 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rkqJD-0001Ad-Vu for qemu-devel@nongnu.org; Thu, 14 Mar 2024 15:00:10 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-6e6c38be762so305941b3a.1 for ; Thu, 14 Mar 2024 12:00:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1710442806; x=1711047606; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yWmALFGWJKqYhXbwjbmytVpu9a+2H7aO4i8AojXFIjw=; b=DUsFJfmGGKRBJo/p60TZc6/fURYfb/9UjYArEZvy4AQm1eXTnc5N4NkzPVd99ov+8F qloCwZnueSO5OhPN3bo7gA3N+d9KE8ZC013ON6f2VjoewRscySfNM6+rFLB+Dbta3yXz lgr9YSb0vxPLGI9IyFUvASLMqHRzkSRzBp1WulBNfgYIVj++Rxzp3ocSWeMaCkJxNwtB nrryBXYMpUdN3ZYXRUtasc4xZUSOWXOURYfyqI2OE96Yr2kyJI9wjZUW6KQeHv+t99vA ChejBJJbl+CSFp0zAamhXdiWRjUwLo3H8yxYVvGlCh2+TdGHv2H9IOJceIUi5+ZxvWZ8 sg7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710442806; x=1711047606; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yWmALFGWJKqYhXbwjbmytVpu9a+2H7aO4i8AojXFIjw=; b=rqUoRLzC5xHxssryZ7zn/Uspgea5uXXatBQxcIOxqzwEFN8QMuRmTz0HQDzUjfJ6pD oqqXhjgR7GNy4gwfUg/84zcBp5SdgYPPq0H8RgRYa0Ayw8qYnfWAvFW/YlV7iCsHoBjK XRVv5LfwlalxKIxS4hR/XuVTOI5jH74GpfNVJJWWH+mIcVJQs4WrCqhQCHcRNJ63AXXU +9uQY0Ksp8K6onycEW+7l5tOCoVp3mb2PF28iEZD+fTgL4FyZoOo9teysht885MoA0t9 UFGVFPBD9ip8qj8Ae0WHu8Uob/KsNdm+cY3Rm6GkdRMEM+NH71q5KKs02KoT41+nC33E 4Cvg== X-Forwarded-Encrypted: i=1; AJvYcCX5q6DD1N+0iuXVqgNkahgO+qtoJzKzseVLLYyKZ4E8FMzIzobZxdxFyfy3knOPtbgHr51ARoisgBLNkAKsOqmHDBDZuwU= X-Gm-Message-State: AOJu0YzAz0WVH5JrBLd2etZM7V7ZEvgtRTj9UdqcYNq8wdcQxdirLdD0 nwGPrqp34kQ9852cYJkyFKteCCPu2fBLg8kpJfryQT+rH7KdrupjGOBznn0nSMY= X-Google-Smtp-Source: AGHT+IEmklMbPNblmgYzog+waxoaGUxpVNb092swQ+ts2Nq7ARiS94SzzW0hVBUStxwerJFJMq30zg== X-Received: by 2002:a05:6a20:958c:b0:1a1:7528:b45e with SMTP id iu12-20020a056a20958c00b001a17528b45emr3328579pzb.3.1710442805833; Thu, 14 Mar 2024 12:00:05 -0700 (PDT) Received: from aryabhatta.. ([49.37.251.185]) by smtp.gmail.com with ESMTPSA id e8-20020a170902784800b001dd1096e365sm2105732pln.281.2024.03.14.12.00.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Mar 2024 12:00:05 -0700 (PDT) From: Himanshu Chauhan To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: ajones@ventanamicro.com Subject: [PATCH v7 2/4] target/riscv: Enable mcontrol6 triggers only when sdtrig is selected Date: Fri, 15 Mar 2024 00:29:55 +0530 Message-Id: <20240314185957.36940-3-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240314185957.36940-1-hchauhan@ventanamicro.com> References: <20240314185957.36940-1-hchauhan@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=hchauhan@ventanamicro.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The mcontrol6 triggers are not defined in debug specification v0.13 These triggers are defined in sdtrig ISA extension. This patch: * Adds ext_sdtrig capability which is used to select mcontrol6 triggers * Keeps the debug property. All triggers that are defined in v0.13 are exposed. Signed-off-by: Himanshu Chauhan Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 +++++ target/riscv/cpu_cfg.h | 1 + target/riscv/debug.c | 30 +++++++++++++++++++++++++----- 3 files changed, 31 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c160b9216b..ab631500ac 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1008,6 +1008,11 @@ static void riscv_cpu_reset_hold(Object *obj) set_default_nan_mode(1, &env->fp_status); #ifndef CONFIG_USER_ONLY + if (!cpu->cfg.debug && cpu->cfg.ext_sdtrig) { + warn_report("Enabling 'debug' since 'sdtrig' is enabled."); + cpu->cfg.debug = true; + } + if (cpu->cfg.debug) { riscv_trigger_reset_hold(env); } diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 2040b90da0..0c57e1acd4 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -114,6 +114,7 @@ struct RISCVCPUConfig { bool ext_zvfbfwma; bool ext_zvfh; bool ext_zvfhmin; + bool ext_sdtrig; bool ext_smaia; bool ext_ssaia; bool ext_sscofpmf; diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 5f14b39b06..c40e727e12 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -100,13 +100,16 @@ static trigger_action_t get_trigger_action(CPURISCVState *env, target_ulong tdata1 = env->tdata1[trigger_index]; int trigger_type = get_trigger_type(env, trigger_index); trigger_action_t action = DBG_ACTION_NONE; + const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); switch (trigger_type) { case TRIGGER_TYPE_AD_MATCH: action = (tdata1 & TYPE2_ACTION) >> 12; break; case TRIGGER_TYPE_AD_MATCH6: - action = (tdata1 & TYPE6_ACTION) >> 12; + if (cfg->ext_sdtrig) { + action = (tdata1 & TYPE6_ACTION) >> 12; + } break; case TRIGGER_TYPE_INST_CNT: case TRIGGER_TYPE_INT: @@ -727,7 +730,12 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val) type2_reg_write(env, env->trigger_cur, tdata_index, val); break; case TRIGGER_TYPE_AD_MATCH6: - type6_reg_write(env, env->trigger_cur, tdata_index, val); + if (riscv_cpu_cfg(env)->ext_sdtrig) { + type6_reg_write(env, env->trigger_cur, tdata_index, val); + } else { + qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n", + trigger_type); + } break; case TRIGGER_TYPE_INST_CNT: itrigger_reg_write(env, env->trigger_cur, tdata_index, val); @@ -750,9 +758,13 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val) target_ulong tinfo_csr_read(CPURISCVState *env) { - /* assume all triggers support the same types of triggers */ - return BIT(TRIGGER_TYPE_AD_MATCH) | - BIT(TRIGGER_TYPE_AD_MATCH6); + target_ulong ts = BIT(TRIGGER_TYPE_AD_MATCH); + + if (riscv_cpu_cfg(env)->ext_sdtrig) { + ts |= BIT(TRIGGER_TYPE_AD_MATCH6); + } + + return ts; } void riscv_cpu_debug_excp_handler(CPUState *cs) @@ -803,6 +815,10 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) } break; case TRIGGER_TYPE_AD_MATCH6: + if (!cpu->cfg.ext_sdtrig) { + break; + } + ctrl = env->tdata1[i]; pc = env->tdata2[i]; @@ -869,6 +885,10 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) } break; case TRIGGER_TYPE_AD_MATCH6: + if (!cpu->cfg.ext_sdtrig) { + break; + } + ctrl = env->tdata1[i]; addr = env->tdata2[i]; flags = 0; From patchwork Thu Mar 14 18:59:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Himanshu Chauhan X-Patchwork-Id: 1912216 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=bgPlMWxo; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TwcF2170sz1yWn for ; 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([49.37.251.185]) by smtp.gmail.com with ESMTPSA id e8-20020a170902784800b001dd1096e365sm2105732pln.281.2024.03.14.12.00.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Mar 2024 12:00:07 -0700 (PDT) From: Himanshu Chauhan To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: ajones@ventanamicro.com Subject: [PATCH v7 3/4] target/riscv: Expose sdtrig ISA extension Date: Fri, 15 Mar 2024 00:29:56 +0530 Message-Id: <20240314185957.36940-4-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240314185957.36940-1-hchauhan@ventanamicro.com> References: <20240314185957.36940-1-hchauhan@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=hchauhan@ventanamicro.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds "sdtrig" in the ISA string when sdtrig extension is enabled. The sdtrig extension may or may not be implemented in a system. Therefore, the -cpu rv64,sdtrig= option can be used to dynamically turn sdtrig extension on or off. By default, the sdtrig extension is disabled and debug property enabled as usual. Signed-off-by: Himanshu Chauhan Acked-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ab631500ac..4231f36c1b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -175,6 +175,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), + ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, ext_sdtrig), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), @@ -1485,6 +1486,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("zvfhmin", ext_zvfhmin, false), MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), + MULTI_EXT_CFG_BOOL("sdtrig", ext_sdtrig, false), MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), From patchwork Thu Mar 14 18:59:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Himanshu Chauhan X-Patchwork-Id: 1912214 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=jEEmYD4D; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TwcD95RFxz23qV for ; Fri, 15 Mar 2024 06:01:13 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rkqJa-0000y5-5k; Thu, 14 Mar 2024 15:00:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rkqJL-0000uB-4L for qemu-devel@nongnu.org; Thu, 14 Mar 2024 15:00:16 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rkqJI-0001Bq-Aa for qemu-devel@nongnu.org; Thu, 14 Mar 2024 15:00:14 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1dde367a10aso1049925ad.0 for ; Thu, 14 Mar 2024 12:00:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1710442810; x=1711047610; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7PdUtes9ZeJi0r/RaS+r6xezQWnZNbnpGDB/vC3+/Kw=; b=jEEmYD4DFCU7O4aXkOZocF4O/RdqG/9+HP08Nqc2/DKcvQCpjeUaSWdMY35G0e/V8W uP0rxmuJyQFrlLF7ypQXrZh++f2pqAneBLoLbrbTLQ2zf/cisQnriIFT2G44AB+Mq48Z ePe4NNnFwa6zWq/rqttkPGS0HfE2SLHJjkARKOeYjfvMBXYfVJAbQntbM5rnWzMhA9vi 2L9Iwj4UPVEdBlxWC0QiZlThIsB+ABJ0HWOW8dGZzeaCqDuRiTYIMOYMWtznrmmrgqFz aEbrKzr6ASeT1xZS7ND8a8M+aubsk+28PPpz4Cj4k9UX1L0gpjROW7kkX+ygX3sJ5qKm QWpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710442810; x=1711047610; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7PdUtes9ZeJi0r/RaS+r6xezQWnZNbnpGDB/vC3+/Kw=; b=YETAftnWaOb+IBjh+US80mOg0X7vebTFuMxgPFwWWrU1s1T5iWFfp7SM/SogYzAeW/ c9rtNO4tc350ERWh36c+gY6sKRGnF0k1u8aCkRlg5SvDvZ/kvVVCRPjGEYhFA5lGycGL B2p6hhxQVgIAQZEKz/HcW+1ZrL5EjJVgfVvHllWTCWVPsgUyDPUOoE9Ci93rdh8jyGKD zELrSWsUCWBuiix/sQespNhAE0XlbC61PfA5tNj1nWxO/LN8hi364hS9lK2+EJAFEFzU Uk+4KUGf0agWZhTfXl6I45FfLXnz/gFHfTS/WMnZT4xGEvNZ7RU2nrEJjDmy0OH6TMbZ L3hg== X-Forwarded-Encrypted: i=1; AJvYcCUzxGN4FYQzYvwTLcFZitIIuiJyK3BnFZEVV78hPhbmUNyPbDEQ2zJOkvH++x+bgXdNrmsWtjsvhS3DyMn+V485BAGkeXE= X-Gm-Message-State: AOJu0YyVxhka2cnzQqcX5k56eleVs76n8dRv84kCCFSlYJkz9sp2rncK 52hh9y3zjygMkxw+6c21Mep+IFL69H3lNg07rHNOEK/9ca25HjJd/5CzWVCtgsk= X-Google-Smtp-Source: AGHT+IFQHmlW28X5dP8uE7vZ3eMNuwm37pY0qeYuTiWzScGee5MtyP3VzZO8uKn4iD58GGZEN/95WA== X-Received: by 2002:a17:903:1386:b0:1de:ddc6:27a6 with SMTP id jx6-20020a170903138600b001deddc627a6mr2193638plb.2.1710442810384; Thu, 14 Mar 2024 12:00:10 -0700 (PDT) Received: from aryabhatta.. ([49.37.251.185]) by smtp.gmail.com with ESMTPSA id e8-20020a170902784800b001dd1096e365sm2105732pln.281.2024.03.14.12.00.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Mar 2024 12:00:09 -0700 (PDT) From: Himanshu Chauhan To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: ajones@ventanamicro.com Subject: [PATCH v7 4/4] target/riscv: Enable sdtrig for Ventana's Veyron CPUs Date: Fri, 15 Mar 2024 00:29:57 +0530 Message-Id: <20240314185957.36940-5-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240314185957.36940-1-hchauhan@ventanamicro.com> References: <20240314185957.36940-1-hchauhan@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=hchauhan@ventanamicro.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Ventana's Veyron CPUs support sdtrig ISA extension. By default, enable the sdtrig extension and disable the debug property for these CPUs. Signed-off-by: Himanshu Chauhan --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4231f36c1b..c9dda73748 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -569,6 +569,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj) cpu->cfg.cbom_blocksize = 64; cpu->cfg.cboz_blocksize = 64; cpu->cfg.ext_zicboz = true; + cpu->cfg.ext_sdtrig = true; cpu->cfg.ext_smaia = true; cpu->cfg.ext_ssaia = true; cpu->cfg.ext_sscofpmf = true;