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([177.94.15.159]) by smtp.gmail.com with ESMTPSA id z10-20020a1709028f8a00b001db7709b322sm2774053plo.298.2024.02.16.03.28.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 03:28:16 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, richard.henderson@linaro.org, max.chou@sifive.com, Daniel Henrique Barboza Subject: [PATCH 1/3] trans_rvv.c.inc: write CSRs must call mark_vs_dirty() too Date: Fri, 16 Feb 2024 08:28:04 -0300 Message-ID: <20240216112806.997948-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216112806.997948-1-dbarboza@ventanamicro.com> References: <20240216112806.997948-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In the Vector spec section 3.2 [1]: "When mstatus.VS is set to Initial or Clean, executing any instruction that changes vector state, including the vector CSRs, will change mstatus.VS to Dirty." ldst_us_trans(), ldst_stride_trans(), ldst_index_trans() and ldst_whole_trans() will change vector state regardless of being a store op or not. Stores will set env->vstart to zero after execution (see vext_ldst_us() in vector_helper.c), and this is vector CSR state change. [1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-start-index-csr-vstart Fixes: 8e1ee1fb57 ("target/riscv: rvv-1.0: add translation-time vector context status") Signed-off-by: Daniel Henrique Barboza --- target/riscv/insn_trans/trans_rvv.c.inc | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 9e101ab434..044c9c903e 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -638,10 +638,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, fn(dest, mask, base, tcg_env, desc); - if (!is_store) { - mark_vs_dirty(s); - } - + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -799,10 +796,7 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2, fn(dest, mask, base, stride, tcg_env, desc); - if (!is_store) { - mark_vs_dirty(s); - } - + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -906,10 +900,7 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, fn(dest, mask, base, index, tcg_env, desc); - if (!is_store) { - mark_vs_dirty(s); - } - + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -1104,9 +1095,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf, fn(dest, base, tcg_env, desc); - if (!is_store) { - mark_vs_dirty(s); - } + mark_vs_dirty(s); gen_set_label(over); return true; From patchwork Fri Feb 16 11:28:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1900004 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=V+Ygxg4V; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; 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([177.94.15.159]) by smtp.gmail.com with ESMTPSA id z10-20020a1709028f8a00b001db7709b322sm2774053plo.298.2024.02.16.03.28.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 03:28:19 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, richard.henderson@linaro.org, max.chou@sifive.com, Daniel Henrique Barboza Subject: [PATCH 2/3] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls Date: Fri, 16 Feb 2024 08:28:05 -0300 Message-ID: <20240216112806.997948-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216112806.997948-1-dbarboza@ventanamicro.com> References: <20240216112806.997948-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org trans_vmv_v_i , trans_vfmv_v_f and the trans_##NAME macro from GEN_VMV_WHOLE_TRANS() are calling mark_vs_dirty() in both branches of their 'ifs'. conditionals. Call it just once in the end like other functions are doing. Signed-off-by: Daniel Henrique Barboza --- target/riscv/insn_trans/trans_rvv.c.inc | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 044c9c903e..778e2723dd 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2094,7 +2094,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a) if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), simm); - mark_vs_dirty(s); } else { TCGv_i32 desc; TCGv_i64 s1; @@ -2115,9 +2114,9 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a) tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd)); fns[s->sew](dest, s1, tcg_env, desc); - mark_vs_dirty(s); gen_set_label(over); } + mark_vs_dirty(s); return true; } return false; @@ -2660,7 +2659,6 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), t1); - mark_vs_dirty(s); } else { TCGv_ptr dest; TCGv_i32 desc; @@ -2686,9 +2684,9 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) fns[s->sew - 1](dest, t1, tcg_env, desc); - mark_vs_dirty(s); gen_set_label(over); } + mark_vs_dirty(s); return true; } return false; @@ -3632,15 +3630,14 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ if (s->vstart_eq_zero) { \ tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd), \ vreg_ofs(s, a->rs2), maxsz, maxsz); \ - mark_vs_dirty(s); \ } else { \ TCGLabel *over = gen_new_label(); \ tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over); \ tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \ tcg_env, maxsz, maxsz, 0, gen_helper_vmvr_v); \ - mark_vs_dirty(s); \ gen_set_label(over); \ } \ + mark_vs_dirty(s); \ return true; \ } \ return false; \ From patchwork Fri Feb 16 11:28:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1900003 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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([177.94.15.159]) by smtp.gmail.com with ESMTPSA id z10-20020a1709028f8a00b001db7709b322sm2774053plo.298.2024.02.16.03.28.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 03:28:23 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, richard.henderson@linaro.org, max.chou@sifive.com, Daniel Henrique Barboza Subject: [PATCH 3/3] target/riscv/translate.c: set vstart_eq_zero in mark_vs_dirty() Date: Fri, 16 Feb 2024 08:28:06 -0300 Message-ID: <20240216112806.997948-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216112806.997948-1-dbarboza@ventanamicro.com> References: <20240216112806.997948-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The 'vstart_eq_zero' flag which is used to determine if some insns, like vector reductor operations, should SIGILL. At this moment the flag is being updated only during cpu_get_tb_cpu_state(), at the start of each translation block. This cadence isn't enough and we're facing situations where a vector instruction successfully updated 'vstart' to zero, but the flag was still marked as 'false', resulting in a SIGILL because instructions are checking the flag. mark_vs_dirty() is called after any instruction changes Vector CSR state, making it a good place to update 'vstart_eq_zero'. Fixes: 8e1ee1fb57 ("target/riscv: rvv-1.0: add translation-time vector context status") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1976 Signed-off-by: Daniel Henrique Barboza --- target/riscv/translate.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 177418b2b9..9943538894 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -652,9 +652,13 @@ static inline void mark_fs_dirty(DisasContext *ctx) { } */ static void mark_vs_dirty(DisasContext *ctx) { + TCGLabel *vstart_zero, *done; TCGv tmp; if (ctx->mstatus_vs != EXT_STATUS_DIRTY) { + vstart_zero = gen_new_label(); + done = gen_new_label(); + /* Remember the state change for the rest of the TB. */ ctx->mstatus_vs = EXT_STATUS_DIRTY; @@ -668,6 +672,24 @@ static void mark_vs_dirty(DisasContext *ctx) tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); } + + /* + * We can safely make 'vl_eq_vlmax = false' if we marked + * VS as dirty with non-zero 'vstart', i.e. there's a fault + * to be handled. If 'vstart' is zero then we should retain + * the existing 'vl_eq_vlmax' - it'll be recalculated on the + * start of the next TB or during vset{i}vl{i} (that forces a + * TB end). + */ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vstart, 0, vstart_zero); + ctx->vstart_eq_zero = false; + ctx->vl_eq_vlmax = false; + tcg_gen_br(done); + + gen_set_label(vstart_zero); + ctx->vstart_eq_zero = true; + + gen_set_label(done); } } #else