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Tue, 09 Jan 2024 20:02:11 -0800 (PST) Received: from brahaspati.localdomain ([152.58.210.84]) by smtp.gmail.com with ESMTPSA id ca8-20020a17090af30800b0028cf4cb2c85sm313893pjb.40.2024.01.09.20.02.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 20:02:11 -0800 (PST) From: Himanshu Chauhan To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/2] target/riscv: Export sdtrig as an extension and ISA string Date: Wed, 10 Jan 2024 09:32:02 +0530 Message-Id: <20240110040203.1920924-2-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240110040203.1920924-1-hchauhan@ventanamicro.com> References: <20240110040203.1920924-1-hchauhan@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=hchauhan@ventanamicro.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch makes the debug trigger (sdtrig) capability as an extension and exports it as an ISA string. The sdtrig extension may or may not be implemented in a system. The -cpu rv64,sdtrig= option can be used to dynamicaly turn sdtrig extension on or off. Signed-off-by: Himanshu Chauhan --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 1 + 2 files changed, 3 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b07a76ef6b..aaa2d4ff1d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -143,6 +143,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), + ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, ext_sdtrig), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), @@ -1306,6 +1307,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false), MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), + MULTI_EXT_CFG_BOOL("sdtrig", ext_sdtrig, true), MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index f4605fb190..3d3acc7f90 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -113,6 +113,7 @@ struct RISCVCPUConfig { bool ext_ssaia; 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Tue, 09 Jan 2024 20:02:13 -0800 (PST) Received: from brahaspati.localdomain ([152.58.210.84]) by smtp.gmail.com with ESMTPSA id ca8-20020a17090af30800b0028cf4cb2c85sm313893pjb.40.2024.01.09.20.02.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 20:02:13 -0800 (PST) From: Himanshu Chauhan To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/2] target/riscv: Raise an exception when sdtrig is turned off Date: Wed, 10 Jan 2024 09:32:03 +0530 Message-Id: <20240110040203.1920924-3-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240110040203.1920924-1-hchauhan@ventanamicro.com> References: <20240110040203.1920924-1-hchauhan@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=hchauhan@ventanamicro.com; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org When sdtrig is turned off by "sdtrig=false" option, raise and illegal instruction exception on any read/write to sdtrig CSRs. Signed-off-by: Himanshu Chauhan --- target/riscv/csr.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c50a33397c..b9ca016ef2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3854,6 +3854,10 @@ static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, static RISCVException read_tselect(CPURISCVState *env, int csrno, target_ulong *val) { + if (!riscv_cpu_cfg(env)->ext_sdtrig) { + return RISCV_EXCP_ILLEGAL_INST; + } + *val = tselect_csr_read(env); return RISCV_EXCP_NONE; } @@ -3861,6 +3865,10 @@ static RISCVException read_tselect(CPURISCVState *env, int csrno, static RISCVException write_tselect(CPURISCVState *env, int csrno, target_ulong val) { + if (!riscv_cpu_cfg(env)->ext_sdtrig) { + return RISCV_EXCP_ILLEGAL_INST; + } + tselect_csr_write(env, val); return RISCV_EXCP_NONE; } @@ -3868,6 +3876,10 @@ static RISCVException write_tselect(CPURISCVState *env, int csrno, static RISCVException read_tdata(CPURISCVState *env, int csrno, target_ulong *val) { + if (!riscv_cpu_cfg(env)->ext_sdtrig) { + return RISCV_EXCP_ILLEGAL_INST; + } + /* return 0 in tdata1 to end the trigger enumeration */ if (env->trigger_cur >= RV_MAX_TRIGGERS && csrno == CSR_TDATA1) { *val = 0; @@ -3885,6 +3897,10 @@ static RISCVException read_tdata(CPURISCVState *env, int csrno, static RISCVException write_tdata(CPURISCVState *env, int csrno, target_ulong val) { + if (!riscv_cpu_cfg(env)->ext_sdtrig) { + return RISCV_EXCP_ILLEGAL_INST; + } + if (!tdata_available(env, csrno - CSR_TDATA1)) { return RISCV_EXCP_ILLEGAL_INST; } @@ -3896,6 +3912,10 @@ static RISCVException write_tdata(CPURISCVState *env, int csrno, static RISCVException read_tinfo(CPURISCVState *env, int csrno, target_ulong *val) { + if (!riscv_cpu_cfg(env)->ext_sdtrig) { + return RISCV_EXCP_ILLEGAL_INST; + } + *val = tinfo_csr_read(env); return RISCV_EXCP_NONE; }