From patchwork Wed Jan 3 00:12:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1881799 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T4VZ26JXnz23d9 for ; Wed, 3 Jan 2024 11:13:46 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2DD3187980; Wed, 3 Jan 2024 01:13:35 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 8BB6C878D3; Wed, 3 Jan 2024 01:13:34 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 6803E87927 for ; Wed, 3 Jan 2024 01:13:31 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0648614BF; Tue, 2 Jan 2024 16:14:17 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1B7583F5A1; Tue, 2 Jan 2024 16:13:29 -0800 (PST) From: Andre Przywara To: Jagan Teki Cc: Samuel Holland , linux-sunxi@lists.linux.dev, u-boot@lists.denx.de Subject: [PATCH 01/19] sunxi: cleanup sunxi-common.h Date: Wed, 3 Jan 2024 00:12:21 +0000 Message-Id: <20240103001239.17482-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20240103001239.17482-1-andre.przywara@arm.com> References: <20240103001239.17482-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The sunxi-common.h configs header used to contain a lot of random Allwinner platform related constants, but over the years we moved a lot of those definitions out there. Clean up the file to remove outdated comments which are leftovers from the olden days. Also remove the definition of LOW_LEVEL_SRAM_STACK, which is actually used nowhere in the whole source tree. This also uses the opportunity to add some section comments that helps structuring the header file and improving readability. Signed-off-by: Andre Przywara --- include/configs/sunxi-common.h | 56 ++++++++-------------------------- 1 file changed, 12 insertions(+), 44 deletions(-) diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index b8ca77d031d..b29a25d5617 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -14,8 +14,9 @@ #include -/* Serial & console */ -/* ns16550 reg in the low bits of cpu reg */ +/**************************************************************************** + * base addresses for the SPL UART driver * + ****************************************************************************/ #ifdef CONFIG_MACH_SUNIV /* suniv doesn't have apb2 and uart is connected to apb1 */ #define CFG_SYS_NS16550_CLK 100000000 @@ -31,8 +32,9 @@ # define CFG_SYS_NS16550_COM5 SUNXI_R_UART_BASE #endif -/* CPU */ - +/**************************************************************************** + * DRAM base address * + ****************************************************************************/ /* * The DRAM Base differs between some models. We cannot use macros for the * CONFIG_FOO defines which contain the DRAM base address since they end @@ -52,16 +54,6 @@ /* V3s do not have enough memory to place code at 0x4a000000 */ #endif -/* - * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is - * slightly bigger. Note that it is possible to map the first 32 KiB of the - * A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the - * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and - * the 1 actually activates the mapping of the first 32 KiB to 0x00000000. - * A64 and H5 also has SRAM A1 at 0x00010000, but no magic remap register - * is known yet. - * H6 has SRAM A1 at 0x00020000. - */ #define CFG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS /* FIXME: this may be larger on some SoCs */ #define CFG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ @@ -69,36 +61,13 @@ #define PHYS_SDRAM_0 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ -/* - * Miscellaneous configurable options - */ - -/* FLASH and environment organization */ - +/**************************************************************************** + * environment variables holding default load addresses * + ****************************************************************************/ /* * We cannot use expressions here, because expressions won't be evaluated in * autoconf.mk. */ -#if CONFIG_SUNXI_SRAM_ADDRESS == 0x10000 -#ifdef CONFIG_ARM64 -/* end of SRAM A2 for now, as SRAM A1 is pretty tight for an ARM64 build */ -#define LOW_LEVEL_SRAM_STACK 0x00054000 -#else -#define LOW_LEVEL_SRAM_STACK 0x00018000 -#endif /* !CONFIG_ARM64 */ -#elif CONFIG_SUNXI_SRAM_ADDRESS == 0x20000 -#ifdef CONFIG_MACH_SUN50I_H616 -#define LOW_LEVEL_SRAM_STACK 0x52a00 /* below FEL buffers */ -#else -/* end of SRAM A2 on H6 for now */ -#define LOW_LEVEL_SRAM_STACK 0x00118000 -#endif -#else -#define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ -#endif - -/* Ethernet support */ - #ifdef CONFIG_ARM64 /* * Boards seem to come with at least 512MB of DRAM. @@ -174,15 +143,11 @@ "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" #ifdef CONFIG_ARM64 - #define MEM_LAYOUT_ENV_EXTRA_SETTINGS \ "kernel_comp_addr_r=" KERNEL_COMP_ADDR_R "\0" \ "kernel_comp_size=" KERNEL_COMP_SIZE "\0" - #else - #define MEM_LAYOUT_ENV_EXTRA_SETTINGS "" - #endif #define DFU_ALT_INFO_RAM \ @@ -191,6 +156,9 @@ "fdt ram " FDT_ADDR_R " 0x100000;" \ "ramdisk ram " RAMDISK_ADDR_R " 0x4000000\0" +/**************************************************************************** + * definitions for the distro boot system * + ****************************************************************************/ #ifdef CONFIG_MMC #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 #define BOOTENV_DEV_MMC_AUTO(devtypeu, devtypel, instance) \ From patchwork Wed Jan 3 00:12:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1881800 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T4VZG1qx5z23d9 for ; Wed, 3 Jan 2024 11:13:57 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9681E8796B; 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Tue, 2 Jan 2024 16:14:18 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2751B3F5A1; Tue, 2 Jan 2024 16:13:31 -0800 (PST) From: Andre Przywara To: Jagan Teki Cc: Samuel Holland , linux-sunxi@lists.linux.dev, u-boot@lists.denx.de Subject: [PATCH 02/19] sunxi: sun50i-h6: remove unneeded base addresses from header Date: Wed, 3 Jan 2024 00:12:22 +0000 Message-Id: <20240103001239.17482-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20240103001239.17482-1-andre.przywara@arm.com> References: <20240103001239.17482-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The cpu_sun50i_h6.h header file defined the base addresses for quite some peripherals of the Allwinner H6 and related CPUs, even though we now only use a fraction of that. Most of the addresses are now either read from the DT, or were never used in U-Boot in the first place. Removed the ones that are not used in the whole of the U-Boot source. to make it clear that this file only contains addresses that are needed for the SPL operation. Signed-off-by: Andre Przywara --- .../include/asm/arch-sunxi/cpu_sun50i_h6.h | 21 ------------------- 1 file changed, 21 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h index 15ee092d358..8a3f465545a 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h @@ -7,25 +7,14 @@ #ifndef _SUNXI_CPU_SUN50I_H6_H #define _SUNXI_CPU_SUN50I_H6_H -#define SUNXI_SRAM_A1_BASE CONFIG_SUNXI_SRAM_ADDRESS -#define SUNXI_SRAM_C_BASE 0x00028000 -#define SUNXI_SRAM_A2_BASE 0x00100000 - -#define SUNXI_DE3_BASE 0x01000000 -#define SUNXI_SS_BASE 0x01904000 -#define SUNXI_EMCE_BASE 0x01905000 - #define SUNXI_SRAMC_BASE 0x03000000 #define SUNXI_CCM_BASE 0x03001000 -#define SUNXI_DMA_BASE 0x03002000 /* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */ #define SUNXI_SIDC_BASE 0x03006000 #define SUNXI_SID_BASE 0x03006200 #define SUNXI_TIMER_BASE 0x03009000 -#define SUNXI_PSI_BASE 0x0300C000 #define SUNXI_GIC400_BASE 0x03020000 -#define SUNXI_IOMMU_BASE 0x030F0000 #ifdef CONFIG_MACH_SUN50I_H6 #define SUNXI_DRAM_COM_BASE 0x04002000 @@ -46,18 +35,8 @@ #define SUNXI_TWI1_BASE 0x05002400 #define SUNXI_TWI2_BASE 0x05002800 #define SUNXI_TWI3_BASE 0x05002C00 -#define SUNXI_SPI0_BASE 0x05010000 -#define SUNXI_SPI1_BASE 0x05011000 -#define SUNXI_GMAC_BASE 0x05020000 -#define SUNXI_USB0_BASE 0x05100000 -#define SUNXI_XHCI_BASE 0x05200000 -#define SUNXI_USB3_BASE 0x05311000 -#define SUNXI_PCIE_BASE 0x05400000 #define SUNXI_HDMI_BASE 0x06000000 -#define SUNXI_TCON_TOP_BASE 0x06510000 -#define SUNXI_TCON_LCD0_BASE 0x06511000 -#define SUNXI_TCON_TV0_BASE 0x06515000 #define SUNXI_RTC_BASE 0x07000000 #define SUNXI_R_CPUCFG_BASE 0x07000400 From patchwork Wed Jan 3 00:12:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1881801 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T4VZS0mBqz23d9 for ; Wed, 3 Jan 2024 11:14:07 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 057D0879A9; Wed, 3 Jan 2024 01:13:37 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id AD02B8795C; Wed, 3 Jan 2024 01:13:35 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 854448796B for ; Wed, 3 Jan 2024 01:13:33 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1DC4C152B; Tue, 2 Jan 2024 16:14:19 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 331923F5A1; Tue, 2 Jan 2024 16:13:32 -0800 (PST) From: Andre Przywara To: Jagan Teki Cc: Samuel Holland , linux-sunxi@lists.linux.dev, u-boot@lists.denx.de Subject: [PATCH 03/19] sunxi: sun4i: remove unneeded base addresses from header Date: Wed, 3 Jan 2024 00:12:23 +0000 Message-Id: <20240103001239.17482-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20240103001239.17482-1-andre.przywara@arm.com> References: <20240103001239.17482-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The cpu_sun4i.h header file defined the base addresses for quite some peripherals of earlier Allwinner CPUs, even though we now only use a fraction of that. Most of the addresses are now either read from the DT, or were never used in U-Boot in the first place. Removed the ones that are not used in the whole of the U-Boot source. to make it clear that this file only contains addresses that are needed for the SPL operation. Signed-off-by: Andre Przywara --- arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 47 --------------------- 1 file changed, 47 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index 3daee2f574a..f023a4cfd93 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -36,58 +36,20 @@ #define SUNXI_SRAMC_BASE 0x01c00000 #define SUNXI_DRAMC_BASE 0x01c01000 -#define SUNXI_DMA_BASE 0x01c02000 #define SUNXI_NFC_BASE 0x01c03000 -#define SUNXI_TS_BASE 0x01c04000 -#define SUNXI_SPI0_BASE 0x01c05000 -#define SUNXI_SPI1_BASE 0x01c06000 -#define SUNXI_MS_BASE 0x01c07000 -#define SUNXI_TVD_BASE 0x01c08000 -#define SUNXI_CSI0_BASE 0x01c09000 #ifndef CONFIG_MACH_SUNXI_H3_H5 #define SUNXI_TVE0_BASE 0x01c0a000 #endif -#define SUNXI_EMAC_BASE 0x01c0b000 #define SUNXI_LCD0_BASE 0x01c0C000 #define SUNXI_LCD1_BASE 0x01c0d000 -#define SUNXI_VE_BASE 0x01c0e000 #define SUNXI_MMC0_BASE 0x01c0f000 #define SUNXI_MMC1_BASE 0x01c10000 #define SUNXI_MMC2_BASE 0x01c11000 #define SUNXI_MMC3_BASE 0x01c12000 -#ifdef CONFIG_SUNXI_GEN_SUN4I -#define SUNXI_USB0_BASE 0x01c13000 -#define SUNXI_USB1_BASE 0x01c14000 -#endif #define SUNXI_SS_BASE 0x01c15000 #if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) #define SUNXI_HDMI_BASE 0x01c16000 #endif -#define SUNXI_SPI2_BASE 0x01c17000 -#define SUNXI_SATA_BASE 0x01c18000 -#ifdef CONFIG_SUNXI_GEN_SUN4I -#define SUNXI_PATA_BASE 0x01c19000 -#define SUNXI_ACE_BASE 0x01c1a000 -#define SUNXI_TVE1_BASE 0x01c1b000 -#define SUNXI_USB2_BASE 0x01c1c000 -#endif -#ifdef CONFIG_SUNXI_GEN_SUN6I -#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) -#define SUNXI_USBPHY_BASE 0x01c19000 -#define SUNXI_USB0_BASE SUNXI_USBPHY_BASE -#define SUNXI_USB1_BASE 0x01c1a000 -#define SUNXI_USB2_BASE 0x01c1b000 -#define SUNXI_USB3_BASE 0x01c1c000 -#define SUNXI_USB4_BASE 0x01c1d000 -#else -#define SUNXI_USB0_BASE 0x01c19000 -#define SUNXI_USB1_BASE 0x01c1a000 -#define SUNXI_USB2_BASE 0x01c1b000 -#endif -#endif -#define SUNXI_CSI1_BASE 0x01c1d000 -#define SUNXI_TZASC_BASE 0x01c1e000 -#define SUNXI_SPI3_BASE 0x01c1f000 #define SUNXI_CCM_BASE 0x01c20000 #define SUNXI_INTC_BASE 0x01c20400 @@ -177,8 +139,6 @@ defined(CONFIG_MACH_SUN50I) #else #define SUNXI_TVE0_BASE 0x01e40000 #endif -#define SUNXI_MP_BASE 0x01e80000 -#define SUNXI_AVG_BASE 0x01ea0000 #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) #define SUNXI_HDMI_BASE 0x01ee0000 @@ -197,13 +157,6 @@ defined(CONFIG_MACH_SUN50I) #define SUN6I_P2WI_BASE 0x01f03400 #define SUNXI_RSB_BASE 0x01f03400 -/* CoreSight Debug Module */ -#define SUNXI_CSDM_BASE 0x3f500000 - -#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */ - -#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */ - #define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) /* SS bonding ids used for cpu identification */ From patchwork Wed Jan 3 00:12:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1881802 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T4VZd3T07z23dW for ; Wed, 3 Jan 2024 11:14:17 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 6E9B6879B3; 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Tue, 2 Jan 2024 16:14:20 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3ECFA3F5A1; Tue, 2 Jan 2024 16:13:33 -0800 (PST) From: Andre Przywara To: Jagan Teki Cc: Samuel Holland , linux-sunxi@lists.linux.dev, u-boot@lists.denx.de Subject: [PATCH 04/19] sunxi: sun9i: remove unneeded base addresses from header Date: Wed, 3 Jan 2024 00:12:24 +0000 Message-Id: <20240103001239.17482-5-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20240103001239.17482-1-andre.przywara@arm.com> References: <20240103001239.17482-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The cpu_sun9i.h header file defined the base addresses for quite some peripherals of the Allwinner A80 CPU, even though we now only use a fraction of that. Most of the addresses are now either read from the DT, or were never used in U-Boot in the first place. Removed the ones that are not used in the whole of the U-Boot source. to make it clear that this file only contains addresses that are needed for the SPL operation. Signed-off-by: Andre Przywara --- arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 41 --------------------- 1 file changed, 41 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h index 2bf2675d5c1..73de4707c16 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h @@ -20,7 +20,6 @@ /* AHB0 Module */ #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000) -#define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000) #define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000) /* SID address space starts at 0x01ce000, but e-fuse is at offset 0x200 */ @@ -32,14 +31,7 @@ #define SUNXI_MMC3_BASE (REGS_AHB0_BASE + 0x12000) #define SUNXI_MMC_COMMON_BASE (REGS_AHB0_BASE + 0x13000) -#define SUNXI_SPI0_BASE (REGS_AHB0_BASE + 0x1A000) -#define SUNXI_SPI1_BASE (REGS_AHB0_BASE + 0x1B000) -#define SUNXI_SPI2_BASE (REGS_AHB0_BASE + 0x1C000) -#define SUNXI_SPI3_BASE (REGS_AHB0_BASE + 0x1D000) - #define SUNXI_GIC400_BASE (REGS_AHB0_BASE + 0x40000) -#define SUNXI_ARMA9_GIC_BASE (REGS_AHB0_BASE + 0x41000) -#define SUNXI_ARMA9_CPUIF_BASE (REGS_AHB0_BASE + 0x42000) #define SUNXI_DRAM_COM_BASE (REGS_AHB0_BASE + 0x62000) #define SUNXI_DRAM_CTL0_BASE (REGS_AHB0_BASE + 0x63000) @@ -47,59 +39,26 @@ #define SUNXI_DRAM_PHY0_BASE (REGS_AHB0_BASE + 0x65000) #define SUNXI_DRAM_PHY1_BASE (REGS_AHB0_BASE + 0x66000) -/* AHB1 Module */ -#define SUNXI_DMA_BASE (REGS_AHB1_BASE + 0x002000) -#define SUNXI_USBOTG_BASE (REGS_AHB1_BASE + 0x100000) -#define SUNXI_USBEHCI0_BASE (REGS_AHB1_BASE + 0x200000) -#define SUNXI_USBEHCI1_BASE (REGS_AHB1_BASE + 0x201000) -#define SUNXI_USBEHCI2_BASE (REGS_AHB1_BASE + 0x202000) - -/* AHB2 Module */ -#define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000) -#define SUNXI_DISP_SYS_BASE (REGS_AHB2_BASE + 0x010000) #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000) -#define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000) -#define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000) - #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000) -#define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000) -#define SUNXI_DE_BE2_BASE (REGS_AHB2_BASE + 0x280000) - -#define SUNXI_DE_DEU0_BASE (REGS_AHB2_BASE + 0x300000) -#define SUNXI_DE_DEU1_BASE (REGS_AHB2_BASE + 0x340000) -#define SUNXI_DE_DRC0_BASE (REGS_AHB2_BASE + 0x400000) -#define SUNXI_DE_DRC1_BASE (REGS_AHB2_BASE + 0x440000) - #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000) #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000) #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000) -#define SUNXI_MIPI_DSI0_BASE (REGS_AHB2_BASE + 0xC40000) -/* Also seen as SUNXI_MIPI_DSI0_DPHY_BASE 0x01ca1000 */ -#define SUNXI_MIPI_DSI0_DPHY_BASE (REGS_AHB2_BASE + 0xC40100) #define SUNXI_HDMI_BASE (REGS_AHB2_BASE + 0xD00000) /* APB0 Module */ #define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000) -#define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400) #define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00) #define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400) -#define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800) /* APB1 Module */ #define SUNXI_TWI0_BASE (REGS_APB1_BASE + 0x2800) #define SUNXI_TWI1_BASE (REGS_APB1_BASE + 0x2C00) -#define SUNXI_TWI2_BASE (REGS_APB1_BASE + 0x3000) -#define SUNXI_TWI3_BASE (REGS_APB1_BASE + 0x3400) -#define SUNXI_TWI4_BASE (REGS_APB1_BASE + 0x3800) /* RCPUS Module */ #define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400) #define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400) -/* Misc. */ -#define SUNXI_BROM_BASE 0xFFFF0000 /* 32K */ -#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) - #ifndef __ASSEMBLY__ void sunxi_board_init(void); void sunxi_reset(void); From patchwork Wed Jan 3 00:12:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1881803 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T4VZq0n2Zz23d9 for ; Wed, 3 Jan 2024 11:14:27 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D4AE3879C3; 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Tue, 2 Jan 2024 16:14:21 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4AA833F5A1; Tue, 2 Jan 2024 16:13:34 -0800 (PST) From: Andre Przywara To: Jagan Teki Cc: Samuel Holland , linux-sunxi@lists.linux.dev, u-boot@lists.denx.de Subject: [PATCH 05/19] sunxi: move #ifdef guards around tzpc_init() to header file Date: Wed, 3 Jan 2024 00:12:25 +0000 Message-Id: <20240103001239.17482-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20240103001239.17482-1-andre.przywara@arm.com> References: <20240103001239.17482-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Some later 32-bit SoCs require some setup of the Secure Peripherals Controller, which is handled in tzpc_init(). At the moment this is guarded in board.c by some #ifdefs selecting the SoCs that need it. Move those #ifdef guards into the header file, providing an empty stub function for all other SoCs, so that the #ifdefs can be removed from the .c file, to improve readability. Signed-off-by: Andre Przywara --- arch/arm/include/asm/arch-sunxi/tzpc.h | 6 ++++++ arch/arm/mach-sunxi/board.c | 2 -- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/tzpc.h b/arch/arm/include/asm/arch-sunxi/tzpc.h index 7a6fcaebdb5..92696088a39 100644 --- a/arch/arm/include/asm/arch-sunxi/tzpc.h +++ b/arch/arm/include/asm/arch-sunxi/tzpc.h @@ -28,6 +28,12 @@ struct sunxi_tzpc { #define SUN8I_H3_TZPC_DECPORT1_ALL 0xff #define SUN8I_H3_TZPC_DECPORT2_ALL 0x7f +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3 void tzpc_init(void); +#else +static inline void tzpc_init(void) +{ +} +#endif #endif /* _SUNXI_TZPC_H */ diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 11a49418225..d998149e375 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -459,10 +459,8 @@ void board_init_f(ulong dummy) { sunxi_sram_init(); -#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3 /* Enable non-secure access to some peripherals */ tzpc_init(); -#endif clock_init(); timer_init(); From patchwork Wed Jan 3 00:12:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1881804 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T4Vb14J6zz23d9 for ; Wed, 3 Jan 2024 11:14:37 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5CDFC879D5; Wed, 3 Jan 2024 01:13:40 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 295FD879C5; Wed, 3 Jan 2024 01:13:39 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id C6A0087927 for ; Wed, 3 Jan 2024 01:13:36 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5EB6314BF; Tue, 2 Jan 2024 16:14:22 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 567493F5A1; Tue, 2 Jan 2024 16:13:35 -0800 (PST) From: Andre Przywara To: Jagan Teki Cc: Samuel Holland , linux-sunxi@lists.linux.dev, u-boot@lists.denx.de Subject: [PATCH 06/19] sunxi: remove common.h inclusion Date: Wed, 3 Jan 2024 00:12:26 +0000 Message-Id: <20240103001239.17482-7-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20240103001239.17482-1-andre.przywara@arm.com> References: <20240103001239.17482-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The usage of the common.h include file is deprecated, and has already been removed from several files. Get rid of all inclusions in the arch/arm/mach-sunxi directory. Most files actually don't need the header at all, for the few others just include the headers that we actually require. Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/board.c | 1 - arch/arm/mach-sunxi/clock.c | 1 - arch/arm/mach-sunxi/clock_sun4i.c | 1 - arch/arm/mach-sunxi/clock_sun50i_h6.c | 1 - arch/arm/mach-sunxi/clock_sun6i.c | 1 - arch/arm/mach-sunxi/clock_sun8i_a83t.c | 1 - arch/arm/mach-sunxi/clock_sun9i.c | 1 - arch/arm/mach-sunxi/cpu_info.c | 1 - arch/arm/mach-sunxi/dram_helpers.c | 3 ++- arch/arm/mach-sunxi/dram_sun4i.c | 1 - arch/arm/mach-sunxi/dram_sun50i_h6.c | 1 - arch/arm/mach-sunxi/dram_sun50i_h616.c | 1 - arch/arm/mach-sunxi/dram_sun6i.c | 1 - arch/arm/mach-sunxi/dram_sun8i_a23.c | 1 - arch/arm/mach-sunxi/dram_sun8i_a33.c | 1 - arch/arm/mach-sunxi/dram_sun8i_a83t.c | 1 - arch/arm/mach-sunxi/dram_sun9i.c | 1 - arch/arm/mach-sunxi/dram_suniv.c | 2 +- arch/arm/mach-sunxi/dram_sunxi_dw.c | 1 - arch/arm/mach-sunxi/gtbus_sun9i.c | 1 - arch/arm/mach-sunxi/pmic_bus.c | 1 - arch/arm/mach-sunxi/prcm.c | 1 - arch/arm/mach-sunxi/spl_spi_sunxi.c | 1 - arch/arm/mach-sunxi/timer.c | 1 - 24 files changed, 3 insertions(+), 24 deletions(-) diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index d998149e375..0140b07d32a 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -9,7 +9,6 @@ * Some init for sunxi platform. */ -#include #include #include #include diff --git a/arch/arm/mach-sunxi/clock.c b/arch/arm/mach-sunxi/clock.c index da3a0eb0584..b6c68c94f67 100644 --- a/arch/arm/mach-sunxi/clock.c +++ b/arch/arm/mach-sunxi/clock.c @@ -7,7 +7,6 @@ * (C) Copyright 2013 Luke Kenneth Casson Leighton */ -#include #include #include #include diff --git a/arch/arm/mach-sunxi/clock_sun4i.c b/arch/arm/mach-sunxi/clock_sun4i.c index 471609764d2..8f1d1b65f00 100644 --- a/arch/arm/mach-sunxi/clock_sun4i.c +++ b/arch/arm/mach-sunxi/clock_sun4i.c @@ -9,7 +9,6 @@ * (C) Copyright 2013 Luke Kenneth Casson Leighton */ -#include #include #include #include diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index bea91c78bc5..dac3663e1be 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -1,4 +1,3 @@ -#include #include #include #include diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index 6bd75a15f6d..aad9df282ec 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -9,7 +9,6 @@ * (C) Copyright 2013 Luke Kenneth Casson Leighton */ -#include #include #include #include diff --git a/arch/arm/mach-sunxi/clock_sun8i_a83t.c b/arch/arm/mach-sunxi/clock_sun8i_a83t.c index 31e4281529a..198fe9dbd73 100644 --- a/arch/arm/mach-sunxi/clock_sun8i_a83t.c +++ b/arch/arm/mach-sunxi/clock_sun8i_a83t.c @@ -9,7 +9,6 @@ * (C) Copyright 2015 Vishnu Patekar */ -#include #include #include #include diff --git a/arch/arm/mach-sunxi/clock_sun9i.c b/arch/arm/mach-sunxi/clock_sun9i.c index 8ba4802f3b3..edaff9a28ce 100644 --- a/arch/arm/mach-sunxi/clock_sun9i.c +++ b/arch/arm/mach-sunxi/clock_sun9i.c @@ -9,7 +9,6 @@ * Philipp Tomsich */ -#include #include #include #include diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c index 7fecc3b88dd..310dca06e57 100644 --- a/arch/arm/mach-sunxi/cpu_info.c +++ b/arch/arm/mach-sunxi/cpu_info.c @@ -5,7 +5,6 @@ * Tom Cubie */ -#include #include #include #include diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c index cdf2750f1c5..4a867df7af8 100644 --- a/arch/arm/mach-sunxi/dram_helpers.c +++ b/arch/arm/mach-sunxi/dram_helpers.c @@ -5,8 +5,9 @@ * (C) Copyright 2015 Hans de Goede */ -#include +#include #include +#include #include #include #include diff --git a/arch/arm/mach-sunxi/dram_sun4i.c b/arch/arm/mach-sunxi/dram_sun4i.c index 80a6c4bc0fd..2cce381c9df 100644 --- a/arch/arm/mach-sunxi/dram_sun4i.c +++ b/arch/arm/mach-sunxi/dram_sun4i.c @@ -20,7 +20,6 @@ * rather undocumented and full of magic. */ -#include #include #include #include diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c index bff2e42513c..e7e2e6a06ff 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c @@ -5,7 +5,6 @@ * (C) Copyright 2017 Icenowy Zheng * */ -#include #include #include #include diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index c5c1331a4c3..68c49e85f9d 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -12,7 +12,6 @@ * (C) Copyright 2020 Jernej Skrabec * */ -#include #include #include #include diff --git a/arch/arm/mach-sunxi/dram_sun6i.c b/arch/arm/mach-sunxi/dram_sun6i.c index 0590110d4ac..c023845908f 100644 --- a/arch/arm/mach-sunxi/dram_sun6i.c +++ b/arch/arm/mach-sunxi/dram_sun6i.c @@ -9,7 +9,6 @@ * * (C) Copyright 2014 Hans de Goede */ -#include #include #include #include diff --git a/arch/arm/mach-sunxi/dram_sun8i_a23.c b/arch/arm/mach-sunxi/dram_sun8i_a23.c index 056cb03efb1..1c3c6d8126e 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_a23.c +++ b/arch/arm/mach-sunxi/dram_sun8i_a23.c @@ -19,7 +19,6 @@ * This may be used as a (possible) reference for future work / cleanups. */ -#include #include #include #include diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c b/arch/arm/mach-sunxi/dram_sun8i_a33.c index 367b74061ed..0d08b6a424e 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_a33.c +++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c @@ -7,7 +7,6 @@ * (C) Copyright 2015 Vishnu Patekar * (C) Copyright 2015 Hans de Goede */ -#include #include #include #include diff --git a/arch/arm/mach-sunxi/dram_sun8i_a83t.c b/arch/arm/mach-sunxi/dram_sun8i_a83t.c index a3f833dd341..ef833321e37 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_a83t.c +++ b/arch/arm/mach-sunxi/dram_sun8i_a83t.c @@ -7,7 +7,6 @@ * (C) Copyright 2015 Vishnu Patekar * (C) Copyright 2015 Hans de Goede */ -#include #include #include #include diff --git a/arch/arm/mach-sunxi/dram_sun9i.c b/arch/arm/mach-sunxi/dram_sun9i.c index 14be212e891..002b6df39d5 100644 --- a/arch/arm/mach-sunxi/dram_sun9i.c +++ b/arch/arm/mach-sunxi/dram_sun9i.c @@ -10,7 +10,6 @@ * Philipp Tomsich */ -#include #include #include #include diff --git a/arch/arm/mach-sunxi/dram_suniv.c b/arch/arm/mach-sunxi/dram_suniv.c index 9e583e18553..640f872ad4c 100644 --- a/arch/arm/mach-sunxi/dram_suniv.c +++ b/arch/arm/mach-sunxi/dram_suniv.c @@ -9,7 +9,7 @@ * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com> */ -#include +#include #include #include #include diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index 9382d3d0be8..b4074f7d9b3 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -8,7 +8,6 @@ * (C) Copyright 2015 Hans de Goede * (C) Copyright 2015 Jens Kuske */ -#include #include #include #include diff --git a/arch/arm/mach-sunxi/gtbus_sun9i.c b/arch/arm/mach-sunxi/gtbus_sun9i.c index 5624621b500..a058fea6bef 100644 --- a/arch/arm/mach-sunxi/gtbus_sun9i.c +++ b/arch/arm/mach-sunxi/gtbus_sun9i.c @@ -6,7 +6,6 @@ * Philipp Tomsich */ -#include #include #include #include diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c index 8e7625fe057..87df312725c 100644 --- a/arch/arm/mach-sunxi/pmic_bus.c +++ b/arch/arm/mach-sunxi/pmic_bus.c @@ -9,7 +9,6 @@ */ #include -#include #include #include #include diff --git a/arch/arm/mach-sunxi/prcm.c b/arch/arm/mach-sunxi/prcm.c index 71a2e44918e..ef7c46eab3b 100644 --- a/arch/arm/mach-sunxi/prcm.c +++ b/arch/arm/mach-sunxi/prcm.c @@ -13,7 +13,6 @@ * Tom Cubie */ -#include #include #include #include diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index c2410dd7bb1..0a2714d2dd9 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Siarhei Siamashka */ -#include #include #include #include diff --git a/arch/arm/mach-sunxi/timer.c b/arch/arm/mach-sunxi/timer.c index 9a6f6c06d8c..1bbfad5e520 100644 --- a/arch/arm/mach-sunxi/timer.c +++ b/arch/arm/mach-sunxi/timer.c @@ -5,7 +5,6 @@ * Tom Cubie */ -#include #include #include #include From patchwork Wed Jan 3 00:12:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1881805 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T4VbF114lz23d9 for ; Wed, 3 Jan 2024 11:14:49 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E2BD98795C; Wed, 3 Jan 2024 01:13:41 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id B911F879AC; Wed, 3 Jan 2024 01:13:40 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id D00698785D for ; Wed, 3 Jan 2024 01:13:37 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 68666C15; Tue, 2 Jan 2024 16:14:23 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7E2143F5A1; Tue, 2 Jan 2024 16:13:36 -0800 (PST) From: Andre Przywara To: Jagan Teki Cc: Samuel Holland , linux-sunxi@lists.linux.dev, u-boot@lists.denx.de Subject: [PATCH 07/19] sunxi: simplify U-Boot proper only builds Date: Wed, 3 Jan 2024 00:12:27 +0000 Message-Id: <20240103001239.17482-8-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20240103001239.17482-1-andre.przywara@arm.com> References: <20240103001239.17482-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean At the moment every Allwinner board builds and requires an SPL, even though we select this individually in each _defconfig file. For experiments and for early bringup of new SoCs it would be beneficial to only build U-Boot proper, for instance to postpone a tedious SPL port (including DRAM support) in the initial phase. Protect some SPL related symbols that we unconditionally select at the moment with "if SPL", to avoid Kconfig conflicts when CONFIG_SPL is disabled. This alone does not cleanly build U-Boot proper only yet, but gets it far enough so that the binary can be harvested. Signed-off-by: Andre Przywara --- arch/arm/Kconfig | 4 ++-- arch/arm/mach-sunxi/Kconfig | 16 ++++++++-------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d812685c984..adce50c66a4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1143,14 +1143,14 @@ config ARCH_SUNXI select SPL_SEPARATE_BSS if SPL select SPL_STACK_R if SPL select SPL_SYS_MALLOC_SIMPLE if SPL - select SPL_SYS_THUMB_BUILD if !ARM64 + select SPL_SYS_THUMB_BUILD if SPL && !ARM64 select SUNXI_GPIO select SYS_NS16550 select SYS_THUMB_BUILD if !ARM64 select USB if DISTRO_DEFAULTS select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST - select SPL_USE_TINY_PRINTF + select SPL_USE_TINY_PRINTF if SPL select USE_PREBOOT select SYS_RELOC_GD_ENV_ADDR imply BOARD_LATE_INIT diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index a4a8d8e9445..421a48bc357 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -182,7 +182,7 @@ config SUNXI_GEN_SUN6I config SUN50I_GEN_H6 bool select FIT - select SPL_LOAD_FIT + select SPL_LOAD_FIT if SPL select MMC_SUNXI_HAS_NEW_MODE select SUPPORT_SPL ---help--- @@ -272,7 +272,7 @@ config MACH_SUN6I select ARCH_SUPPORT_PSCI select SPL_ARMV7_SET_CORTEX_SMPEN select DRAM_SUN6I - select SPL_I2C + select SPL_I2C if SPL select SUN6I_PRCM select SUNXI_GEN_SUN6I select SUPPORT_SPL @@ -300,7 +300,7 @@ config MACH_SUN8I_A23 select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI select DRAM_SUN8I_A23 - select SPL_I2C + select SPL_I2C if SPL select SUNXI_GEN_SUN6I select SUPPORT_SPL select SYS_I2C_SUN8I_RSB @@ -313,7 +313,7 @@ config MACH_SUN8I_A33 select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI select DRAM_SUN8I_A33 - select SPL_I2C + select SPL_I2C if SPL select SUNXI_GEN_SUN6I select SUPPORT_SPL select SYS_I2C_SUN8I_RSB @@ -323,7 +323,7 @@ config MACH_SUN8I_A83T bool "sun8i (Allwinner A83T)" select CPU_V7A select DRAM_SUN8I_A83T - select SPL_I2C + select SPL_I2C if SPL select SUNXI_GEN_SUN6I select MMC_SUNXI_HAS_NEW_MODE select MMC_SUNXI_HAS_MODE_SWITCH @@ -382,7 +382,7 @@ config MACH_SUN9I select CPU_V7A select SPL_ARMV7_SET_CORTEX_SMPEN select DRAM_SUN9I - select SPL_I2C + select SPL_I2C if SPL select SUN6I_PRCM select SUNXI_GEN_SUN6I select SUPPORT_SPL @@ -398,7 +398,7 @@ config MACH_SUN50I select SUNXI_DRAM_DW select SUNXI_DRAM_DW_32BIT select FIT - select SPL_LOAD_FIT + select SPL_LOAD_FIT if SPL select SUNXI_A64_TIMER_ERRATUM config MACH_SUN50I_H5 @@ -407,7 +407,7 @@ config MACH_SUN50I_H5 select MACH_SUNXI_H3_H5 select MMC_SUNXI_HAS_NEW_MODE select FIT - select SPL_LOAD_FIT + select SPL_LOAD_FIT if SPL config MACH_SUN50I_H6 bool "sun50i (Allwinner H6)" From patchwork Wed Jan 3 00:12:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1881806 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T4VbR3jGGz23d9 for ; Wed, 3 Jan 2024 11:14:58 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 61ED3879CB; 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Tue, 2 Jan 2024 16:14:24 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 89BF53F5A1; Tue, 2 Jan 2024 16:13:37 -0800 (PST) From: Andre Przywara To: Jagan Teki Cc: Samuel Holland , linux-sunxi@lists.linux.dev, u-boot@lists.denx.de Subject: [PATCH 08/19] sunxi: remove unneeded i2c_init_board() call for U-Boot proper Date: Wed, 3 Jan 2024 00:12:28 +0000 Message-Id: <20240103001239.17482-9-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20240103001239.17482-1-andre.przywara@arm.com> References: <20240103001239.17482-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The driver used for the Allwinner I2C IP is using proper DT and DM enablement for a while: we enable the clock gate and de-assert the reset line in the driver's probe() routine, and the pinmux setup is taken care of by the DM framework. This means the explicit call to the i2c_init_board() routine is not needed for U-Boot proper. As the board_init() function in board.c is only called for U-Boot proper, we can remove the call, something that the comment there hinted at already. Fix the comment for the board_init() function on the way: we were not really doing board specific setup there. The fact that this function is called from U-Boot proper only is probably more helpful for reasoning about this code. Signed-off-by: Andre Przywara --- board/sunxi/board.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 8c12c8deade..1313b01dcea 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -186,7 +186,7 @@ enum env_location env_get_location(enum env_operation op, int prio) return ENVL_UNKNOWN; } -/* add board specific code here */ +/* called only from U-Boot proper */ int board_init(void) { __maybe_unused int id_pfr1, ret; @@ -226,13 +226,6 @@ int board_init(void) if (ret) return ret; -#if CONFIG_IS_ENABLED(DM_I2C) - /* - * Temporary workaround for enabling I2C clocks until proper sunxi DM - * clk, reset and pinctrl drivers land. - */ - i2c_init_board(); -#endif eth_init_board(); return 0; From patchwork Wed Jan 3 00:12:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1881807 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T4Vbj1t0qz23d9 for ; Wed, 3 Jan 2024 11:15:11 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D5815879AC; Wed, 3 Jan 2024 01:13:45 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 47A3D879CC; Wed, 3 Jan 2024 01:13:44 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id ECCC5879D1 for ; Wed, 3 Jan 2024 01:13:39 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 80BDA152B; Tue, 2 Jan 2024 16:14:25 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 958403F5A1; Tue, 2 Jan 2024 16:13:38 -0800 (PST) From: Andre Przywara To: Jagan Teki Cc: Samuel Holland , linux-sunxi@lists.linux.dev, u-boot@lists.denx.de Subject: [PATCH 09/19] sunxi: compile clock.c for SPL only Date: Wed, 3 Jan 2024 00:12:29 +0000 Message-Id: <20240103001239.17482-10-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20240103001239.17482-1-andre.przywara@arm.com> References: <20240103001239.17482-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean With the clock_twi_onoff() function now being called only from the SPL, the whole clock.c file in arch/arm/mach-sunxi is needed by SPL code only. Remove the redundant #ifdef from the clock_init() function, actually this function was already only called from the SPL. Then adjust the Makefile to compile clock.c only with CONFIG_SPL_BUILD defined. This avoids unnecessary code in U-Boot proper and allows further refactoring and code-split between the SPL and U-Boot proper. Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/Makefile | 2 +- arch/arm/mach-sunxi/clock.c | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 1d4c70ec352..3f83c0280ef 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -7,7 +7,6 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. obj-y += board.o -obj-y += clock.o obj-y += cpu_info.o obj-y += dram_helpers.o obj-$(CONFIG_SUN6I_PRCM) += prcm.o @@ -31,6 +30,7 @@ obj-y += timer.o endif ifdef CONFIG_SPL_BUILD +obj-y += clock.o obj-$(CONFIG_MACH_SUNIV) += dram_suniv.o obj-$(CONFIG_DRAM_SUN4I) += dram_sun4i.o obj-$(CONFIG_DRAM_SUN6I) += dram_sun6i.o diff --git a/arch/arm/mach-sunxi/clock.c b/arch/arm/mach-sunxi/clock.c index b6c68c94f67..5e9fa0d0748 100644 --- a/arch/arm/mach-sunxi/clock.c +++ b/arch/arm/mach-sunxi/clock.c @@ -23,10 +23,8 @@ __weak void gtbus_init(void) int clock_init(void) { -#ifdef CONFIG_SPL_BUILD clock_init_safe(); gtbus_init(); -#endif clock_init_uart(); clock_init_sec(); From patchwork Wed Jan 3 00:12:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1881808 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T4Vbt3g1sz23d9 for ; Wed, 3 Jan 2024 11:15:22 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4C071879D2; Wed, 3 Jan 2024 01:13:46 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 7F8D887927; Wed, 3 Jan 2024 01:13:44 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id EAD8F878D3 for ; Wed, 3 Jan 2024 01:13:40 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8B36FC15; Tue, 2 Jan 2024 16:14:26 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A0EF93F5A1; Tue, 2 Jan 2024 16:13:39 -0800 (PST) From: Andre Przywara To: Jagan Teki Cc: Samuel Holland , linux-sunxi@lists.linux.dev, u-boot@lists.denx.de Subject: [PATCH 10/19] sunxi: sun4i: make more clock functions SPL only Date: Wed, 3 Jan 2024 00:12:30 +0000 Message-Id: <20240103001239.17482-11-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20240103001239.17482-1-andre.przywara@arm.com> References: <20240103001239.17482-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean In clock_sun4i.c, responsible for (mostly early) clock setup on early generation Allwinner SoCs, many functions are only needed by the SPL, and are thus already guarded by CONFIG_SPL_BUILD. Over the years drivers like for the UART or I2C were converted to DM, so they care about clock setup themselves now, by using a proper DM clock driver. This means those devices need the clock setup functions here for the SPL only. Include those functions into the existing CONFIG_SPL_BUILD guards, so they are compiled for the SPL only. This avoids unnecessary code in U-Boot proper and helps further refactoring. Add some comments on the way to help understanding of the file. Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/clock_sun4i.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-sunxi/clock_sun4i.c b/arch/arm/mach-sunxi/clock_sun4i.c index 8f1d1b65f00..eead5a924f4 100644 --- a/arch/arm/mach-sunxi/clock_sun4i.c +++ b/arch/arm/mach-sunxi/clock_sun4i.c @@ -41,7 +41,6 @@ void clock_init_safe(void) setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT); #endif } -#endif void clock_init_uart(void) { @@ -75,7 +74,6 @@ int clock_twi_onoff(int port, int state) return 0; } -#ifdef CONFIG_SPL_BUILD #define PLL1_CFG(N, K, M, P) ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \ 0 << CCM_PLL1_CFG_VCO_RST_SHIFT | \ 8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \ @@ -175,8 +173,9 @@ void clock_set_pll1(unsigned int hz) &ccm->cpu_ahb_apb0_cfg); sdelay(20); } -#endif +#endif /* CONFIG_SPL_BUILD */ +/* video, DRAM, PLL_PERIPH clocks */ void clock_set_pll3(unsigned int clk) { struct sunxi_ccm_reg * const ccm = From patchwork Wed Jan 3 00:12:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1881809 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T4Vc46yhdz20Rq for ; Wed, 3 Jan 2024 11:15:32 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id AC736879DC; Wed, 3 Jan 2024 01:13:46 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 1A45C878D3; Wed, 3 Jan 2024 01:13:45 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 063BC879BD for ; Wed, 3 Jan 2024 01:13:42 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 96A00152B; Tue, 2 Jan 2024 16:14:27 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AC5A13F5A1; Tue, 2 Jan 2024 16:13:40 -0800 (PST) From: Andre Przywara To: Jagan Teki Cc: Samuel Holland , linux-sunxi@lists.linux.dev, u-boot@lists.denx.de Subject: [PATCH 11/19] sunxi: sun6i: make more clock functions SPL only Date: Wed, 3 Jan 2024 00:12:31 +0000 Message-Id: <20240103001239.17482-12-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20240103001239.17482-1-andre.przywara@arm.com> References: <20240103001239.17482-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean In clock_sun6i.c, responsible for (mostly early) clock setup on older generation Allwinner SoCs, many functions are only needed by the SPL, and are thus already guarded by CONFIG_SPL_BUILD. Over the years drivers like for the UART or I2C were converted to DM, so they care about clock setup themselves now, by using a proper DM clock driver. This means those devices need the clock setup functions here for the SPL only. Include those functions into the existing CONFIG_SPL_BUILD guards, so they are compiled for the SPL only. This avoids unnecessary code in U-Boot proper and helps further refactoring. Add some comments on the way to help understanding of the file. Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/clock_sun6i.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index aad9df282ec..59f7e15ffe8 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -62,7 +62,6 @@ void clock_init_safe(void) setbits_le32(&ccm->sata_clk_cfg, CCM_SATA_CTRL_ENABLE); #endif } -#endif /* CONFIG_SPL_BUILD */ void clock_init_sec(void) { @@ -124,7 +123,6 @@ void clock_init_uart(void) #endif } -#ifdef CONFIG_SPL_BUILD void clock_set_pll1(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -173,6 +171,7 @@ void clock_set_pll1(unsigned int clk) } #endif /* CONFIG_SPL_BUILD */ +/* video, DRAM, PLL_PERIPH clocks */ void clock_set_pll3(unsigned int clk) { struct sunxi_ccm_reg * const ccm = From patchwork Wed Jan 3 00:12:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1881810 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T4VcH4X5gz20Rq for ; Wed, 3 Jan 2024 11:15:42 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 326AB8747A; Wed, 3 Jan 2024 01:13:47 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 8E53387950; Wed, 3 Jan 2024 01:13:45 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 52DF9879D2 for ; Wed, 3 Jan 2024 01:13:43 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A222BC15; Tue, 2 Jan 2024 16:14:28 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B7A753F5A1; Tue, 2 Jan 2024 16:13:41 -0800 (PST) From: Andre Przywara To: Jagan Teki Cc: Samuel Holland , linux-sunxi@lists.linux.dev, u-boot@lists.denx.de Subject: [PATCH 12/19] sunxi: sun50i_h6: make more clock functions SPL only Date: Wed, 3 Jan 2024 00:12:32 +0000 Message-Id: <20240103001239.17482-13-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20240103001239.17482-1-andre.przywara@arm.com> References: <20240103001239.17482-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean In clock_sun50i_h6.c, responsible for (mostly early) clock setup on newer generation Allwinner SoCs, many functions are only needed by the SPL, and are thus already guarded by CONFIG_SPL_BUILD. Over the years drivers like for the UART or I2C were converted to DM, so they care about clock setup themselves now, by using a proper DM clock driver. This means those devices need the clock setup functions here for the SPL only. Include those functions into the existing CONFIG_SPL_BUILD guards, so they are compiled for the SPL only. By moving the clock_get_pll6() function to the end of the file, all SPL-only clocks can be contained within one #ifdef guard. This avoids unnecessary code in U-Boot proper and helps further refactoring. Add some comments on the way to help understanding of the file. Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/clock_sun50i_h6.c | 57 +++++++++++++-------------- 1 file changed, 28 insertions(+), 29 deletions(-) diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index dac3663e1be..cc2ee336416 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -51,7 +51,6 @@ void clock_init_safe(void) */ writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg); } -#endif void clock_init_uart(void) { @@ -73,7 +72,6 @@ void clock_init_uart(void) 1 << (RESET_SHIFT + CONFIG_CONS_INDEX - 1)); } -#ifdef CONFIG_SPL_BUILD void clock_set_pll1(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -105,33 +103,6 @@ void clock_set_pll1(unsigned int clk) val |= CCM_CPU_AXI_MUX_PLL_CPUX; writel(val, &ccm->cpu_axi_cfg); } -#endif - -unsigned int clock_get_pll6(void) -{ - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - uint32_t rval = readl(&ccm->pll6_cfg); - int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; - int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> - CCM_PLL6_CTRL_DIV2_SHIFT) + 1; - int div1, m; - - if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) { - div1 = ((rval & CCM_PLL6_CTRL_P0_MASK) >> - CCM_PLL6_CTRL_P0_SHIFT) + 1; - m = 1; - } else { - div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> - CCM_PLL6_CTRL_DIV1_SHIFT) + 1; - if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) - m = 4; - else - m = 2; - } - - return 24000000U * n / m / div1 / div2; -} int clock_twi_onoff(int port, int state) { @@ -160,3 +131,31 @@ int clock_twi_onoff(int port, int state) return 0; } +#endif /* CONFIG_SPL_BUILD */ + +/* PLL_PERIPH0 clock, used by the MMC driver */ +unsigned int clock_get_pll6(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll6_cfg); + int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; + int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> + CCM_PLL6_CTRL_DIV2_SHIFT) + 1; + int div1, m; + + if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) { + div1 = ((rval & CCM_PLL6_CTRL_P0_MASK) >> + CCM_PLL6_CTRL_P0_SHIFT) + 1; + m = 1; + } else { + div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> + CCM_PLL6_CTRL_DIV1_SHIFT) + 1; + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + m = 4; + else + m = 2; + } + + return 24000000U * n / m / div1 / div2; +} From patchwork Wed Jan 3 00:12:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1881811 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T4VcS1rjFz20Rq for ; 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spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id ADC931516; Tue, 2 Jan 2024 16:14:29 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C31683F5A1; Tue, 2 Jan 2024 16:13:42 -0800 (PST) From: Andre Przywara To: Jagan Teki Cc: Samuel Holland , linux-sunxi@lists.linux.dev, u-boot@lists.denx.de Subject: [PATCH 13/19] sunxi: sun8i_a83t: make more clock functions SPL only Date: Wed, 3 Jan 2024 00:12:33 +0000 Message-Id: <20240103001239.17482-14-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20240103001239.17482-1-andre.przywara@arm.com> References: <20240103001239.17482-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean In clock_sun8i_a83t.c, responsible for (mostly early) clock setup on the Allwinner A83T SoC, many functions are only needed by the SPL, and are thus already guarded by CONFIG_SPL_BUILD. Over the years drivers like for the UART or I2C were converted to DM, so they care about clock setup themselves now, by using a proper DM clock driver. This means those devices need the clock setup functions here for the SPL only. Include those functions into the existing CONFIG_SPL_BUILD guards, so they are compiled for the SPL only. This avoids unnecessary code in U-Boot proper and helps further refactoring. Add some comments on the way to help understanding of the file. Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/clock_sun8i_a83t.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-sunxi/clock_sun8i_a83t.c b/arch/arm/mach-sunxi/clock_sun8i_a83t.c index 198fe9dbd73..9eeba084f95 100644 --- a/arch/arm/mach-sunxi/clock_sun8i_a83t.c +++ b/arch/arm/mach-sunxi/clock_sun8i_a83t.c @@ -46,7 +46,6 @@ void clock_init_safe(void) /* timestamp */ writel(1, 0x01720000); } -#endif void clock_init_uart(void) { @@ -70,7 +69,6 @@ void clock_init_uart(void) CONFIG_CONS_INDEX - 1)); } -#ifdef CONFIG_SPL_BUILD void clock_set_pll1(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -102,8 +100,9 @@ void clock_set_pll1(unsigned int clk) CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT, &ccm->cpu_axi_cfg); } -#endif +#endif /* CONFIG_SPL_BUILD */ +/* DRAM and PLL_PERIPH0 clock (used by the MMC driver) */ void clock_set_pll5(unsigned int clk) { struct sunxi_ccm_reg * const ccm = From patchwork Wed Jan 3 00:12:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1881812 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T4Vcd5zNYz20Rq for ; Wed, 3 Jan 2024 11:16:01 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1EB52879EF; Wed, 3 Jan 2024 01:13:49 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 4D8CA879E1; Wed, 3 Jan 2024 01:13:47 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 255E487927 for ; Wed, 3 Jan 2024 01:13:45 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B9499C15; Tue, 2 Jan 2024 16:14:30 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CEFBC3F5A1; Tue, 2 Jan 2024 16:13:43 -0800 (PST) From: Andre Przywara To: Jagan Teki Cc: Samuel Holland , linux-sunxi@lists.linux.dev, u-boot@lists.denx.de Subject: [PATCH 14/19] sunxi: sun9i: make more clock functions SPL only Date: Wed, 3 Jan 2024 00:12:34 +0000 Message-Id: <20240103001239.17482-15-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20240103001239.17482-1-andre.przywara@arm.com> References: <20240103001239.17482-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean In clock_sun9i.c, responsible for (mostly early) clock setup on the Allwinner A80 SoC, many functions are only needed by the SPL, and are thus already guarded by CONFIG_SPL_BUILD. Over the years drivers like for the UART or I2C were converted to DM, and they care about clock setup themselves now, by using a proper DM clock driver. This means those devices need the clock setup functions here for the SPL only. Move some functions around, to group all SPL-only function within one #ifdef guard. Some functions were exported, but never used outside of this file, so remove their prototypes from the header file and mark them as static. This avoids unnecessary code in U-Boot proper and helps further refactoring. Add some comments on the way to help understanding of the file. Signed-off-by: Andre Przywara --- arch/arm/include/asm/arch-sunxi/clock_sun9i.h | 3 - arch/arm/mach-sunxi/clock_sun9i.c | 97 +++++++++---------- 2 files changed, 48 insertions(+), 52 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h index fe6b8ba2732..0264bfe1c50 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h @@ -220,10 +220,7 @@ struct sunxi_ccm_reg { #ifndef __ASSEMBLY__ void clock_set_pll1(unsigned int clk); -void clock_set_pll2(unsigned int clk); -void clock_set_pll4(unsigned int clk); void clock_set_pll6(unsigned int clk); -void clock_set_pll12(unsigned int clk); unsigned int clock_get_pll4_periph0(void); #endif diff --git a/arch/arm/mach-sunxi/clock_sun9i.c b/arch/arm/mach-sunxi/clock_sun9i.c index edaff9a28ce..5913e40cb65 100644 --- a/arch/arm/mach-sunxi/clock_sun9i.c +++ b/arch/arm/mach-sunxi/clock_sun9i.c @@ -17,6 +17,52 @@ #ifdef CONFIG_SPL_BUILD +static void clock_set_pll2(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int p = 0; + + /* Switch cluster 1 to 24MHz clock while changing PLL2 */ + clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK, + C1_CPUX_CLK_SRC_OSC24M); + + writel(CCM_PLL2_CTRL_EN | CCM_PLL2_CTRL_P(p) | + CCM_PLL2_CLOCK_TIME_2 | CCM_PLL2_CTRL_N(clk / 24000000), + &ccm->pll2_c1_cfg); + + sdelay(2000); + + /* Switch cluster 1 back to PLL2 */ + clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK, + C1_CPUX_CLK_SRC_PLL2); +} + +static void clock_set_pll4(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + writel(CCM_PLL4_CTRL_EN | CCM_PLL4_CTRL_N(clk / 24000000), + &ccm->pll4_periph0_cfg); + + sdelay(2000); +} + +static void clock_set_pll12(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (readl(&ccm->pll12_periph1_cfg) & CCM_PLL12_CTRL_EN) + return; + + writel(CCM_PLL12_CTRL_EN | CCM_PLL12_CTRL_N(clk / 24000000), + &ccm->pll12_periph1_cfg); + + sdelay(2000); +} + void clock_init_safe(void) { struct sunxi_ccm_reg * const ccm = @@ -63,7 +109,6 @@ void clock_init_safe(void) /* set enable-bit in TSTAMP_CTRL_REG */ writel(1, 0x01720000); } -#endif void clock_init_uart(void) { @@ -80,7 +125,6 @@ void clock_init_uart(void) CONFIG_CONS_INDEX - 1)); } -#ifdef CONFIG_SPL_BUILD void clock_set_pll1(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -108,27 +152,6 @@ void clock_set_pll1(unsigned int clk) C0_CPUX_CLK_SRC_PLL1); } -void clock_set_pll2(unsigned int clk) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - const int p = 0; - - /* Switch cluster 1 to 24MHz clock while changing PLL2 */ - clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK, - C1_CPUX_CLK_SRC_OSC24M); - - writel(CCM_PLL2_CTRL_EN | CCM_PLL2_CTRL_P(p) | - CCM_PLL2_CLOCK_TIME_2 | CCM_PLL2_CTRL_N(clk / 24000000), - &ccm->pll2_c1_cfg); - - sdelay(2000); - - /* Switch cluster 1 back to PLL2 */ - clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK, - C1_CPUX_CLK_SRC_PLL2); -} - void clock_set_pll6(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -143,32 +166,6 @@ void clock_set_pll6(unsigned int clk) sdelay(2000); } -void clock_set_pll12(unsigned int clk) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - if (readl(&ccm->pll12_periph1_cfg) & CCM_PLL12_CTRL_EN) - return; - - writel(CCM_PLL12_CTRL_EN | CCM_PLL12_CTRL_N(clk / 24000000), - &ccm->pll12_periph1_cfg); - - sdelay(2000); -} - - -void clock_set_pll4(unsigned int clk) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - writel(CCM_PLL4_CTRL_EN | CCM_PLL4_CTRL_N(clk / 24000000), - &ccm->pll4_periph0_cfg); - - sdelay(2000); -} -#endif int clock_twi_onoff(int port, int state) { @@ -193,7 +190,9 @@ int clock_twi_onoff(int port, int state) return 0; } +#endif /* CONFIG_SPL_BUILD */ +/* PLL_PERIPH0 clock (used by the MMC driver) */ unsigned int clock_get_pll4_periph0(void) { struct sunxi_ccm_reg *const ccm = From patchwork Wed Jan 3 00:12:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1881813 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T4Vcs3Hztz20Rq for ; Wed, 3 Jan 2024 11:16:13 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8DE33879C5; Wed, 3 Jan 2024 01:13:51 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 33EF4879ED; Wed, 3 Jan 2024 01:13:49 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 4B94A879D1 for ; Wed, 3 Jan 2024 01:13:46 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E132C14BF; Tue, 2 Jan 2024 16:14:31 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DA8953F5A1; Tue, 2 Jan 2024 16:13:44 -0800 (PST) From: Andre Przywara To: Jagan Teki Cc: Samuel Holland , linux-sunxi@lists.linux.dev, u-boot@lists.denx.de Subject: [PATCH 15/19] sunxi: move pinmux setup into separate SPL only file Date: Wed, 3 Jan 2024 00:12:35 +0000 Message-Id: <20240103001239.17482-16-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20240103001239.17482-1-andre.przywara@arm.com> References: <20240103001239.17482-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean At the moment the board/sunxi/board.c file contains a number of pinmux setup functions, that are only called by the SPL, to program the configured pins for the UART, NAND or eMMC devices. Move those functions into a separate file, to help keeping the board.c file clean, and allow compiling this new file for the SPL only. To help review, this file is as much copy&paste as possible. This raises some checkpatch complaints, but this will be fixed and further cleanup will be provided in a subsequent patch. Right now we just add some comments to some #endif's to mark nested regions. It also removes a now redundant CONFIG_SPL_BUILD guard, and fixes a whitespace problem for the R528 eMMC setup. The new file is placed in arch/arm/mach-sunxi, as the plan is to keep all (legacy) SPL code in there. Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/Makefile | 1 + arch/arm/mach-sunxi/spl_pinmux.c | 326 +++++++++++++++++++++++++++++++ board/sunxi/board.c | 309 +---------------------------- 3 files changed, 328 insertions(+), 308 deletions(-) create mode 100644 arch/arm/mach-sunxi/spl_pinmux.c diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 3f83c0280ef..c15ef01aaad 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -31,6 +31,7 @@ endif ifdef CONFIG_SPL_BUILD obj-y += clock.o +obj-y += spl_pinmux.o obj-$(CONFIG_MACH_SUNIV) += dram_suniv.o obj-$(CONFIG_DRAM_SUN4I) += dram_sun4i.o obj-$(CONFIG_DRAM_SUN6I) += dram_sun6i.o diff --git a/arch/arm/mach-sunxi/spl_pinmux.c b/arch/arm/mach-sunxi/spl_pinmux.c new file mode 100644 index 00000000000..45cc2cfe2b1 --- /dev/null +++ b/arch/arm/mach-sunxi/spl_pinmux.c @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2023 Arm Ltd. + * (C) Copyright 2012-2013 Henrik Nordstrom + * (C) Copyright 2013 Luke Kenneth Casson Leighton + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * Code to setup pinmux configuration in the SPL, which lacks the DT to + * look this up properly. + */ + +#include +#include +#include +#include +#include + +void i2c_init_board(void) +{ +#ifdef CONFIG_I2C0_ENABLE +#if defined(CONFIG_MACH_SUN4I) || \ + defined(CONFIG_MACH_SUN5I) || \ + defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); + clock_twi_onoff(0, 1); +#elif defined(CONFIG_MACH_SUN6I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); + clock_twi_onoff(0, 1); +#elif defined(CONFIG_MACH_SUN8I_V3S) + sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0); + clock_twi_onoff(0, 1); +#elif defined(CONFIG_MACH_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); + clock_twi_onoff(0, 1); +#elif defined(CONFIG_MACH_SUN50I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0); + clock_twi_onoff(0, 1); +#endif +#endif /* CONFIG_I2C0_ENABLE */ + +#ifdef CONFIG_I2C1_ENABLE +#if defined(CONFIG_MACH_SUN4I) || \ + defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); + clock_twi_onoff(1, 1); +#elif defined(CONFIG_MACH_SUN5I) + sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); + clock_twi_onoff(1, 1); +#elif defined(CONFIG_MACH_SUN6I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); + clock_twi_onoff(1, 1); +#elif defined(CONFIG_MACH_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); + clock_twi_onoff(1, 1); +#elif defined(CONFIG_MACH_SUN50I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1); + clock_twi_onoff(1, 1); +#endif +#endif /* CONFIG_I2C1_ENABLE */ + +#ifdef CONFIG_R_I2C_ENABLE +#ifdef CONFIG_MACH_SUN50I + clock_twi_onoff(5, 1); + sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI); + sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI); +#elif defined(CONFIG_MACH_SUN50I_H616) + clock_twi_onoff(5, 1); + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI); +#else + clock_twi_onoff(5, 1); + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); +#endif +#endif /* CONFIG_R_I2C_ENABLE */ +} + +#if defined(CONFIG_NAND_SUNXI) +static void nand_pinmux_setup(void) +{ + unsigned int pin; + + for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); + +#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I + for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); +#endif + /* sun4i / sun7i do have a PC23, but it is not used for nand, + * only sun7i has a PC24 */ +#ifdef CONFIG_MACH_SUN7I + sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); +#endif +} + +static void nand_clock_setup(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \ + defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I + setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0)); +#endif + setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); +} + +void board_nand_init(void) +{ + nand_pinmux_setup(); + nand_clock_setup(); +} +#endif /* CONFIG_NAND_SUNXI */ + +#ifdef CONFIG_MMC +static void mmc_pinmux_setup(int sdc) +{ + unsigned int pin; + + switch (sdc) { + case 0: + /* SDC0: PF0-PF5 */ + for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + break; + + case 1: +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + if (IS_ENABLED(CONFIG_MMC1_PINS_PH)) { + /* SDC1: PH22-PH-27 */ + for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + } else { + /* SDC1: PG0-PG5 */ + for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + } +#elif defined(CONFIG_MACH_SUN5I) + /* SDC1: PG3-PG8 */ + for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } +#elif defined(CONFIG_MACH_SUN6I) + /* SDC1: PG0-PG5 */ + for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } +#elif defined(CONFIG_MACH_SUN8I) + /* SDC1: PG0-PG5 */ + for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } +#endif + break; + + case 2: +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) + /* SDC2: PC6-PC11 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } +#elif defined(CONFIG_MACH_SUN5I) + /* SDC2: PC6-PC15 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } +#elif defined(CONFIG_MACH_SUN6I) + /* SDC2: PC6-PC15, PC24 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + + sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(SUNXI_GPC(24), 2); +#elif defined(CONFIG_MACH_SUN8I_R40) + /* SDC2: PC6-PC15, PC24 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + + sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(SUNXI_GPC(24), 2); +#elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I) + /* SDC2: PC5-PC6, PC8-PC16 */ + for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + + for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } +#elif defined(CONFIG_MACH_SUN50I_H6) + /* SDC2: PC4-PC14 */ + for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } +#elif defined(CONFIG_MACH_SUN50I_H616) + /* SDC2: PC0-PC1, PC5-PC6, PC8-PC11, PC13-PC16 */ + for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(16); pin++) { + if (pin > SUNXI_GPC(1) && pin < SUNXI_GPC(5)) + continue; + if (pin == SUNXI_GPC(7) || pin == SUNXI_GPC(12)) + continue; + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 3); + } +#elif defined(CONFIG_MACH_SUN9I) + /* SDC2: PC6-PC16 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } +#elif defined(CONFIG_MACH_SUN8I_R528) + /* SDC2: PC2-PC7 */ + for (pin = SUNXI_GPC(2); pin <= SUNXI_GPC(7); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } +#else + puts("ERROR: No pinmux setup defined for MMC2!\n"); +#endif + break; + + case 3: +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + /* SDC3: PI4-PI9 */ + for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } +#elif defined(CONFIG_MACH_SUN6I) + /* SDC3: PC6-PC15, PC24 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + + sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); + sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(SUNXI_GPC(24), 2); +#endif + break; + + default: + printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); + break; + } +} + +int board_mmc_init(struct bd_info *bis) +{ + /* + * The BROM always accesses MMC port 0 (typically an SD card), and + * most boards seem to have such a slot. The others haven't reported + * any problem with unconditionally enabling this in the SPL. + */ + if (!IS_ENABLED(CONFIG_UART0_PORT_F)) { + mmc_pinmux_setup(0); + if (!sunxi_mmc_init(0)) + return -1; + } + + if (CONFIG_MMC_SUNXI_SLOT_EXTRA != -1) { + mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); + if (!sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA)) + return -1; + } + + return 0; +} + +#endif /* CONFIG_MMC */ diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 1313b01dcea..5f80c097a15 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -54,78 +54,6 @@ DECLARE_GLOBAL_DATA_PTR; -void i2c_init_board(void) -{ -#ifdef CONFIG_I2C0_ENABLE -#if defined(CONFIG_MACH_SUN4I) || \ - defined(CONFIG_MACH_SUN5I) || \ - defined(CONFIG_MACH_SUN7I) || \ - defined(CONFIG_MACH_SUN8I_R40) - sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); - sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); - clock_twi_onoff(0, 1); -#elif defined(CONFIG_MACH_SUN6I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); - sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); - clock_twi_onoff(0, 1); -#elif defined(CONFIG_MACH_SUN8I_V3S) - sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0); - sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0); - clock_twi_onoff(0, 1); -#elif defined(CONFIG_MACH_SUN8I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); - sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); - clock_twi_onoff(0, 1); -#elif defined(CONFIG_MACH_SUN50I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0); - sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0); - clock_twi_onoff(0, 1); -#endif -#endif - -#ifdef CONFIG_I2C1_ENABLE -#if defined(CONFIG_MACH_SUN4I) || \ - defined(CONFIG_MACH_SUN7I) || \ - defined(CONFIG_MACH_SUN8I_R40) - sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); - sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); - clock_twi_onoff(1, 1); -#elif defined(CONFIG_MACH_SUN5I) - sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); - sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); - clock_twi_onoff(1, 1); -#elif defined(CONFIG_MACH_SUN6I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); - sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); - clock_twi_onoff(1, 1); -#elif defined(CONFIG_MACH_SUN8I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); - sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); - clock_twi_onoff(1, 1); -#elif defined(CONFIG_MACH_SUN50I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1); - sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1); - clock_twi_onoff(1, 1); -#endif -#endif - -#ifdef CONFIG_R_I2C_ENABLE -#ifdef CONFIG_MACH_SUN50I - clock_twi_onoff(5, 1); - sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI); - sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI); -#elif CONFIG_MACH_SUN50I_H616 - clock_twi_onoff(5, 1); - sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI); - sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI); -#else - clock_twi_onoff(5, 1); - sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); - sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); -#endif -#endif -} - /* * Try to use the environment from the boot source first. * For MMC, this means a FAT partition on the boot device (SD or eMMC). @@ -282,241 +210,7 @@ int dram_init(void) return 0; } -#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD) -static void nand_pinmux_setup(void) -{ - unsigned int pin; - - for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); - -#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I - for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); -#endif - /* sun4i / sun7i do have a PC23, but it is not used for nand, - * only sun7i has a PC24 */ -#ifdef CONFIG_MACH_SUN7I - sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); -#endif -} - -static void nand_clock_setup(void) -{ - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); -#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \ - defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I - setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0)); -#endif - setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); -} - -void board_nand_init(void) -{ - nand_pinmux_setup(); - nand_clock_setup(); -} -#endif /* CONFIG_NAND_SUNXI */ - -#ifdef CONFIG_MMC -static void mmc_pinmux_setup(int sdc) -{ - unsigned int pin; - - switch (sdc) { - case 0: - /* SDC0: PF0-PF5 */ - for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } - break; - - case 1: -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ - defined(CONFIG_MACH_SUN8I_R40) - if (IS_ENABLED(CONFIG_MMC1_PINS_PH)) { - /* SDC1: PH22-PH-27 */ - for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { - sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } - } else { - /* SDC1: PG0-PG5 */ - for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { - sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } - } -#elif defined(CONFIG_MACH_SUN5I) - /* SDC1: PG3-PG8 */ - for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { - sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } -#elif defined(CONFIG_MACH_SUN6I) - /* SDC1: PG0-PG5 */ - for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { - sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } -#elif defined(CONFIG_MACH_SUN8I) - /* SDC1: PG0-PG5 */ - for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { - sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } -#endif - break; - - case 2: -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) - /* SDC2: PC6-PC11 */ - for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } -#elif defined(CONFIG_MACH_SUN5I) - /* SDC2: PC6-PC15 */ - for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } -#elif defined(CONFIG_MACH_SUN6I) - /* SDC2: PC6-PC15, PC24 */ - for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } - - sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(SUNXI_GPC(24), 2); -#elif defined(CONFIG_MACH_SUN8I_R40) - /* SDC2: PC6-PC15, PC24 */ - for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } - - sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(SUNXI_GPC(24), 2); -#elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I) - /* SDC2: PC5-PC6, PC8-PC16 */ - for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } - - for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } -#elif defined(CONFIG_MACH_SUN50I_H6) - /* SDC2: PC4-PC14 */ - for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } -#elif defined(CONFIG_MACH_SUN50I_H616) - /* SDC2: PC0-PC1, PC5-PC6, PC8-PC11, PC13-PC16 */ - for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(16); pin++) { - if (pin > SUNXI_GPC(1) && pin < SUNXI_GPC(5)) - continue; - if (pin == SUNXI_GPC(7) || pin == SUNXI_GPC(12)) - continue; - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 3); - } -#elif defined(CONFIG_MACH_SUN9I) - /* SDC2: PC6-PC16 */ - for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } -#elif defined(CONFIG_MACH_SUN8I_R528) - /* SDC2: PC2-PC7 */ - for (pin = SUNXI_GPC(2); pin <= SUNXI_GPC(7); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } -#else - puts("ERROR: No pinmux setup defined for MMC2!\n"); -#endif - break; - - case 3: -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ - defined(CONFIG_MACH_SUN8I_R40) - /* SDC3: PI4-PI9 */ - for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } -#elif defined(CONFIG_MACH_SUN6I) - /* SDC3: PC6-PC15, PC24 */ - for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { - sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } - - sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); - sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(SUNXI_GPC(24), 2); -#endif - break; - - default: - printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); - break; - } -} - -int board_mmc_init(struct bd_info *bis) -{ - /* - * The BROM always accesses MMC port 0 (typically an SD card), and - * most boards seem to have such a slot. The others haven't reported - * any problem with unconditionally enabling this in the SPL. - */ - if (!IS_ENABLED(CONFIG_UART0_PORT_F)) { - mmc_pinmux_setup(0); - if (!sunxi_mmc_init(0)) - return -1; - } - - if (CONFIG_MMC_SUNXI_SLOT_EXTRA != -1) { - mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); - if (!sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA)) - return -1; - } - - return 0; -} - -#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 +#if defined(CONFIG_MMC) && CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 int mmc_get_env_dev(void) { switch (sunxi_get_boot_device()) { @@ -528,7 +222,6 @@ int mmc_get_env_dev(void) return CONFIG_SYS_MMC_ENV_DEV; } } -#endif #endif /* CONFIG_MMC */ #ifdef CONFIG_SPL_BUILD From patchwork Wed Jan 3 00:12:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1881814 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T4Vd45DJDz20Rq for ; Wed, 3 Jan 2024 11:16:24 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 08131879F3; Wed, 3 Jan 2024 01:13:52 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id D396F879E4; Wed, 3 Jan 2024 01:13:49 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 56B5587927 for ; Wed, 3 Jan 2024 01:13:47 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EC920C15; Tue, 2 Jan 2024 16:14:32 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0E30E3F5A1; Tue, 2 Jan 2024 16:13:45 -0800 (PST) From: Andre Przywara To: Jagan Teki Cc: Samuel Holland , linux-sunxi@lists.linux.dev, u-boot@lists.denx.de Subject: [PATCH 16/19] sunxi: SPL pinmux: rewrite without #ifdefs Date: Wed, 3 Jan 2024 00:12:36 +0000 Message-Id: <20240103001239.17482-17-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20240103001239.17482-1-andre.przywara@arm.com> References: <20240103001239.17482-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean At the moment the SPL functions setting up the required pinmux for the UART, NAND and MMC controllers make heavy use of #ifdefs, which are sometimes even nested. This makes them hard to read, and more importantly hard to extend. Rewrite those functions with the help of IS_ENABLED(), to use proper C "if" statements. For the I2C case, also split the function up into one per I2C controller, to further simplify the code layout. The MMC function gets further simplified, by replacing the repeated direct calls to the GPIO functions with using variables, that describe a range of pins to handle, including skipped pins and outliers. The actual pinmux functions are then called from one place. One part of the NAND clock setup relies on SoC specific struct members, so that has to keep using #ifdefs, to avoid breaking compilation for other SoCs. Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/spl_pinmux.c | 434 +++++++++++++++---------------- 1 file changed, 210 insertions(+), 224 deletions(-) diff --git a/arch/arm/mach-sunxi/spl_pinmux.c b/arch/arm/mach-sunxi/spl_pinmux.c index 45cc2cfe2b1..18f8cd93b6a 100644 --- a/arch/arm/mach-sunxi/spl_pinmux.c +++ b/arch/arm/mach-sunxi/spl_pinmux.c @@ -17,95 +17,105 @@ #include #include +static void i2c0_init_board(void) +{ + if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN5I) || + IS_ENABLED(CONFIG_MACH_SUN7I) || IS_ENABLED(CONFIG_MACH_SUN8I_R40)) { + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); + clock_twi_onoff(0, 1); + } else if (IS_ENABLED(CONFIG_MACH_SUN6I)) { + sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); + clock_twi_onoff(0, 1); + } else if (IS_ENABLED(CONFIG_MACH_SUN8I_V3S)) { + sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0); + clock_twi_onoff(0, 1); + } else if (IS_ENABLED(CONFIG_MACH_SUN8I)) { + sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); + clock_twi_onoff(0, 1); + } else if (IS_ENABLED(CONFIG_MACH_SUN50I)) { + sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0); + clock_twi_onoff(0, 1); + } +} + +static void i2c1_init_board(void) +{ + if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) || + IS_ENABLED(CONFIG_MACH_SUN8I_R40)) { + sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); + clock_twi_onoff(1, 1); + } else if (IS_ENABLED(CONFIG_MACH_SUN5I)) { + sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); + clock_twi_onoff(1, 1); + } else if (IS_ENABLED(CONFIG_MACH_SUN6I)) { + sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); + clock_twi_onoff(1, 1); + } else if (IS_ENABLED(CONFIG_MACH_SUN8I)) { + sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); + clock_twi_onoff(1, 1); + } else if (IS_ENABLED(CONFIG_MACH_SUN50I)) { + sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1); + clock_twi_onoff(1, 1); + } +} + +static void i2cr_init_board(void) +{ + if (IS_ENABLED(CONFIG_MACH_SUN50I)) { + clock_twi_onoff(5, 1); + sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI); + sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI); + } else if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) { + clock_twi_onoff(5, 1); + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI); + } else { + clock_twi_onoff(5, 1); + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); + } +} + void i2c_init_board(void) { -#ifdef CONFIG_I2C0_ENABLE -#if defined(CONFIG_MACH_SUN4I) || \ - defined(CONFIG_MACH_SUN5I) || \ - defined(CONFIG_MACH_SUN7I) || \ - defined(CONFIG_MACH_SUN8I_R40) - sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); - sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); - clock_twi_onoff(0, 1); -#elif defined(CONFIG_MACH_SUN6I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); - sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); - clock_twi_onoff(0, 1); -#elif defined(CONFIG_MACH_SUN8I_V3S) - sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0); - sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0); - clock_twi_onoff(0, 1); -#elif defined(CONFIG_MACH_SUN8I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); - sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); - clock_twi_onoff(0, 1); -#elif defined(CONFIG_MACH_SUN50I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0); - sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0); - clock_twi_onoff(0, 1); -#endif -#endif /* CONFIG_I2C0_ENABLE */ + if (IS_ENABLED(CONFIG_I2C0_ENABLE)) + i2c0_init_board(); -#ifdef CONFIG_I2C1_ENABLE -#if defined(CONFIG_MACH_SUN4I) || \ - defined(CONFIG_MACH_SUN7I) || \ - defined(CONFIG_MACH_SUN8I_R40) - sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); - sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); - clock_twi_onoff(1, 1); -#elif defined(CONFIG_MACH_SUN5I) - sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); - sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); - clock_twi_onoff(1, 1); -#elif defined(CONFIG_MACH_SUN6I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); - sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); - clock_twi_onoff(1, 1); -#elif defined(CONFIG_MACH_SUN8I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); - sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); - clock_twi_onoff(1, 1); -#elif defined(CONFIG_MACH_SUN50I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1); - sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1); - clock_twi_onoff(1, 1); -#endif -#endif /* CONFIG_I2C1_ENABLE */ + if (IS_ENABLED(CONFIG_I2C1_ENABLE)) + i2c1_init_board(); -#ifdef CONFIG_R_I2C_ENABLE -#ifdef CONFIG_MACH_SUN50I - clock_twi_onoff(5, 1); - sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI); - sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI); -#elif defined(CONFIG_MACH_SUN50I_H616) - clock_twi_onoff(5, 1); - sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI); - sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI); -#else - clock_twi_onoff(5, 1); - sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); - sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); -#endif -#endif /* CONFIG_R_I2C_ENABLE */ + if (IS_ENABLED(CONFIG_R_I2C_ENABLE)) + i2cr_init_board(); } #if defined(CONFIG_NAND_SUNXI) -static void nand_pinmux_setup(void) +void nand_pinmux_setup(void) { unsigned int pin; for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); -#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I - for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); -#endif - /* sun4i / sun7i do have a PC23, but it is not used for nand, - * only sun7i has a PC24 */ -#ifdef CONFIG_MACH_SUN7I - sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); -#endif + if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I)) { + for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); + } + /* + * sun4i / sun7i do have a PC23, but it is not used for NAND. + * Only sun7i has a PC24. + */ + if (IS_ENABLED(CONFIG_MACH_SUN7I)) + sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); } static void nand_clock_setup(void) @@ -114,10 +124,12 @@ static void nand_clock_setup(void) (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); + #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \ - defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I + defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0)); #endif + setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); } @@ -131,174 +143,149 @@ void board_nand_init(void) #ifdef CONFIG_MMC static void mmc_pinmux_setup(int sdc) { - unsigned int pin; + unsigned int pin, first_pin, last_pin, pin_mux; + unsigned int skip_pin = ~0, extra_pin = ~0; switch (sdc) { case 0: /* SDC0: PF0-PF5 */ - for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } + first_pin = SUNXI_GPF(0); + last_pin = SUNXI_GPF(5); + pin_mux = SUNXI_GPF_SDC0; break; - case 1: -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ - defined(CONFIG_MACH_SUN8I_R40) - if (IS_ENABLED(CONFIG_MMC1_PINS_PH)) { - /* SDC1: PH22-PH-27 */ - for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { - sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); + if (IS_ENABLED(CONFIG_MACH_SUN4I) || + IS_ENABLED(CONFIG_MACH_SUN7I) || + IS_ENABLED(CONFIG_MACH_SUN8I_R40)) { + if (IS_ENABLED(CONFIG_MMC1_PINS_PH)) { + /* SDC1: PH22-PH-27 */ + first_pin = SUNXI_GPH(22); + last_pin = SUNXI_GPH(27); + pin_mux = SUN4I_GPH_SDC1; + } else { + /* SDC1: PG0-PG5 */ + first_pin = SUNXI_GPG(0); + last_pin = SUNXI_GPG(5); + pin_mux = SUN4I_GPG_SDC1; } - } else { + } else if (IS_ENABLED(CONFIG_MACH_SUN5I)) { + /* SDC1: PG3-PG8 */ + first_pin = SUNXI_GPG(3); + last_pin = SUNXI_GPG(8); + pin_mux = SUN4I_GPG_SDC1; + } else if (IS_ENABLED(CONFIG_MACH_SUN6I)) { /* SDC1: PG0-PG5 */ - for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { - sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } - } -#elif defined(CONFIG_MACH_SUN5I) - /* SDC1: PG3-PG8 */ - for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { - sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } -#elif defined(CONFIG_MACH_SUN6I) - /* SDC1: PG0-PG5 */ - for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { - sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } -#elif defined(CONFIG_MACH_SUN8I) - /* SDC1: PG0-PG5 */ - for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { - sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); + first_pin = SUNXI_GPG(0); + last_pin = SUNXI_GPG(5); + pin_mux = SUN6I_GPG_SDC1; + } else if (IS_ENABLED(CONFIG_MACH_SUN8I)) { + /* SDC1: PG0-PG5 */ + first_pin = SUNXI_GPG(0); + last_pin = SUNXI_GPG(5); + pin_mux = SUN8I_GPG_SDC1; } -#endif break; - case 2: -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) - /* SDC2: PC6-PC11 */ - for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } -#elif defined(CONFIG_MACH_SUN5I) - /* SDC2: PC6-PC15 */ - for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } -#elif defined(CONFIG_MACH_SUN6I) - /* SDC2: PC6-PC15, PC24 */ - for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } + if (IS_ENABLED(CONFIG_MACH_SUN4I) || + IS_ENABLED(CONFIG_MACH_SUN7I)) { + /* SDC2: PC6-PC11 */ + first_pin = SUNXI_GPG(6); + last_pin = SUNXI_GPG(11); + pin_mux = SUNXI_GPC_SDC2; + } else if (IS_ENABLED(CONFIG_MACH_SUN5I)) { + /* SDC2: PC6-PC15 */ + first_pin = SUNXI_GPG(6); + last_pin = SUNXI_GPG(15); + pin_mux = SUNXI_GPC_SDC2; + } else if (IS_ENABLED(CONFIG_MACH_SUN6I)) { + /* SDC2: PC6-PC15, PC24 */ + first_pin = SUNXI_GPG(6); + last_pin = SUNXI_GPG(15); + extra_pin = SUNXI_GPC(24); + pin_mux = SUNXI_GPC_SDC2; + } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) { + /* SDC2: PC6-PC15, PC24 */ + first_pin = SUNXI_GPC(6); + last_pin = SUNXI_GPC(15); + extra_pin = SUNXI_GPC(24); + pin_mux = SUNXI_GPC_SDC2; + } else if (IS_ENABLED(CONFIG_MACH_SUN8I) || + IS_ENABLED(CONFIG_MACH_SUN50I)) { + /* SDC2: PC5-PC6, PC8-PC16 */ + first_pin = SUNXI_GPC(5); + last_pin = SUNXI_GPC(16); + skip_pin = SUNXI_GPC(7); + pin_mux = SUNXI_GPC_SDC2; + } else if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) { + /* SDC2: PC4-PC14 */ + first_pin = SUNXI_GPC(4); + last_pin = SUNXI_GPC(14); + pin_mux = SUNXI_GPC_SDC2; + } else if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) { + /* SDC2: PC0-PC1, PC5-PC6, PC8-PC11, PC13-PC16 */ + first_pin = SUNXI_GPC(5); + last_pin = SUNXI_GPC(11); + skip_pin = SUNXI_GPC(7); + pin_mux = SUNXI_GPC_SDC2; - sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(SUNXI_GPC(24), 2); -#elif defined(CONFIG_MACH_SUN8I_R40) - /* SDC2: PC6-PC15, PC24 */ - for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } - - sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(SUNXI_GPC(24), 2); -#elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I) - /* SDC2: PC5-PC6, PC8-PC16 */ - for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } - - for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } -#elif defined(CONFIG_MACH_SUN50I_H6) - /* SDC2: PC4-PC14 */ - for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } -#elif defined(CONFIG_MACH_SUN50I_H616) - /* SDC2: PC0-PC1, PC5-PC6, PC8-PC11, PC13-PC16 */ - for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(16); pin++) { - if (pin > SUNXI_GPC(1) && pin < SUNXI_GPC(5)) - continue; - if (pin == SUNXI_GPC(7) || pin == SUNXI_GPC(12)) - continue; - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 3); - } -#elif defined(CONFIG_MACH_SUN9I) - /* SDC2: PC6-PC16 */ - for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } -#elif defined(CONFIG_MACH_SUN8I_R528) - /* SDC2: PC2-PC7 */ - for (pin = SUNXI_GPC(2); pin <= SUNXI_GPC(7); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); + for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(1); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 3); + } + for (pin = SUNXI_GPC(13); pin <= SUNXI_GPC(16); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 3); + } + } else if (IS_ENABLED(CONFIG_MACH_SUN9I)) { + /* SDC2: PC6-PC16 */ + first_pin = SUNXI_GPC(6); + last_pin = SUNXI_GPC(16); + pin_mux = SUNXI_GPC_SDC2; + } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) { + /* SDC2: PC2-PC7 */ + first_pin = SUNXI_GPC(2); + last_pin = SUNXI_GPC(7); + pin_mux = SUNXI_GPC_SDC2; + } else { + puts("ERROR: No pinmux setup defined for MMC2!\n"); } -#else - puts("ERROR: No pinmux setup defined for MMC2!\n"); -#endif break; - case 3: -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ - defined(CONFIG_MACH_SUN8I_R40) - /* SDC3: PI4-PI9 */ - for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); + if (IS_ENABLED(CONFIG_MACH_SUN4I) || + IS_ENABLED(CONFIG_MACH_SUN7I) || + IS_ENABLED(CONFIG_MACH_SUN8I_R40)) { + /* SDC3: PI4-PI9 */ + first_pin = SUNXI_GPI(4); + last_pin = SUNXI_GPI(9); + pin_mux = SUNXI_GPI_SDC3; + } else if (IS_ENABLED(CONFIG_MACH_SUN6I)) { + /* SDC3: PC6-PC15, PC24 */ + first_pin = SUNXI_GPC(6); + last_pin = SUNXI_GPC(15); + extra_pin = SUNXI_GPC(24); + pin_mux = SUN6I_GPC_SDC3; } -#elif defined(CONFIG_MACH_SUN6I) - /* SDC3: PC6-PC15, PC24 */ - for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { - sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } - - sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); - sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(SUNXI_GPC(24), 2); -#endif break; default: printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); break; } + + for (pin = first_pin; pin <= last_pin; pin++) { + if (pin == skip_pin) + continue; + sunxi_gpio_set_cfgpin(pin, pin_mux); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + if (extra_pin != ~0) { + sunxi_gpio_set_cfgpin(extra_pin, pin_mux); + sunxi_gpio_set_pull(extra_pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(extra_pin, 2); + } } int board_mmc_init(struct bd_info *bis) @@ -322,5 +309,4 @@ int board_mmc_init(struct bd_info *bis) return 0; } - #endif /* CONFIG_MMC */ From patchwork Wed Jan 3 00:12:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1881815 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T4VdJ4frlz20Rq for ; Wed, 3 Jan 2024 11:16:35 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 73CBE879F9; Wed, 3 Jan 2024 01:13:52 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 5E15F87A06; Wed, 3 Jan 2024 01:13:51 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 6234287950 for ; Wed, 3 Jan 2024 01:13:48 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 042991516; Tue, 2 Jan 2024 16:14:34 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 19A233F5A1; Tue, 2 Jan 2024 16:13:46 -0800 (PST) From: Andre Przywara To: Jagan Teki Cc: Samuel Holland , linux-sunxi@lists.linux.dev, u-boot@lists.denx.de Subject: [PATCH 17/19] sunxi: move UART pinmux setup into separate file Date: Wed, 3 Jan 2024 00:12:37 +0000 Message-Id: <20240103001239.17482-18-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20240103001239.17482-1-andre.przywara@arm.com> References: <20240103001239.17482-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The code that programs the pinmuxes for the configured UART dominates the gpio_init() function, and is only needed by SPL code. Move those lines into a separate function in a new file, that gets compiled for the SPL only. That simplifies further cleanup, and helps to separate SPL-only code from generic code. To help review, this only copies the code (generating some checkpatch complaints), further cleanup will be provided in subsequent patches. Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/Makefile | 1 + arch/arm/mach-sunxi/board.c | 110 ++------------------------ arch/arm/mach-sunxi/uart_pinmux.c | 124 ++++++++++++++++++++++++++++++ 3 files changed, 130 insertions(+), 105 deletions(-) create mode 100644 arch/arm/mach-sunxi/uart_pinmux.c diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index c15ef01aaad..9a9dffc176f 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -32,6 +32,7 @@ endif ifdef CONFIG_SPL_BUILD obj-y += clock.o obj-y += spl_pinmux.o +obj-y += uart_pinmux.o obj-$(CONFIG_MACH_SUNIV) += dram_suniv.o obj-$(CONFIG_DRAM_SUN4I) += dram_sun4i.o obj-$(CONFIG_DRAM_SUN6I) += dram_sun6i.o diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 0140b07d32a..dd642c0d2f0 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -75,113 +75,13 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) #endif /* CONFIG_ARM64 */ #ifdef CONFIG_SPL_BUILD +void uart_pinmux_setup(void); + static int gpio_init(void) { - __maybe_unused uint val; -#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) -#if defined(CONFIG_MACH_SUN4I) || \ - defined(CONFIG_MACH_SUN7I) || \ - defined(CONFIG_MACH_SUN8I_R40) - /* disable GPB22,23 as uart0 tx,rx to avoid conflict */ - sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); - sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); -#endif -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || \ - defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I_R40) || \ - defined(CONFIG_MACH_SUN9I) - sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0); -#else - sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0); -#endif - sunxi_gpio_set_pull(SUNXI_GPF(4), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNIV) - sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0); - sunxi_gpio_set_pull(SUNXI_GPE(1), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \ - defined(CONFIG_MACH_SUN7I) || \ - defined(CONFIG_MACH_SUN8I_R40)) - sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0); - sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I) - sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0); - sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0); - sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33) - sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0); - sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5) - sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0); - sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I) - sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0); - sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6) - sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0); - sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H616) - sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H616_GPH_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H616_GPH_UART0); - sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T) - sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); - sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S) - sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0); - sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); - sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_R528) - sunxi_gpio_set_cfgpin(SUNXI_GPE(2), 6); - sunxi_gpio_set_cfgpin(SUNXI_GPE(3), 6); - sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV) - sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0); - sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) - sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); - sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); - sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I_H3) - sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUN8I_H3_GPA_UART2); - sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUN8I_H3_GPA_UART2); - sunxi_gpio_set_pull(SUNXI_GPA(1), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) - sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); - sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); - sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 4 && defined(CONFIG_MACH_SUN8I_R528) - sunxi_gpio_set_cfgpin(SUNXI_GPB(6), 7); - sunxi_gpio_set_cfgpin(SUNXI_GPB(7), 7); - sunxi_gpio_set_pull(SUNXI_GPB(7), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) - sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); - sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); - sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \ - !defined(CONFIG_MACH_SUN8I_R40) - sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1); - sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_GPG_UART1); - sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP); -#else -#error Unsupported console port number. Please fix pin mux settings in board.c -#endif + u32 val; + + uart_pinmux_setup(); /* * Update PIO power bias configuration by copying the hardware diff --git a/arch/arm/mach-sunxi/uart_pinmux.c b/arch/arm/mach-sunxi/uart_pinmux.c new file mode 100644 index 00000000000..af5ecc4fb3c --- /dev/null +++ b/arch/arm/mach-sunxi/uart_pinmux.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2023 Arm Ltd. + * (C) Copyright 2012-2013 Henrik Nordstrom + * (C) Copyright 2013 Luke Kenneth Casson Leighton + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * Code to setup the UART pinmux configuration in the SPL, which lacks + * the DT to look this up properly. + */ + +#include +#include +#include + +void uart_pinmux_setup(void) +{ +#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) +#if defined(CONFIG_MACH_SUN4I) || \ + defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + /* disable GPB22,23 as uart0 tx,rx to avoid conflict */ + sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); + sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); +#endif +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || \ + defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I_R40) || \ + defined(CONFIG_MACH_SUN9I) + sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0); +#else + sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0); +#endif + sunxi_gpio_set_pull(SUNXI_GPF(4), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNIV) + sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0); + sunxi_gpio_set_pull(SUNXI_GPE(1), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \ + defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40)) + sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I) + sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0); + sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33) + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5) + sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0); + sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I) + sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6) + sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0); + sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H616) + sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H616_GPH_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H616_GPH_UART0); + sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T) + sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S) + sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); + sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_R528) + sunxi_gpio_set_cfgpin(SUNXI_GPE(2), 6); + sunxi_gpio_set_cfgpin(SUNXI_GPE(3), 6); + sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV) + sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0); + sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) + sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); + sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); + sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I_H3) + sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUN8I_H3_GPA_UART2); + sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUN8I_H3_GPA_UART2); + sunxi_gpio_set_pull(SUNXI_GPA(1), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); + sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 4 && defined(CONFIG_MACH_SUN8I_R528) + sunxi_gpio_set_cfgpin(SUNXI_GPB(6), 7); + sunxi_gpio_set_cfgpin(SUNXI_GPB(7), 7); + sunxi_gpio_set_pull(SUNXI_GPB(7), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); + sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); + sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \ + !defined(CONFIG_MACH_SUN8I_R40) + sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1); + sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_GPG_UART1); + sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP); +#else +#error Unsupported console port number. Please fix pin mux settings in board.c +#endif +} From patchwork Wed Jan 3 00:12:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1881816 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T4VdT5jbDz20Rq for ; Wed, 3 Jan 2024 11:16:45 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E43EA879E5; Wed, 3 Jan 2024 01:13:52 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id A524587A07; Wed, 3 Jan 2024 01:13:51 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 70093879F2 for ; Wed, 3 Jan 2024 01:13:49 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0F6D4C15; Tue, 2 Jan 2024 16:14:35 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 252953F5A1; Tue, 2 Jan 2024 16:13:48 -0800 (PST) From: Andre Przywara To: Jagan Teki Cc: Samuel Holland , linux-sunxi@lists.linux.dev, u-boot@lists.denx.de Subject: [PATCH 18/19] sunxi: SPL pinmux: split out UART pinmux per port Date: Wed, 3 Jan 2024 00:12:38 +0000 Message-Id: <20240103001239.17482-19-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20240103001239.17482-1-andre.przywara@arm.com> References: <20240103001239.17482-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The UART SPL pinmux function is particularly hard to read, as it combines per-SoC definitions with per-configuration choices (which UART to use). Split the existing single function into one per UART port, to reduce the #ifdef hell and improve readability. The four cases which deal with UARTs other than 0 or 1 are left in the main function, to reduce clutter. Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/uart_pinmux.c | 66 ++++++++++++++++++++----------- 1 file changed, 42 insertions(+), 24 deletions(-) diff --git a/arch/arm/mach-sunxi/uart_pinmux.c b/arch/arm/mach-sunxi/uart_pinmux.c index af5ecc4fb3c..cb4b16f0e37 100644 --- a/arch/arm/mach-sunxi/uart_pinmux.c +++ b/arch/arm/mach-sunxi/uart_pinmux.c @@ -15,9 +15,8 @@ #include #include -void uart_pinmux_setup(void) +void uart0_portf_pinmux_setup(void) { -#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) #if defined(CONFIG_MACH_SUN4I) || \ defined(CONFIG_MACH_SUN7I) || \ defined(CONFIG_MACH_SUN8I_R40) @@ -35,68 +34,92 @@ void uart_pinmux_setup(void) sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0); #endif sunxi_gpio_set_pull(SUNXI_GPF(4), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNIV) +} + +void uart0_pinmux_setup(void) +{ +#if defined(CONFIG_MACH_SUNIV) sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0); sunxi_gpio_set_pull(SUNXI_GPE(1), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \ - defined(CONFIG_MACH_SUN7I) || \ - defined(CONFIG_MACH_SUN8I_R40)) +#elif (defined(CONFIG_MACH_SUN4I) || \ + defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40)) sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0); sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I) +#elif defined(CONFIG_MACH_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0); sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I) +#elif defined(CONFIG_MACH_SUN6I) sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0); sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33) +#elif defined(CONFIG_MACH_SUN8I_A33) sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0); sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5) +#elif defined(CONFIG_MACH_SUNXI_H3_H5) sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0); sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I) +#elif defined(CONFIG_MACH_SUN50I) sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0); sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6) +#elif defined(CONFIG_MACH_SUN50I_H6) sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0); sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H616) +#elif defined(CONFIG_MACH_SUN50I_H616) sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H616_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H616_GPH_UART0); sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T) +#elif defined(CONFIG_MACH_SUN8I_A83T) sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S) +#elif defined(CONFIG_MACH_SUN8I_V3S) sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0); sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I) +#elif defined(CONFIG_MACH_SUN9I) sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_R528) +#elif defined(CONFIG_MACH_SUN8I_R528) sunxi_gpio_set_cfgpin(SUNXI_GPE(2), 6); sunxi_gpio_set_cfgpin(SUNXI_GPE(3), 6); sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV) +#endif +} + +void uart1_pinmux_setup(void) +{ +#if defined(CONFIG_MACH_SUNIV) sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0); sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) +#elif defined(CONFIG_MACH_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); +#elif defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40) + sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1); + sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_GPG_UART1); + sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP); +#endif +} + +void uart_pinmux_setup(void) +{ +#if CONFIG_CONS_INDEX == 1 + uart0_pinmux_setup(); + return; +#elif CONFIG_CONS_INDEX == 2 + uart1_pinmux_setup(); + return; #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I_H3) sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUN8I_H3_GPA_UART2); sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUN8I_H3_GPA_UART2); @@ -113,11 +136,6 @@ void uart_pinmux_setup(void) sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \ - !defined(CONFIG_MACH_SUN8I_R40) - sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1); - sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_GPG_UART1); - sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP); #else #error Unsupported console port number. Please fix pin mux settings in board.c #endif From patchwork Wed Jan 3 00:12:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1881817 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T4Vdj03h4z20Rq for ; Wed, 3 Jan 2024 11:16:56 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 593A0879E2; Wed, 3 Jan 2024 01:13:55 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 7586D87A0A; Wed, 3 Jan 2024 01:13:53 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 79B3F879E4 for ; Wed, 3 Jan 2024 01:13:50 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1ABAA14BF; Tue, 2 Jan 2024 16:14:36 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 305DF3F5A1; Tue, 2 Jan 2024 16:13:49 -0800 (PST) From: Andre Przywara To: Jagan Teki Cc: Samuel Holland , linux-sunxi@lists.linux.dev, u-boot@lists.denx.de Subject: [PATCH 19/19] sunxi: SPL pinmux: rewrite UART setup without #ifdefs Date: Wed, 3 Jan 2024 00:12:39 +0000 Message-Id: <20240103001239.17482-20-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20240103001239.17482-1-andre.przywara@arm.com> References: <20240103001239.17482-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The existing SPL UART pinmux setup is using #ifdef's heavily, which makes it hard to read and even harder to extend. Replace the #ifdef's with proper C "if" statements, with the help of the magic IS_ENABLED() macro. To cover the non-configured case, which is currently handled by an #error preprocessor directive, create a prototype for a non-existing function. Replace that #error line with a call to that function, which will be removed by the compiler and linker in the normal case, but will cause a linker error otherwise. Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/uart_pinmux.c | 240 ++++++++++++++++-------------- 1 file changed, 128 insertions(+), 112 deletions(-) diff --git a/arch/arm/mach-sunxi/uart_pinmux.c b/arch/arm/mach-sunxi/uart_pinmux.c index cb4b16f0e37..ba42352fbcf 100644 --- a/arch/arm/mach-sunxi/uart_pinmux.c +++ b/arch/arm/mach-sunxi/uart_pinmux.c @@ -15,128 +15,144 @@ #include #include -void uart0_portf_pinmux_setup(void) +/* Non-existing function to trigger speaking link error. */ +void Unsupported_console_number_Please_fix_UART_pin_mux_settings(void); + +static void uart0_portf_pinmux_setup(void) { -#if defined(CONFIG_MACH_SUN4I) || \ - defined(CONFIG_MACH_SUN7I) || \ - defined(CONFIG_MACH_SUN8I_R40) - /* disable GPB22,23 as uart0 tx,rx to avoid conflict */ - sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); - sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); -#endif -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || \ - defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I_R40) || \ - defined(CONFIG_MACH_SUN9I) - sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0); -#else - sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0); -#endif + if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) || + IS_ENABLED(CONFIG_MACH_SUN8I_R40)) { + /* disable GPB22,23 as uart0 tx,rx to avoid conflict */ + sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); + sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); + } + + if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN5I) || + IS_ENABLED(CONFIG_MACH_SUN7I) || IS_ENABLED(CONFIG_MACH_SUN8I_R40) || + IS_ENABLED(CONFIG_MACH_SUN9I)) { + sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0); + } else { + sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0); + } sunxi_gpio_set_pull(SUNXI_GPF(4), SUNXI_GPIO_PULL_UP); } -void uart0_pinmux_setup(void) +static void uart0_pinmux_setup(void) { -#if defined(CONFIG_MACH_SUNIV) - sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0); - sunxi_gpio_set_pull(SUNXI_GPE(1), SUNXI_GPIO_PULL_UP); -#elif (defined(CONFIG_MACH_SUN4I) || \ - defined(CONFIG_MACH_SUN7I) || \ - defined(CONFIG_MACH_SUN8I_R40)) - sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0); - sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); -#elif defined(CONFIG_MACH_SUN5I) - sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0); - sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP); -#elif defined(CONFIG_MACH_SUN6I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0); - sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); -#elif defined(CONFIG_MACH_SUN8I_A33) - sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0); - sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); -#elif defined(CONFIG_MACH_SUNXI_H3_H5) - sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0); - sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP); -#elif defined(CONFIG_MACH_SUN50I) - sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0); - sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); -#elif defined(CONFIG_MACH_SUN50I_H6) - sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0); - sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); -#elif defined(CONFIG_MACH_SUN50I_H616) - sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H616_GPH_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H616_GPH_UART0); - sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); -#elif defined(CONFIG_MACH_SUN8I_A83T) - sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); - sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); -#elif defined(CONFIG_MACH_SUN8I_V3S) - sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0); - sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); -#elif defined(CONFIG_MACH_SUN9I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); - sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); -#elif defined(CONFIG_MACH_SUN8I_R528) - sunxi_gpio_set_cfgpin(SUNXI_GPE(2), 6); - sunxi_gpio_set_cfgpin(SUNXI_GPE(3), 6); - sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP); -#endif + if (IS_ENABLED(CONFIG_UART0_PORT_F)) { + uart0_portf_pinmux_setup(); + return; + } + + if (IS_ENABLED(CONFIG_MACH_SUNIV)) { + sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0); + sunxi_gpio_set_pull(SUNXI_GPE(1), SUNXI_GPIO_PULL_UP); + } else if (IS_ENABLED(CONFIG_MACH_SUN4I) || + IS_ENABLED(CONFIG_MACH_SUN7I) || + IS_ENABLED(CONFIG_MACH_SUN8I_R40)) { + sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); + } else if (IS_ENABLED(CONFIG_MACH_SUN5I)) { + sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP); + } else if (IS_ENABLED(CONFIG_MACH_SUN6I)) { + sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0); + sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); + } else if (IS_ENABLED(CONFIG_MACH_SUN8I_A33)) { + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); + } else if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5)) { + sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0); + sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP); + } else if (IS_ENABLED(CONFIG_MACH_SUN50I)) { + sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); + } else if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) { + sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0); + sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); + } else if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) { + sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H616_GPH_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H616_GPH_UART0); + sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); + } else if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T)) { + sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); + } else if (IS_ENABLED(CONFIG_MACH_SUN8I_V3S)) { + sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); + } else if (IS_ENABLED(CONFIG_MACH_SUN9I)) { + sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); + sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); + } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) { + sunxi_gpio_set_cfgpin(SUNXI_GPE(2), 6); + sunxi_gpio_set_cfgpin(SUNXI_GPE(3), 6); + sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP); + } else { + Unsupported_console_number_Please_fix_UART_pin_mux_settings(); + } } -void uart1_pinmux_setup(void) +static void uart1_pinmux_setup(void) { -#if defined(CONFIG_MACH_SUNIV) - sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0); - sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP); -#elif defined(CONFIG_MACH_SUN5I) - sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); - sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); - sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); -#elif defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40) - sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1); - sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_GPG_UART1); - sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP); -#endif + if (IS_ENABLED(CONFIG_MACH_SUNIV)) { + sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0); + sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP); + } else if (IS_ENABLED(CONFIG_MACH_SUN5I)) { + sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); + sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); + sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); + } else if (IS_ENABLED(CONFIG_MACH_SUN8I) && + !IS_ENABLED(CONFIG_MACH_SUN8I_R40)) { + sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1); + sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_GPG_UART1); + sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP); + } else { + Unsupported_console_number_Please_fix_UART_pin_mux_settings(); + } } void uart_pinmux_setup(void) { -#if CONFIG_CONS_INDEX == 1 - uart0_pinmux_setup(); - return; -#elif CONFIG_CONS_INDEX == 2 - uart1_pinmux_setup(); - return; -#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I_H3) - sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUN8I_H3_GPA_UART2); - sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUN8I_H3_GPA_UART2); - sunxi_gpio_set_pull(SUNXI_GPA(1), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) - sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); - sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); - sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 4 && defined(CONFIG_MACH_SUN8I_R528) - sunxi_gpio_set_cfgpin(SUNXI_GPB(6), 7); - sunxi_gpio_set_cfgpin(SUNXI_GPB(7), 7); - sunxi_gpio_set_pull(SUNXI_GPB(7), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) - sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); - sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); - sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); -#else -#error Unsupported console port number. Please fix pin mux settings in board.c -#endif + if (CONFIG_CONS_INDEX == 1) { + uart0_pinmux_setup(); + return; + } + if (CONFIG_CONS_INDEX == 2) { + uart1_pinmux_setup(); + return; + } + if (CONFIG_CONS_INDEX == 3 && IS_ENABLED(CONFIG_MACH_SUN8I_H3)) { + sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUN8I_H3_GPA_UART2); + sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUN8I_H3_GPA_UART2); + sunxi_gpio_set_pull(SUNXI_GPA(1), SUNXI_GPIO_PULL_UP); + } else if (CONFIG_CONS_INDEX == 3 && IS_ENABLED(CONFIG_MACH_SUN8I)) { + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); + sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); + } else if (CONFIG_CONS_INDEX == 4 && + IS_ENABLED(CONFIG_MACH_SUN8I_R528)) { + sunxi_gpio_set_cfgpin(SUNXI_GPB(6), 7); + sunxi_gpio_set_cfgpin(SUNXI_GPB(7), 7); + sunxi_gpio_set_pull(SUNXI_GPB(7), SUNXI_GPIO_PULL_UP); + } else if (CONFIG_CONS_INDEX == 5 && IS_ENABLED(CONFIG_MACH_SUN8I)) { + sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); + sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); + sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); + } else { + Unsupported_console_number_Please_fix_UART_pin_mux_settings(); + } }