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Wed, 8 Nov 2023 12:30:56 +0000 From: Leo Hou To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, jason.chien@sifive.com, zhangdongxue@canaan-creative.com, Leo Hou Subject: [PATCH 1/1] Changed the way aclint gets CPUState from hartid-base to cpu_index Date: Wed, 8 Nov 2023 20:30:46 +0800 Message-Id: X-Mailer: git-send-email 2.37.1 In-Reply-To: References: X-ClientProxiedBy: ZQ0PR01CA0021.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:2::14) To BJSPR01MB0627.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:d::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BJSPR01MB0627:EE_|BJSPR01MB0881:EE_ X-MS-Office365-Filtering-Correlation-Id: d572467c-82ae-4f3c-0efd-08dbe0568e65 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Swzs0ueJoNVxMtCvGsBwZALWiVGBbAn/Gv9oBEvfL7N/wPLlmDIdoIrGHS8x0Cp36JcVI/fmwX2VxdN1ui/uy5X2uvXTFqF7im7ewnH4JYd72EUTnxW8ILK6NMXSETT/EoNuE7Pzrehu8YEkOygpxpVe4yUse2Zx0uukMaPomEATq/y/Yp8IikX0WyfWLUhXEyCO+ZGzYBv9fZWOn2oJyhDSJwQ5T3RC+VcZdQHGiuSwnsmOSoiXAs2zV2HjbSZ13CBPjjU/2W31J05JYp9IsVYC/nhvwWt1h4oyacI78Syke6EYSBOQUVbKK3PglhhoYw+bxifusbGF5K5vNk2+4POrq5xnoLGe8fRAxSZ/9anqskW/XEZ2Xiisqq24xAg2LAJIddCrdTRk6VctuubMyzlquqRhw4W+NmYo3FK2B7nsJVKDjd75HAMKdEPcaJs+Re5930n2TUiL4aTJNt9xxoClD0jGg8mM/wjZTVbVTTHrdt7ckYt9LTY6QwhTu9SbARMdeqOeoC06BIlTBkWr4R7DrSENRpHZTBFlsE4Epif8tVIozoOBywtb37Zc4Kus X-Forefront-Antispam-Report: CIP:255.255.255.255; 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envelope-from=LeoHou@canaan-creative.com; helo=CHN02-BJS-obe.outbound.protection.partner.outlook.cn X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01, T_SPF_PERMERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Leo Hou cpu_by_arch_id() uses hartid-base as the index to obtain the corresponding CPUState structure variable. qemu_get_cpu() uses cpu_index as the index to obtain the corresponding CPUState structure variable. In heterogeneous CPU or multi-socket scenarios, multiple aclint needs to be instantiated, and the hartid-base of each cpu bound by aclint can start from 0. If cpu_by_arch_id() is still used in this case, all aclint will bind to the earliest initialized hart with hartid-base 0 and cause conflicts. So with cpu_index as the index, use qemu_get_cpu() to get the CPUState struct variable, and connect the aclint interrupt line to the hart of the CPU indexed with cpu_index (the corresponding hartid-base can start at 0). It's more reasonable. Signed-off-by: Leo Hou --- hw/intc/riscv_aclint.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index ab1a0b4b3a..be8f539fcb 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -130,7 +130,7 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr, addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) { size_t hartid = mtimer->hartid_base + ((addr - mtimer->timecmp_base) >> 3); - CPUState *cpu = cpu_by_arch_id(hartid); + CPUState *cpu = qemu_get_cpu(hartid); CPURISCVState *env = cpu ? cpu_env(cpu) : NULL; if (!env) { qemu_log_mask(LOG_GUEST_ERROR, @@ -173,7 +173,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr, addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) { size_t hartid = mtimer->hartid_base + ((addr - mtimer->timecmp_base) >> 3); - CPUState *cpu = cpu_by_arch_id(hartid); + CPUState *cpu = qemu_get_cpu(hartid); CPURISCVState *env = cpu ? cpu_env(cpu) : NULL; if (!env) { qemu_log_mask(LOG_GUEST_ERROR, @@ -232,7 +232,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr, /* Check if timer interrupt is triggered for each hart. */ for (i = 0; i < mtimer->num_harts; i++) { - CPUState *cpu = cpu_by_arch_id(mtimer->hartid_base + i); + CPUState *cpu = qemu_get_cpu(mtimer->hartid_base + i); CPURISCVState *env = cpu ? cpu_env(cpu) : NULL; if (!env) { continue; @@ -293,7 +293,7 @@ static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp) s->timecmp = g_new0(uint64_t, s->num_harts); /* Claim timer interrupt bits */ for (i = 0; i < s->num_harts; i++) { - RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(s->hartid_base + i)); + RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i)); if (riscv_cpu_claim_interrupts(cpu, MIP_MTIP) < 0) { error_report("MTIP already claimed"); exit(1); @@ -373,7 +373,7 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size, sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); for (i = 0; i < num_harts; i++) { - CPUState *cpu = cpu_by_arch_id(hartid_base + i); + CPUState *cpu = qemu_get_cpu(hartid_base + i); RISCVCPU *rvcpu = RISCV_CPU(cpu); CPURISCVState *env = cpu ? cpu_env(cpu) : NULL; riscv_aclint_mtimer_callback *cb = @@ -408,7 +408,7 @@ static uint64_t riscv_aclint_swi_read(void *opaque, hwaddr addr, if (addr < (swi->num_harts << 2)) { size_t hartid = swi->hartid_base + (addr >> 2); - CPUState *cpu = cpu_by_arch_id(hartid); + CPUState *cpu = qemu_get_cpu(hartid); CPURISCVState *env = cpu ? cpu_env(cpu) : NULL; if (!env) { qemu_log_mask(LOG_GUEST_ERROR, @@ -431,7 +431,7 @@ static void riscv_aclint_swi_write(void *opaque, hwaddr addr, uint64_t value, if (addr < (swi->num_harts << 2)) { size_t hartid = swi->hartid_base + (addr >> 2); - CPUState *cpu = cpu_by_arch_id(hartid); + CPUState *cpu = qemu_get_cpu(hartid); CPURISCVState *env = cpu ? cpu_env(cpu) : NULL; if (!env) { qemu_log_mask(LOG_GUEST_ERROR, @@ -546,7 +546,7 @@ DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base, sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); for (i = 0; i < num_harts; i++) { - CPUState *cpu = cpu_by_arch_id(hartid_base + i); + CPUState *cpu = qemu_get_cpu(hartid_base + i); RISCVCPU *rvcpu = RISCV_CPU(cpu); qdev_connect_gpio_out(dev, i,