From patchwork Wed Nov 1 20:41:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1858075 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=K9hDeMuE; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SLJrL0VgCz1yQq for ; Thu, 2 Nov 2023 07:43:46 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyI2f-0002Ud-8U; Wed, 01 Nov 2023 16:42:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyI2c-0002U7-PY for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:18 -0400 Received: from mail-yb1-xb2c.google.com ([2607:f8b0:4864:20::b2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyI2a-0000bu-3x for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:18 -0400 Received: by mail-yb1-xb2c.google.com with SMTP id 3f1490d57ef6-d9ad67058fcso200095276.1 for ; Wed, 01 Nov 2023 13:42:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698871334; x=1699476134; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WZSLNse0I7cUlWTw/6OvUD8xc6YtkA+K7w7TUTv5SIE=; b=K9hDeMuEj3x/grQ/kEbpWwKZ6iEaOCg4JCq5eQF/VOX8DTNttwbSIwxLiHwtzwwxCc QMDFuFoOoBrMtQy9+XhyfDNCU5YN4gJPYhq8Kx97ZbDrIOasCIHlq9Ruo931SsqAjVKK B5dNLMk9qQ9tjkQhL3sqfdVItVS0bYq/USzFgW/tqALxLBvufdYTwr7mjpHs5NgN8WBx XVJLpdaEFx3K0lmziZRmlxMEvgH465Xgg1qSFzwTCLvcQMQ54HQetfyPjCnKta9Ai1j/ SwlyaxIjl9OvwZlF3eUMo3xoJAMcvNjdxBFHX6M5KNEAiXyl8EQ0OJgPXhNCRv+KwiLl s+RA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698871334; x=1699476134; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WZSLNse0I7cUlWTw/6OvUD8xc6YtkA+K7w7TUTv5SIE=; b=JmreFiQWXKIQ1Rvh+WSVqpS/Ff6+JSFrwmCCaTOWamLdqUTqg0EoTgJhKIRyQA5AnK EvGLa9wc5ZmDxTfawCEcu92nPmx/+p1LxsR9DvknStJY3WWYjYMH1uLZuZwPJ3v5HVH5 PlYokW8mHGw+agAKHYWGk26SKVl2OWOe6FVdSweG+SfT7b/eVFHIofl1h27rPki6KVE9 U7g43BcoGoBPTBrTg7xZRII2Ahn73l4AH/u1OL783QDw5NEJ0Dtv8QU9UHL3GbFBhwxx UHLq8G4ABKzz//j9juA5KPgJFBTIYEjEAvyzwdUUjHUTweXSM3xbCo+SDMQ+n2YofOYI wZcA== X-Gm-Message-State: AOJu0YyZwnxICVwkktX/x0YwtcIbAw13i6v+ke9fp2u/71bHaJf+ZHqd IMdV0maT3HFWrY++10ye8J6AnF0zjs0S9VdZjDA= X-Google-Smtp-Source: AGHT+IG+aMqdg3sfBQJUC9RZN//JdC1eN0l2mflXFs391BEDmmEtVHJlVLPIznkf7p18zpQwwMwxkQ== X-Received: by 2002:a25:bfc3:0:b0:da3:b5dd:d9 with SMTP id q3-20020a25bfc3000000b00da3b5dd00d9mr3040765ybm.39.1698871334264; Wed, 01 Nov 2023 13:42:14 -0700 (PDT) Received: from grind.. ([179.193.10.161]) by smtp.gmail.com with ESMTPSA id z187-20020a2533c4000000b00d9cc49edae9sm329724ybz.63.2023.11.01.13.42.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 13:42:13 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v8 01/19] target/riscv: create TYPE_RISCV_VENDOR_CPU Date: Wed, 1 Nov 2023 17:41:46 -0300 Message-ID: <20231101204204.345470-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231101204204.345470-1-dbarboza@ventanamicro.com> References: <20231101204204.345470-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::b2c; envelope-from=dbarboza@ventanamicro.com; helo=mail-yb1-xb2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We want to add a new CPU type for bare CPUs that will inherit specific traits of the 2 existing types: - it will allow for extensions to be enabled/disabled, like generic CPUs; - it will NOT inherit defaults, like vendor CPUs. We can make this conditions met by adding an explicit type for the existing vendor CPUs and change the existing logic to not imply that "not generic" means vendor CPUs. Let's add the "vendor" CPU type first. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 30 +++++++++++++++++++++--------- 2 files changed, 22 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index f3fbe37a2c..7831e86d37 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -24,6 +24,7 @@ #define TYPE_RISCV_CPU "riscv-cpu" #define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu" +#define TYPE_RISCV_VENDOR_CPU "riscv-vendor-cpu" #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f40da4c661..822970345c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1725,6 +1725,13 @@ void riscv_cpu_list(void) .instance_init = initfn \ } +#define DEFINE_VENDOR_CPU(type_name, initfn) \ + { \ + .name = type_name, \ + .parent = TYPE_RISCV_VENDOR_CPU, \ + .instance_init = initfn \ + } + static const TypeInfo riscv_cpu_type_infos[] = { { .name = TYPE_RISCV_CPU, @@ -1742,21 +1749,26 @@ static const TypeInfo riscv_cpu_type_infos[] = { .parent = TYPE_RISCV_CPU, .abstract = true, }, + { + .name = TYPE_RISCV_VENDOR_CPU, + .parent = TYPE_RISCV_CPU, + .abstract = true, + }, DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init), #if defined(TARGET_RISCV32) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), #elif defined(TARGET_RISCV64) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), #endif }; From patchwork Wed Nov 1 20:41:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1858083 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=MzCWMQRF; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SLJtM6p3cz1yQt for ; Thu, 2 Nov 2023 07:45:31 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyI2g-0002Vd-G4; Wed, 01 Nov 2023 16:42:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyI2e-0002V9-ME for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:20 -0400 Received: from mail-yb1-xb2a.google.com ([2607:f8b0:4864:20::b2a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyI2d-0000cd-5T for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:20 -0400 Received: by mail-yb1-xb2a.google.com with SMTP id 3f1490d57ef6-d9ac31cb051so189732276.3 for ; Wed, 01 Nov 2023 13:42:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698871337; x=1699476137; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OMuHLdrzcJQqp5mm/d7oE5DlJvLRfjtu2KHzBTuStOg=; b=MzCWMQRFsCpabOB5w/mXqNyKkK8BiDncAA3OmC9OrlFgJMY/uXM3B1Oj8VwpIts7PC py+gw1mwyWGyiIbC3TUP0YZGKA7btG/KJS2+q1ZUWWJ72L3de+NDjsA2tyI14L4Givw5 MBOUnNO3+wW5je7Vxrzeu43YAvuEg7d2LysHy8YFlyey9mwFJhhFTrV9tBh/YJecDl5Q O4Qjzl2RiQ9EOeI++yIrEj716Vsm9v9iRnpLqbUZH0gqvfJBDF13wbm8ZbRYxDz62DYg mtGyKeri/WfbAlnWBevVLNjOe25YSx17oHYC/j/gglzOlJ1Rc4P87iRp5rvN37sLYZA+ SsXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698871337; x=1699476137; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OMuHLdrzcJQqp5mm/d7oE5DlJvLRfjtu2KHzBTuStOg=; b=Bk/fdF72F94LvpIXYBP8xbjvAczncvVJ48pQK8jVXG47H4yfadKiLYqJJQ0ynYLhkh qdkEV2R2E5cjLU+DlTb1rxcRNZ+Nhi5T2owq4Pl/92jnF2i22NVr+IlNVypyO01tgbX1 bHrQMwm85q0CT+RcqS6t1dPPhlBWdPlj0WQwX7GkTAKNsz62xkPmGyPex4XQy9h571HA MI3MbBfZ1Z/hDBYGrwyCqz8Uch+gKSEE9miXCeUYIiaw8UXmfTnJ95JqO/bZ/pYJ61br PUasT4fr81VJlmKNUr2iekJRUsgh3NdVtWdr5DvwUDKSOmrf5upTVZQ8l5eOMINGO4s+ WSWQ== X-Gm-Message-State: AOJu0YzxzIQtWrpRCFJRBIIWgn4DLCf7wvhqn5MOPKiAbGCXEJdAoZZd IjJ75Ff//caxFae6oqH8oxHM/SxnZEG/d9ZCUZg= X-Google-Smtp-Source: AGHT+IHEFpL6Maqdx2qW+4ZPVO42RQXJj8TvMVKp1yyI2ZBB9UgDuSfGZS5/GqfxH8WUmkTBXEP0NQ== X-Received: by 2002:a25:824e:0:b0:da0:6179:95ac with SMTP id d14-20020a25824e000000b00da0617995acmr14409125ybn.48.1698871336813; Wed, 01 Nov 2023 13:42:16 -0700 (PDT) Received: from grind.. ([179.193.10.161]) by smtp.gmail.com with ESMTPSA id z187-20020a2533c4000000b00d9cc49edae9sm329724ybz.63.2023.11.01.13.42.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 13:42:16 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v8 02/19] target/riscv/tcg: do not use "!generic" CPU checks Date: Wed, 1 Nov 2023 17:41:47 -0300 Message-ID: <20231101204204.345470-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231101204204.345470-1-dbarboza@ventanamicro.com> References: <20231101204204.345470-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::b2a; envelope-from=dbarboza@ventanamicro.com; helo=mail-yb1-xb2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Our current logic in get/setters of MISA and multi-letter extensions works because we have only 2 CPU types, generic and vendor, and by using "!generic" we're implying that we're talking about vendor CPUs. When adding a third CPU type this logic will break so let's handle it beforehand. In set_misa_ext_cfg() and set_multi_ext_cfg(), check for "vendor" cpu instead of "not generic". The "generic CPU" checks remaining are from riscv_cpu_add_misa_properties() and cpu_add_multi_ext_prop() before applying default values for the extensions. This leaves us with: - vendor CPUs will not allow extension enablement, all other CPUs will; - generic CPUs will inherit default values for extensions, all others won't. And now we can add a new, third CPU type, that will allow extensions to be enabled and will not inherit defaults, without changing the existing logic. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 093bda2e75..f54069d06f 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -612,6 +612,11 @@ static bool riscv_cpu_is_generic(Object *cpu_obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; } +static bool riscv_cpu_is_vendor(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_VENDOR_CPU) != NULL; +} + /* * We'll get here via the following path: * @@ -674,7 +679,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, target_ulong misa_bit = misa_ext_cfg->misa_bit; RISCVCPU *cpu = RISCV_CPU(obj); CPURISCVState *env = &cpu->env; - bool generic_cpu = riscv_cpu_is_generic(obj); + bool vendor_cpu = riscv_cpu_is_vendor(obj); bool prev_val, value; if (!visit_type_bool(v, name, &value, errp)) { @@ -688,7 +693,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, } if (value) { - if (!generic_cpu) { + if (vendor_cpu) { g_autofree char *cpuname = riscv_cpu_get_name(cpu); error_setg(errp, "'%s' CPU does not allow enabling extensions", cpuname); @@ -793,7 +798,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, { const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; RISCVCPU *cpu = RISCV_CPU(obj); - bool generic_cpu = riscv_cpu_is_generic(obj); + bool vendor_cpu = riscv_cpu_is_vendor(obj); bool prev_val, value; if (!visit_type_bool(v, name, &value, errp)) { @@ -817,7 +822,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, return; } - if (value && !generic_cpu) { + if (value && vendor_cpu) { g_autofree char *cpuname = riscv_cpu_get_name(cpu); error_setg(errp, "'%s' CPU does not allow enabling extensions", cpuname); From patchwork Wed Nov 1 20:41:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1858079 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=TBKZWpSK; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SLJsx1cqTz1yQq for ; Thu, 2 Nov 2023 07:45:09 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyI2i-0002WZ-G4; Wed, 01 Nov 2023 16:42:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyI2g-0002W0-OX for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:22 -0400 Received: from mail-yb1-xb33.google.com ([2607:f8b0:4864:20::b33]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyI2f-0000e7-8q for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:22 -0400 Received: by mail-yb1-xb33.google.com with SMTP id 3f1490d57ef6-d9ca471cf3aso190269276.2 for ; Wed, 01 Nov 2023 13:42:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698871339; x=1699476139; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1QqMbaZ9ZTHkQg0Yfq1IBFSzq4QoXF5VtwzSAbraCcY=; b=TBKZWpSKZ/2tRV56wnsiIpk3O8WrrGZEG/psruqKUoIuQlIvtPF4UoKZ1LeMLZeu9t t5e5eneq790lIJ1Xp/tTFOMSr/BcTU6KOeBNFAJp22hBidkawnNzqoc3IAjam9d+yGY3 RMctnYyN+Cl+q+iFlP/V4AIfENXV6IAppeNbdoPPPkF/+XdS/lFpk23ryDaFXHaLfvgz SA+FvaneScnDVKYBgivnwJtb7P3JIQf3EBfgFLtKdLxQnV796GprkBwPNArBJp8VxYzR 8dskGPRS6At1P2L2TgCPdfoeC1sZdYJy8WaOdcdJP19NT9xIYZQuo4rhwD0hJ63N7+cn fmyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698871339; x=1699476139; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1QqMbaZ9ZTHkQg0Yfq1IBFSzq4QoXF5VtwzSAbraCcY=; b=VJIZMaVOmKGO0hSRMAyqzbF8fUwApAayjOsZRcNudBHQRxxrktiHODCNNSQHbgUXYG S3uBenZcSdjSo1FkFAudzIrw0499TnZkQPdgXpO41vmvo/ipS2FlZ43RFRsS9A3xdn5M wYBOQz1pEE9CvhhoZlVWxUduP1XVVf0VMyMJM3Hbpti25kaBRNQcKxL2I1VW08ejG1ao WkjhEZsAi12ivY/iTUGV/BGxxCNqUg0wyHVVtEDvX+JpGRxYG1zQhTAEZxhkKgAVZ2jX HZPMGSIxBynK5vyRl7eNbJTKhi9jlZ3Gh1yURRMsJRG6KJld4CUtUInYjORNTlvAqaS1 5SDw== X-Gm-Message-State: AOJu0YxPNLufMCxD4RsiIWEkJOR2Hm35A5fCu8hKBw6JjDFdRoTpjuvr 4q4FMTzWcmGtcUWeC9rRa+ACTfPEG7tHYGvSTH4= X-Google-Smtp-Source: AGHT+IH9fe2t8SSf/H4HLOw+H0lQ+HMp2715ocMS6i4YTuxuFF71lF6GlcQ4C4G8B+H+4kIcsm74mA== X-Received: by 2002:a25:ae11:0:b0:da3:9565:635a with SMTP id a17-20020a25ae11000000b00da39565635amr5611851ybj.56.1698871339374; Wed, 01 Nov 2023 13:42:19 -0700 (PDT) Received: from grind.. ([179.193.10.161]) by smtp.gmail.com with ESMTPSA id z187-20020a2533c4000000b00d9cc49edae9sm329724ybz.63.2023.11.01.13.42.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 13:42:19 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v8 03/19] target/riscv/cpu.c: set satp_max_supported in cpu_riscv_set_satp() Date: Wed, 1 Nov 2023 17:41:48 -0300 Message-ID: <20231101204204.345470-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231101204204.345470-1-dbarboza@ventanamicro.com> References: <20231101204204.345470-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::b33; envelope-from=dbarboza@ventanamicro.com; helo=mail-yb1-xb33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The setter() for the boolean attributes that set satp_mode (sv32, sv39, sv48, sv57, sv64) considers that the CPU will always do a set_satp_mode_max_supported() during cpu_init(). This is not the case for the KVM 'host' CPU, and we'll add another CPU that won't set satp_mode_max() during cpu_init(). Users should be able to set a max_support in these circunstances. Allow cpu_riscv_set_satp() to set satp_mode_max_supported if the CPU didn't set one prior. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 822970345c..9f6837ecb7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1100,6 +1100,7 @@ static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { + RISCVCPU *cpu = RISCV_CPU(obj); RISCVSATPMap *satp_map = opaque; uint8_t satp = satp_mode_from_str(name); bool value; @@ -1108,6 +1109,16 @@ static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, return; } + /* + * Allow users to set satp max supported if the CPU didn't + * set any during cpu_init(). First value set to 'true' + * in this case is assumed to be the max supported for + * the CPU. + */ + if (value && cpu->cfg.satp_mode.supported == 0) { + set_satp_mode_max_supported(cpu, satp); + } + satp_map->map = deposit32(satp_map->map, satp, 1, value); satp_map->init |= 1 << satp; } From patchwork Wed Nov 1 20:41:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1858071 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=pU8H5I/c; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SLJqk2f9Yz1yQq for ; Thu, 2 Nov 2023 07:43:12 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyI2k-0002Zz-8z; Wed, 01 Nov 2023 16:42:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyI2j-0002YC-1w for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:25 -0400 Received: from mail-yb1-xb2e.google.com ([2607:f8b0:4864:20::b2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyI2h-0000f2-L5 for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:24 -0400 Received: by mail-yb1-xb2e.google.com with SMTP id 3f1490d57ef6-d9c7bba32beso199282276.1 for ; Wed, 01 Nov 2023 13:42:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698871342; x=1699476142; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/A81MfmHSii2g9wXL7wLzUzIse0LpnaxjmFzQl496fY=; b=pU8H5I/cgMSAplIt403QlmJSX4KVNx4nOhtGxDqM2MnRwm9qg4oax8L0ZKMrDzUuH3 ShTo4MhNidIgzlXISx7QiHnNk3Yyi9cjOdi5GgSrRIoapKHZ4f/GdM4RC9Mx1NQ+cMFz PmGITvr1am6uxIJWp+KB7Q1TPoXe7f24g3OcSzM6Mz2yNvVsG396JeXIgzwDlGjWZgY1 NIPWZOe2nU2ejnyVaPuRDsOZKt1Dyu62DzTv80RNkU5p24embTDrMYzcLDgt4Xm5uPot 6hE0RCoAnx01lH8ZMr3E+8FAyzuXoT/cbRuNUCfCgmRiop0tZP59Lsmilbz3JOazVJ/z 1Qmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698871342; x=1699476142; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/A81MfmHSii2g9wXL7wLzUzIse0LpnaxjmFzQl496fY=; b=XVJNNhEqPFdbSGWx1QR888yzuCqePqM4+ohhV60n5xMZqBahIeY5gnDXmIXLiiP9aM ycxpWluVK1VO2qLs60EFu83ULG4DEWI3IDNq5uSw4wbWto42NEevMliksjc2XqJ047ag qnQ+yfesMsLsAl1x7zH5vtJhH+apzhHtvit9YE7swWvYMTqPCnDdwBmbRQoWbrloBV7J thbCCyqxSbP8MdxS86y6gB0J2yvjx9yhA2761Qc77oh8ufKnK4btum8ssevvqZAJUNzi reCqLb8avGIlUCipm2zVpToBuvoIofDBTGiD+FJ4LLEZGM7AhP9yCtsB3h0V5/nGRVGs 6AuA== X-Gm-Message-State: AOJu0YxLLMbUTKrJaeB2XoCH5Tn2SCb7Hgy93/V4UbAv6Y/8fU5sgHON lbbiQsMbuE3lNflL7idS5Dj1DJusGC4uYCG0of4= X-Google-Smtp-Source: AGHT+IENqMhtKJdqSEYs5OQBjapzS6n0sc4WcNofbV17gAyS5L5sqDD7cdKSqf9DsiA4g+fufbRkHw== X-Received: by 2002:a25:d7cb:0:b0:da0:4aaa:b480 with SMTP id o194-20020a25d7cb000000b00da04aaab480mr18248956ybg.19.1698871341974; Wed, 01 Nov 2023 13:42:21 -0700 (PDT) Received: from grind.. ([179.193.10.161]) by smtp.gmail.com with ESMTPSA id z187-20020a2533c4000000b00d9cc49edae9sm329724ybz.63.2023.11.01.13.42.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 13:42:21 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v8 04/19] target/riscv/cpu.c: set satp_mode_max MBARE during satp_finalize() Date: Wed, 1 Nov 2023 17:41:49 -0300 Message-ID: <20231101204204.345470-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231101204204.345470-1-dbarboza@ventanamicro.com> References: <20231101204204.345470-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::b2e; envelope-from=dbarboza@ventanamicro.com; helo=mail-yb1-xb2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org KVM CPUs can handle "cpu->cfg.satp_mode.supported == 0" because KVM will make it do internally, not requiring the current SATP support from TCG. But other TCG CPUs doesn't deal well with it. We'll assert out before OpenSBI if the CPU doesn't set a default: ERROR:../target/riscv/cpu.c:317:satp_mode_max_from_map: assertion failed: (map > 0) Bail out! ERROR:../target/riscv/cpu.c:317:satp_mode_max_from_map: assertion failed: (map > 0) This will be thrown by target/riscv/csr.c, write_satp(), when stepping in validate_vm(). There's no current CPUs affected by it, but next patch will add a new CPU that doesn't have defaults and this assert will be hit. Change riscv_cpu_satp_mode_finalize() to set satp_mode_max_supported() to MBARE if the CPU happens to not have a max mode set yet. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9f6837ecb7..f7c1989d14 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -942,9 +942,19 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; uint8_t satp_mode_map_max, satp_mode_supported_max; - /* The CPU wants the OS to decide which satp mode to use */ if (cpu->cfg.satp_mode.supported == 0) { - return; + if (kvm_enabled()) { + /* The CPU wants the OS to decide which satp mode to use */ + return; + } + + /* + * We do not handle cpu->cfg.satp_mode.supported == 0 + * with TCG yet. Set to MBARE. + */ + if (tcg_enabled()) { + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); + } } satp_mode_supported_max = From patchwork Wed Nov 1 20:41:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1858087 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=bNOBN0rv; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SLJvJ6dvqz1yQ5 for ; Thu, 2 Nov 2023 07:46:20 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyI2n-0002be-2t; Wed, 01 Nov 2023 16:42:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyI2l-0002aF-4Q for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:27 -0400 Received: from mail-yb1-xb2c.google.com ([2607:f8b0:4864:20::b2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyI2j-0000fb-Nx for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:26 -0400 Received: by mail-yb1-xb2c.google.com with SMTP id 3f1490d57ef6-da30fd994fdso1228130276.1 for ; Wed, 01 Nov 2023 13:42:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698871344; x=1699476144; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K359glfS+eWj+oJdfLPBDj+kA+tlcXin2KqqlCog67k=; b=bNOBN0rvW8uYp0SCGSP4L1fpbV46T4UdPYVnvDtCa/1HI0qXfdao1gh/NKaYorgUJ+ TiBlok7N1UKbn9y+rB5bOYRovCF6zuaVF2c0Z2b9MJmyheGEtBBie7YXNfdPK2FaPAt6 U8Wj6yir4yoH1oQMTlq+ijevBQ7jac8rs549hyXLabIDgn9thPWClFf5u6kdEgJGksbT helnh+390EKBf/2GkcaMP6AsL0fFo9+KBlg8vJP3ZSTBMlRbz3NaZFnbPNiltBoEjYuy 5fTMeCwnvL7Qib1+0lYDvf3mpoxjcsVHdh5zOiq6e3Gmyq6OjPQSfiYBBaLqiEXI4mGZ IVNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698871344; x=1699476144; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K359glfS+eWj+oJdfLPBDj+kA+tlcXin2KqqlCog67k=; b=uEOJpAKeXFmzozioktOhlaWxM8D5pEzBvCUET4RBQTwEdkJm9s3oWyJi6k6MulruU6 b+Tb+fiffV7aLFrn/YPBXajaNLzdU6rpEA+3WBIB1B3MedhPKWBn2Shv8iRI0tIdwkHa bEltndR/Ap9SADy+FrTUendoCtOmBbzwgYOHagFHRqVeVMNt6l4g5uAVY5t/c1zHkxsr F0yQVHVG3jV1CoWuJbJVB3zi7XGdFjWYB11ulRy51YxaU59HyP9KaNgBlrTUr6MS2VVd gYptlcgepl/Zi+ypSwBuQ2HK5GJcSKw9vAZOOR1IXUmIZ0OFYexmaQMcfJwPK2NX4744 1NGg== X-Gm-Message-State: AOJu0YxRivONXBvlOYTvYgpLAjPLkign9k6STPRGX8I/L13vTELYt2Ds avmt6015/pfRGWBxCBHzGI6A/a+KDmPpO8R5Q+U= X-Google-Smtp-Source: AGHT+IFz2TU4fY5iZqim2D9+BtH8nAONPfcCnzWdqTID5y4fWpbZJOa35SBvwIIR5okz2y8W9IHUOg== X-Received: by 2002:a25:328f:0:b0:da0:3e30:49bd with SMTP id y137-20020a25328f000000b00da03e3049bdmr5592771yby.24.1698871344515; Wed, 01 Nov 2023 13:42:24 -0700 (PDT) Received: from grind.. ([179.193.10.161]) by smtp.gmail.com with ESMTPSA id z187-20020a2533c4000000b00d9cc49edae9sm329724ybz.63.2023.11.01.13.42.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 13:42:24 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v8 05/19] target/riscv/tcg: update priv_ver on user_set extensions Date: Wed, 1 Nov 2023 17:41:50 -0300 Message-ID: <20231101204204.345470-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231101204204.345470-1-dbarboza@ventanamicro.com> References: <20231101204204.345470-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::b2c; envelope-from=dbarboza@ventanamicro.com; helo=mail-yb1-xb2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We'll add a new bare CPU type that won't have any default priv_ver. This means that the CPU will default to priv_ver = 0, i.e. 1.10.0. At the same we'll allow these CPUs to enable extensions at will, but then, if the extension has a priv_ver newer than 1.10, we'll end up disabling it. Users will then need to manually set priv_ver to something other than 1.10 to enable the extensions they want, which is not ideal. Change the setter() of multi letter extensions to allow user enabled extensions to bump the priv_ver of the CPU. This will make it conveniente for users to enable extensions for CPUs that doesn't set a default priv_ver. This change does not affect any existing CPU: vendor CPUs does not allow extensions to be enabled, and generic CPUs are already set to priv_ver LATEST. Signed-off-by: Daniel Henrique Barboza --- target/riscv/tcg/tcg-cpu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f54069d06f..b88fce98a4 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -114,6 +114,22 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) g_assert_not_reached(); } +static void cpu_validate_multi_ext_priv_ver(CPURISCVState *env, + uint32_t ext_offset) +{ + int ext_priv_ver; + + if (env->priv_ver == PRIV_VERSION_LATEST) { + return; + } + + ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset); + + if (env->priv_ver < ext_priv_ver) { + env->priv_ver = ext_priv_ver; + } +} + static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, bool value) { @@ -829,6 +845,10 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, return; } + if (value) { + cpu_validate_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); + } + isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); } From patchwork Wed Nov 1 20:41:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1858081 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=UPRuMU7f; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SLJt325RXz1yQ5 for ; Thu, 2 Nov 2023 07:45:15 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyI2p-0002dA-NS; Wed, 01 Nov 2023 16:42:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyI2o-0002c8-DU for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:30 -0400 Received: from mail-yb1-xb2f.google.com ([2607:f8b0:4864:20::b2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyI2m-0000gL-Nq for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:30 -0400 Received: by mail-yb1-xb2f.google.com with SMTP id 3f1490d57ef6-d84f18e908aso202559276.1 for ; Wed, 01 Nov 2023 13:42:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698871347; x=1699476147; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=j19jADic7A42loDpy3Do/I7i0K00Zw+KuiH/I8hQZA0=; b=UPRuMU7frfnFIB5q0yykTBjkrFHlRB4srFuCjiO7J+PWWZz04RIvxG5usbUDC+vvW0 kygN/CXUwYFCgAyUiryos6gjAit6Tf0vkXhy0qo60GzH3GkwZJat3GeCHwE2hqB3wsKk Ba3XlGjDJTsLzLoL4ns6JuGVd0/gjkPEQ+F5otpouk2jyxkJ3kUWXVh3N2W5iQtjNptB VIAlA7bwqdSuwmE+MYf59Bw3RZe54OzI7O1YzYZNvmx9BTx1fxFbbO/p4KbMM5hhRCkJ GFG3yn5F0F6bH3gcT9vronYXBtsbo58kLCaHiGmOKscIa7kjdNEaVCdwK3ZylDD4sJEK c+yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698871347; x=1699476147; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j19jADic7A42loDpy3Do/I7i0K00Zw+KuiH/I8hQZA0=; b=MRtpK34Ci52XlAF6o1/r+X+XArdUqn4bAyv0LUPp/VRmyPai/75Z/VqSrQ087a4ss3 vIHWSHRpaturlEDd+uJJCcjBfc8LXsmqzKuTRweeFsxxQjNnJxt8VUu99aCsDSt73imP L6BtmBAXzQ6g27tQVQzc9TfHIlykecvrXyBI8IcaTD57zmCk2l5xUGNF6wf2c1uV8g7P so5ojB0kmPG0++HnbK8lJCNhDRvXFQEP9mA5PlnPelz1fiZ7cxBEUyddruvqFDMz+Ul3 n0JN5SbfTqk/pM5cqz+VtShwmtT5dXdrPYpsrtB9hHGMCLs0NqjMdrvLC5OtJySERdLP Do9w== X-Gm-Message-State: AOJu0YyeeHR8bLmWBEk50TUCkbFrEXdGFjyLq+GA6UTmzGmzH4nttcua k3e+sOh+HhWyHHp20mzxCxIPA9JkaRK1qX7BN9o= X-Google-Smtp-Source: AGHT+IFo4DPM+BkNWUgLkSfYzQtw7WVkwZpm04b9ycsjS6ZkiUkxHabhF19oIEYVkgM3Ymef4OIgtw== X-Received: by 2002:a25:aa85:0:b0:d9a:5244:32e5 with SMTP id t5-20020a25aa85000000b00d9a524432e5mr18212118ybi.35.1698871347101; Wed, 01 Nov 2023 13:42:27 -0700 (PDT) Received: from grind.. ([179.193.10.161]) by smtp.gmail.com with ESMTPSA id z187-20020a2533c4000000b00d9cc49edae9sm329724ybz.63.2023.11.01.13.42.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 13:42:26 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v8 06/19] target/riscv: add rv64i CPU Date: Wed, 1 Nov 2023 17:41:51 -0300 Message-ID: <20231101204204.345470-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231101204204.345470-1-dbarboza@ventanamicro.com> References: <20231101204204.345470-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::b2f; envelope-from=dbarboza@ventanamicro.com; helo=mail-yb1-xb2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We don't have any form of a 'bare bones' CPU. rv64, our default CPUs, comes with a lot of defaults. This is fine for most regular uses but it's not suitable when more control of what is actually loaded in the CPU is required. A bare-bones CPU would be annoying to deal with if not by profile support, a way to load a multitude of extensions with a single flag. Profile support is going to be implemented shortly, so let's add a CPU for it. The new 'rv64i' CPU will have only RVI loaded. It is inspired in the profile specification that dictates, for RVA22U64 [1]: "RVA22U64 Mandatory Base RV64I is the mandatory base ISA for RVA22U64" And so it seems that RV64I is the mandatory base ISA for all profiles listed in [1], making it an ideal CPU to use with profile support. rv64i is a CPU of type TYPE_RISCV_BARE_CPU. It has a mix of features from pre-existent CPUs: - it allows extensions to be enabled, like generic CPUs; - it will not inherit extension defaults, like vendor CPUs. This is the minimum extension set to boot OpenSBI and buildroot using rv64i: ./build/qemu-system-riscv64 -nographic -M virt \ -cpu rv64i,sv39=true,g=true,c=true,s=true,u=true Our minimal riscv,isa in this case will be: # cat /proc/device-tree/cpus/cpu@0/riscv,isa rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd# [1] https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/cpu-qom.h | 2 ++ target/riscv/cpu.c | 23 +++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 7831e86d37..ea9a752280 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -25,6 +25,7 @@ #define TYPE_RISCV_CPU "riscv-cpu" #define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu" #define TYPE_RISCV_VENDOR_CPU "riscv-vendor-cpu" +#define TYPE_RISCV_BARE_CPU "riscv-bare-cpu" #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) @@ -35,6 +36,7 @@ #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") +#define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f7c1989d14..4a6e544eaf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -544,6 +544,16 @@ static void rv128_base_cpu_init(Object *obj) set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif } + +static void rv64i_bare_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + riscv_cpu_set_misa(env, MXL_RV64, RVI); + + /* Remove the defaults from the parent class */ + RISCV_CPU(obj)->cfg.ext_zicntr = false; + RISCV_CPU(obj)->cfg.ext_zihpm = false; +} #else static void rv32_base_cpu_init(Object *obj) { @@ -1753,6 +1763,13 @@ void riscv_cpu_list(void) .instance_init = initfn \ } +#define DEFINE_BARE_CPU(type_name, initfn) \ + { \ + .name = type_name, \ + .parent = TYPE_RISCV_BARE_CPU, \ + .instance_init = initfn \ + } + static const TypeInfo riscv_cpu_type_infos[] = { { .name = TYPE_RISCV_CPU, @@ -1775,6 +1792,11 @@ static const TypeInfo riscv_cpu_type_infos[] = { .parent = TYPE_RISCV_CPU, .abstract = true, }, + { + .name = TYPE_RISCV_BARE_CPU, + .parent = TYPE_RISCV_CPU, + .abstract = true, + }, DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init), #if defined(TARGET_RISCV32) @@ -1791,6 +1813,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), + DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init), #endif }; From patchwork Wed Nov 1 20:41:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1858076 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=XRr8wz2p; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SLJrT6s6nz1yQq for ; Thu, 2 Nov 2023 07:43:53 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyI2t-0002hG-Mt; Wed, 01 Nov 2023 16:42:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyI2r-0002eh-U2 for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:33 -0400 Received: from mail-yb1-xb32.google.com ([2607:f8b0:4864:20::b32]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyI2p-0000gr-Hr for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:33 -0400 Received: by mail-yb1-xb32.google.com with SMTP id 3f1490d57ef6-d81d09d883dso216368276.0 for ; Wed, 01 Nov 2023 13:42:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698871350; x=1699476150; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NT0jvyKzdtzF9zQdRLgFLjwKag0HYamRR1hXbSBg0xk=; b=XRr8wz2pkuuEqhfS0PnBZ/5UziZLP05GuwppteAG38lb0mbhL6D9NBJQlceiOIQnaN uz60n0XsxhcIOPwb2B0G/q2y0WxdQ5T6Uu2F3u+cooguW7ClCmH5J0FYyADk4euaB43r kz6iDAld2CRtNJyP6UeSjvvpNER79AtqDpAGaYTEzFANL25CCcy745UdvvsNRIZVi0qL i39n/FOBN7CY1DtHvcr4EHDgfoCa8KpXywvvSNUMCFintQZJW9EVnzdc4FufTpcNL0Xl 0wAp2TxsUCnzak2HYlhV9J0s4F50rOqTZhOiOVpCfQLUlhxgJEU85Q5dhXo6i6y0JgAh 1LLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698871350; x=1699476150; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NT0jvyKzdtzF9zQdRLgFLjwKag0HYamRR1hXbSBg0xk=; b=AlAK7h1erk/L2EZS2YpvHpQWoOw/nFXLZJIw0aKmIMp8bxyvQbLqRbRkCGZPSttlXY A5+0YI/q38pVzEwzVY10gTh1eiTjip6ErNbNqqbyPmjbu2bVULw9Sl3aaOpXfR5aaxXh pV5DsnT27GtyX/fq9Piy/Q86/n2x3/Oxln+m8kclfczpJa7N5+23glVFLDtblP0cVrIL H0hng3X3+McTHOLgvvjxYIpEThFtfyxn+7WwLuaL54riNWBUJd8xcwskibdMnT0Oup/i 0fNYkeG8nDHXzG0SO4GoZzrGW2uCtf/cNaIWJGvgfFAuJcw9ILVY6aPAbd7ZQJrAj9De xidw== X-Gm-Message-State: AOJu0Yz/31pAaHPacG+217n8FfihEbDDdg63G8jbZd+kARTs2/cAMAc9 CPe589Ik8hCXmJzqFvevSzWNYyDb3eUegwEIdoQ= X-Google-Smtp-Source: AGHT+IGWGcMrKuISnXoWKNcUhrKLPFqdZ/neMYhsvWnay7aSYaajAw695Ea3UzYq4W3dx1peAcJcBA== X-Received: by 2002:a25:7806:0:b0:da0:d0be:ef06 with SMTP id t6-20020a257806000000b00da0d0beef06mr11206622ybc.51.1698871349865; Wed, 01 Nov 2023 13:42:29 -0700 (PDT) Received: from grind.. ([179.193.10.161]) by smtp.gmail.com with ESMTPSA id z187-20020a2533c4000000b00d9cc49edae9sm329724ybz.63.2023.11.01.13.42.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 13:42:29 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v8 07/19] target/riscv: add zicbop extension flag Date: Wed, 1 Nov 2023 17:41:52 -0300 Message-ID: <20231101204204.345470-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231101204204.345470-1-dbarboza@ventanamicro.com> References: <20231101204204.345470-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::b32; envelope-from=dbarboza@ventanamicro.com; helo=mail-yb1-xb32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org QEMU already implements zicbom (Cache Block Management Operations) and zicboz (Cache Block Zero Operations). Commit 59cb29d6a5 ("target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder") added placeholders for what would be the instructions for zicbop (Cache Block Prefetch Operations), which are now no-ops. The RVA22U64 profile mandates zicbop, which means that applications that run with this profile might expect zicbop to be present in the riscv,isa DT and might behave badly if it's absent. Adding zicbop as an extension will make our future RVA22U64 implementation more in line with what userspace expects and, if/when cache block prefetch operations became relevant to QEMU, we already have the extension flag to turn then on/off as needed. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- hw/riscv/virt.c | 5 +++++ target/riscv/cpu.c | 3 +++ target/riscv/cpu_cfg.h | 2 ++ 3 files changed, 10 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 1732c42915..99c087240f 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -273,6 +273,11 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, cpu_ptr->cfg.cboz_blocksize); } + if (cpu_ptr->cfg.ext_zicbop) { + qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-size", + cpu_ptr->cfg.cbop_blocksize); + } + qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4a6e544eaf..92807f5324 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -78,6 +78,7 @@ const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV, */ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom), + ISA_EXT_DATA_ENTRY(zicbop, PRIV_VERSION_1_12_0, ext_zicbop), ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_zicboz), ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_zicntr), @@ -1367,6 +1368,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false), MULTI_EXT_CFG_BOOL("zicbom", ext_zicbom, true), + MULTI_EXT_CFG_BOOL("zicbop", ext_zicbop, true), MULTI_EXT_CFG_BOOL("zicboz", ext_zicboz, true), MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false), @@ -1455,6 +1457,7 @@ Property riscv_cpu_options[] = { DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), + DEFINE_PROP_UINT16("cbop_blocksize", RISCVCPU, cfg.cbop_blocksize, 64), DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), DEFINE_PROP_END_OF_LIST(), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 6eef4a51ea..2203b4c45b 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -65,6 +65,7 @@ struct RISCVCPUConfig { bool ext_zicntr; bool ext_zicsr; bool ext_zicbom; + bool ext_zicbop; bool ext_zicboz; bool ext_zicond; bool ext_zihintntl; @@ -134,6 +135,7 @@ struct RISCVCPUConfig { uint16_t vlen; uint16_t elen; uint16_t cbom_blocksize; + uint16_t cbop_blocksize; uint16_t cboz_blocksize; bool mmu; bool pmp; From patchwork Wed Nov 1 20:41:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1858095 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=RMfUug+/; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SLJwD3lcCz1yQ5 for ; Thu, 2 Nov 2023 07:47:08 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyI2v-0002iT-Vh; Wed, 01 Nov 2023 16:42:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyI2t-0002hT-NQ for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:35 -0400 Received: from mail-yb1-xb32.google.com ([2607:f8b0:4864:20::b32]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyI2s-0000hO-0o for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:35 -0400 Received: by mail-yb1-xb32.google.com with SMTP id 3f1490d57ef6-da37522a363so214484276.0 for ; Wed, 01 Nov 2023 13:42:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698871352; x=1699476152; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vg8TWqLJuWdWqnDA43cqj104JxPxDzhD4xhOykP5PPE=; b=RMfUug+/Rc0/6/3Pg0oYmuR7znHjtxTWyAb7OgUvdJbb98W81xQY0n6NxoKErfyzZY cvEWKP6ocxCKARRDkNSxpja8G9L3HzmPaWnl20fNNdDQue63uAze5m3C45vrke+1A8oK yTpR1v940KKHpFelAa4JDmPCinIJcEG2GOC0tTtscN44zbWIsERzquBJHe2ezDzPY9pa SmqazwxC/UvIm6PjKxnPBiXU0hTTQYeBvASJu/8Ap12u/sF9CUOghM7x4cHtLNHiqAZe m1UmssslSkOrqzwPvAtfhGOBJDHkdhd5CqUQ0yu+GcjITtffUPQTWeSO3PzG1AD/0AXt 7zPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698871352; x=1699476152; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vg8TWqLJuWdWqnDA43cqj104JxPxDzhD4xhOykP5PPE=; b=FUuXd5LU+10fNoyCpdddcZwZ1cWM95A5RtJHiTqdzrO+EK5Rkd4cB0r2GNgtGbdyiP xBWOqJh9rEB5NarGAltw0FUOeKsTMpNwIwKlToYI9JdJu0NDfHcAbuPI5BfgVIHlFUxE 0F+UsdfSgL/ZqhXlumOvhk5eK/kzLu9k5LPTSPSvdw7FTO1NzwS3CQxsHITnhQkRhE9y 7MxevrHWlQ0a7Tg5IA9x65fXWDFreOIhYaN6K9Fl4Y+72545+dzv+Up0hJyB4Bm0mrVB n4/LfVtB88m58uwrKszscpeByKM6Kh+3AFL9dVgqf03uyn9dDNDlQzsirX+ylDvND4S1 cmvA== X-Gm-Message-State: AOJu0YxATu+7miMEMHCN3BySPYwYXUqpfCvZvRqfi8Rd/wsHnilNJSZM IKgCRmGT6+HZyHKpISfI/zM9aP4mXv+SX2G9l00= X-Google-Smtp-Source: AGHT+IHlDhuyzYBRLlmjEsIqdTP1KCHApUVLjBaOnEhjOo/hkbPM+TA6nH0bXdF2I7m6oHeXCDlwOA== X-Received: by 2002:a25:aaae:0:b0:d9a:5666:7ab5 with SMTP id t43-20020a25aaae000000b00d9a56667ab5mr18039594ybi.10.1698871352399; Wed, 01 Nov 2023 13:42:32 -0700 (PDT) Received: from grind.. ([179.193.10.161]) by smtp.gmail.com with ESMTPSA id z187-20020a2533c4000000b00d9cc49edae9sm329724ybz.63.2023.11.01.13.42.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 13:42:32 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v8 08/19] target/riscv/tcg: add 'zic64b' support Date: Wed, 1 Nov 2023 17:41:53 -0300 Message-ID: <20231101204204.345470-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231101204204.345470-1-dbarboza@ventanamicro.com> References: <20231101204204.345470-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::b32; envelope-from=dbarboza@ventanamicro.com; helo=mail-yb1-xb32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org zic64b is defined in the RVA22U64 profile [1] as a named feature for "Cache blocks must be 64 bytes in size, naturally aligned in the address space". It's a fantasy name for 64 bytes cache blocks. The RVA22U64 profile mandates this feature, meaning that applications using this profile expects 64 bytes cache blocks. To make the upcoming RVA22U64 implementation complete, we'll zic64b as a 'named feature', not a regular extension. This means that: - it won't be exposed to users; - it won't be written in riscv,isa. This will be extended to other named extensions in the future, so we're creating some common boilerplate for them as well. zic64b is default to 'true' since we're already using 64 bytes blocks. If any cache block size (cbo{m,p,z}_blocksize) is changed to something different than 64, zic64b is set to 'false'. Our profile implementation will then be able to check the current state of zic64b and take the appropriate action (e.g. throw a warning). [1] https://github.com/riscv/riscv-profiles/releases/download/v1.0/profiles.pdf Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 6 ++++++ target/riscv/cpu.h | 1 + target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 31 +++++++++++++++++++++++++++++++ 4 files changed, 39 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 92807f5324..c7c09c1f7c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1427,6 +1427,12 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { DEFINE_PROP_END_OF_LIST(), }; +const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = { + MULTI_EXT_CFG_BOOL("zic64b", zic64b, true), + + DEFINE_PROP_END_OF_LIST(), +}; + /* Deprecated entries marked for future removal */ const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = { MULTI_EXT_CFG_BOOL("Zifencei", ext_zifencei, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8efc4d83ec..bf12f34082 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -745,6 +745,7 @@ typedef struct RISCVCPUMultiExtConfig { extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; +extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[]; extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[]; extern Property riscv_cpu_options[]; diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 2203b4c45b..f61a8434c4 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -108,6 +108,7 @@ struct RISCVCPUConfig { bool ext_smepmp; bool rvv_ta_all_1s; bool rvv_ma_all_1s; + bool zic64b; uint32_t mvendorid; uint64_t marchid; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index b88fce98a4..a577cd795a 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -114,6 +114,19 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) g_assert_not_reached(); } +static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) +{ + const RISCVCPUMultiExtConfig *feat; + + for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { + if (feat->offset == ext_offset) { + return true; + } + } + + return false; +} + static void cpu_validate_multi_ext_priv_ver(CPURISCVState *env, uint32_t ext_offset) { @@ -123,6 +136,10 @@ static void cpu_validate_multi_ext_priv_ver(CPURISCVState *env, return; } + if (cpu_cfg_offset_is_named_feat(ext_offset)) { + return; + } + ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset); if (env->priv_ver < ext_priv_ver) { @@ -280,6 +297,18 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) } } +static void riscv_cpu_validate_zic64b(RISCVCPU *cpu) +{ + cpu->cfg.zic64b = cpu->cfg.cbom_blocksize == 64 && + cpu->cfg.cbop_blocksize == 64 && + cpu->cfg.cboz_blocksize == 64; +} + +static void riscv_cpu_validate_named_features(RISCVCPU *cpu) +{ + riscv_cpu_validate_zic64b(cpu); +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. @@ -602,6 +631,8 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) return; } + riscv_cpu_validate_named_features(cpu); + if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available From patchwork Wed Nov 1 20:41:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1858085 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=NdaMsRw2; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SLJtM5yVRz1yQ5 for ; Thu, 2 Nov 2023 07:45:31 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyI2x-0002jF-Sd; Wed, 01 Nov 2023 16:42:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyI2w-0002ib-AI for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:38 -0400 Received: from mail-yb1-xb2c.google.com ([2607:f8b0:4864:20::b2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyI2u-0000jP-Ph for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:38 -0400 Received: by mail-yb1-xb2c.google.com with SMTP id 3f1490d57ef6-d9ad67058fcso200464276.1 for ; Wed, 01 Nov 2023 13:42:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698871355; x=1699476155; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W9vkQpTeB3ayrchqiqPL77Nx2STXCsE/ldIKYWZcyJE=; b=NdaMsRw2ASRTVgM7N+2cxRZCtYtdWQr374oxYlLI/sERlaqSKUS2Fbs+s+tjk/wNiS KEuZyePFwTcH9Weq/GoSYRePenUFlHirjMqjbEFrOpM99Ci9uehmamv4PMYZWwnJezGa joStAxWaHGSwNaOe32eRYBK+AY4tWNNJc/ZB6w1icXYVG3tB3ooabhcuv9CGOQEiK3SC ua4qokUGyZRw1vr/jAWPocanntgrgZYMRnh5tBTNnTdbt4nO90JvxGbVW9UpLrdJHtle bw2/NaekxGHbdDiblrEwR2NniTZpkBqfP+b0MX+u5oCiC7tfciaAusmOQCki4qRz30pF 61JQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698871355; x=1699476155; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W9vkQpTeB3ayrchqiqPL77Nx2STXCsE/ldIKYWZcyJE=; b=NLop4J5V9oam9KFoFeFRYyNjwkC0awsW+OsMnhyg2jypKLmkdPm4ADeUf0orMEqlSz PI7Sw8BbP4q53CQCv2j3OxCi6hZeZS5Rfi+MV04jxYzZxsVAtov+8ungKkDzR2cbZsYc o9jLGtdE7VJXJrIlcc5f5CWFsJx69wXF8LxnhMBg6v1W/RHMjJ6rn1IQHLZoqoBoWL9i K8xISzvZMWPqs0jUe/AOHaD6l9XIJW4kb8pyAxqsnrgq4fdo+xc1ZZTo6rdjP1WG1MyW sOlXT05ZBeKL2ejdZzpcHtOntsJrPgWyoXiocEcoLeVn+/vMGEMzXMdDKEKIZMODMM/X sdGQ== X-Gm-Message-State: AOJu0YzxpUqKndDsYJiJIzqoMgFMmACxlUYmGNM5UbcEg+Pr4r+yk3Zc 1OFuvsT+9pTebmrJh8lWf8YKS17TGEVoVseEHtY= X-Google-Smtp-Source: AGHT+IHc5qggz4PIvKNfh/i8VC/UE4xVbbUFvBvW4Z5CEw0B49oDZ062tpEfhigRDXFT9+PvVVjT/g== X-Received: by 2002:a25:e78f:0:b0:d91:b6e5:54dd with SMTP id e137-20020a25e78f000000b00d91b6e554ddmr14900959ybh.3.1698871355214; Wed, 01 Nov 2023 13:42:35 -0700 (PDT) Received: from grind.. ([179.193.10.161]) by smtp.gmail.com with ESMTPSA id z187-20020a2533c4000000b00d9cc49edae9sm329724ybz.63.2023.11.01.13.42.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 13:42:34 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v8 09/19] riscv-qmp-cmds.c: expose named features in cpu_model_expansion Date: Wed, 1 Nov 2023 17:41:54 -0300 Message-ID: <20231101204204.345470-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231101204204.345470-1-dbarboza@ventanamicro.com> References: <20231101204204.345470-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::b2c; envelope-from=dbarboza@ventanamicro.com; helo=mail-yb1-xb2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Named features (zic64b the sole example at this moment) aren't expose to users, thus we need another way to expose them. Go through each named feature, get its boolean value, do the needed conversions (bool to qbool, qbool to QObject) and add it to output dict. Another adjustment is needed: named features are evaluated during finalize(), so riscv_cpu_finalize_features() needs to be mandatory regardless of whether we have an input dict or not. Otherwise zic64b will always return 'false', which is incorrect: the default values of cache blocksizes ([cbom/cbop/cboz]_blocksize) are set to 64, satisfying the conditions for zic64b. Here's an API usage example after this patch: $ ./build/qemu-system-riscv64 -S -M virt -display none -qmp tcp:localhost:1234,server,wait=off $ ./scripts/qmp/qmp-shell localhost:1234 Welcome to the QMP low-level shell! Connected to QEMU 8.1.50 (QEMU) query-cpu-model-expansion type=full model={"name":"rv64"} {"return": {"model": {"name": "rv64", "props": {... "zic64b": true, ...}}}} zic64b is set to 'true', as expected, since all cache sizes are 64 bytes by default. If we change one of the cache blocksizes, zic64b is returned as 'false': (QEMU) query-cpu-model-expansion type=full model={"name":"rv64","props":{"cbom_blocksize":128}} {"return": {"model": {"name": "rv64", "props": {... "zic64b": false, ...}}}} Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/riscv-qmp-cmds.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c index 2f2dbae7c8..5ada279776 100644 --- a/target/riscv/riscv-qmp-cmds.c +++ b/target/riscv/riscv-qmp-cmds.c @@ -26,6 +26,7 @@ #include "qapi/error.h" #include "qapi/qapi-commands-machine-target.h" +#include "qapi/qmp/qbool.h" #include "qapi/qmp/qdict.h" #include "qapi/qmp/qerror.h" #include "qapi/qobject-input-visitor.h" @@ -99,6 +100,22 @@ static void riscv_obj_add_multiext_props(Object *obj, QDict *qdict_out, } } +static void riscv_obj_add_named_feats_qdict(Object *obj, QDict *qdict_out) +{ + const RISCVCPUMultiExtConfig *named_cfg; + RISCVCPU *cpu = RISCV_CPU(obj); + QObject *value; + bool flag_val; + + for (int i = 0; riscv_cpu_named_features[i].name != NULL; i++) { + named_cfg = &riscv_cpu_named_features[i]; + flag_val = isa_ext_is_enabled(cpu, named_cfg->offset); + value = QOBJECT(qbool_from_bool(flag_val)); + + qdict_put_obj(qdict_out, named_cfg->name, value); + } +} + static void riscv_cpuobj_validate_qdict_in(Object *obj, QObject *props, const QDict *qdict_in, Error **errp) @@ -129,11 +146,6 @@ static void riscv_cpuobj_validate_qdict_in(Object *obj, QObject *props, goto err; } - riscv_cpu_finalize_features(RISCV_CPU(obj), &local_err); - if (local_err) { - goto err; - } - visit_end_struct(visitor, NULL); err: @@ -191,6 +203,13 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type, } } + riscv_cpu_finalize_features(RISCV_CPU(obj), &local_err); + if (local_err) { + error_propagate(errp, local_err); + object_unref(obj); + return NULL; + } + expansion_info = g_new0(CpuModelExpansionInfo, 1); expansion_info->model = g_malloc0(sizeof(*expansion_info->model)); expansion_info->model->name = g_strdup(model->name); @@ -200,6 +219,7 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type, riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_extensions); riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_experimental_exts); riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_vendor_exts); + riscv_obj_add_named_feats_qdict(obj, qdict_out); /* Add our CPU boolean options too */ riscv_obj_add_qdict_prop(obj, qdict_out, "mmu"); From patchwork Wed Nov 1 20:41:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1858077 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=QRRMGIhC; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SLJsL4bXDz1yQq for ; Thu, 2 Nov 2023 07:44:38 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyI30-0002jg-GT; Wed, 01 Nov 2023 16:42:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyI2z-0002jW-IY for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:41 -0400 Received: from mail-yb1-xb2c.google.com ([2607:f8b0:4864:20::b2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyI2w-0000k3-TL for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:41 -0400 Received: by mail-yb1-xb2c.google.com with SMTP id 3f1490d57ef6-da0359751dbso244804276.1 for ; Wed, 01 Nov 2023 13:42:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698871358; x=1699476158; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=n9raNQUR8M8FL8GUSRMtUjkusVa+uIoPzSHAduhHO24=; b=QRRMGIhCqo2Gj2SXc4IVK1/fCiwXg4/jnrO7VxMW4/7rGaY/EbO9BEqgipmxet84Oa sSEgHT4PVdp9/ea99J4hLE67TDs1k9rBjYVPRJYg/5oinDhdWehyvWwXT6G9Mw1n2nf5 7pRn+EKGCkH/ktPw693SwOxkYWLwCZALzuItMZFNMZacuA/jtAQbkhbHD8qhOqOoD2v4 /kS9JQCRi4ATniOvJ3t1lOlQvrAq7O8u3s/8voNnKhQNjgWdzTfNoTQnvHqEPM8bBh52 JHbYPNNsSy6NsSlobg5rC6+lokm+eA6k75g9hLXYA8X9yUiVV+6uh5MOfhoGFH3S9Oid ATTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698871358; x=1699476158; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n9raNQUR8M8FL8GUSRMtUjkusVa+uIoPzSHAduhHO24=; b=D3ksBtps4e9SJC2egrN48U7mhrROnfXp/fchk2KDJjeeRHE0rpJytk5ovPFV+EK5GE xnR8cAqsQqzuYJnycwSYsn1UMizCp++Hk0NghIQSVfYTZRgjFLGxnghr7wRjl0OetX1O bxX+rtp6y6sPY5Bf7PHCvhiktH1PEBhcC1/rVXT9nXMuMEkQjRiLwUalBS7rKBRLWppS x0s2b+36aRuMEFzk51KVMUIae8LfAvOUU5mWs31rhRrRhPfZ8UZqMxYtX7BRJkPiLD5u D/lHEe23H+jY0KcMSjwQXqZI0uvPliB4IIGr6jn3cwqk+7COaTkJqXlmjL9a9Gj/OUol ZxAA== X-Gm-Message-State: AOJu0YxdQyZ3Ap83a3NedKHPC536Xl9AVpLdUYc6B1u+pNhr3yVt6Qrg XBeiiekMHq43G8K7Fa6B+7m5CINBbGZBDqs6g1Q= X-Google-Smtp-Source: AGHT+IFXy9AJ2qOm/MUgR2jawAum6X+hOET4orfWEX9Su3RvLGNun0axeHOgE3FMJdjwfyy/pWDXEA== X-Received: by 2002:a25:738c:0:b0:da3:aef8:efc7 with SMTP id o134-20020a25738c000000b00da3aef8efc7mr3039806ybc.0.1698871357765; Wed, 01 Nov 2023 13:42:37 -0700 (PDT) Received: from grind.. ([179.193.10.161]) by smtp.gmail.com with ESMTPSA id z187-20020a2533c4000000b00d9cc49edae9sm329724ybz.63.2023.11.01.13.42.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 13:42:37 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v8 10/19] target/riscv: add rva22u64 profile definition Date: Wed, 1 Nov 2023 17:41:55 -0300 Message-ID: <20231101204204.345470-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231101204204.345470-1-dbarboza@ventanamicro.com> References: <20231101204204.345470-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::b2c; envelope-from=dbarboza@ventanamicro.com; helo=mail-yb1-xb2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The rva22U64 profile, described in: https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva22-profiles Contains a set of CPU extensions aimed for 64-bit userspace applications. Enabling this set to be enabled via a single user flag makes it convenient to enable a predictable set of features for the CPU, giving users more predicability when running/testing their workloads. QEMU implements all possible extensions of this profile. All the so called 'synthetic extensions' described in the profile that are cache related are ignored/assumed enabled (Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa, Zicclsm) since we do not implement a cache model. An abstraction called RISCVCPUProfile is created to store the profile. 'ext_offsets' contains mandatory extensions that QEMU supports. Same thing with the 'misa_ext' mask. Optional extensions must be enabled manually in the command line if desired. The design here is to use the common target/riscv/cpu.c file to store the profile declaration and export it to the accelerator files. Each accelerator is then responsible to expose it (or not) to users and how to enable the extensions. Next patches will implement the profile for TCG and KVM. Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 32 ++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 12 ++++++++++++ 2 files changed, 44 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c7c09c1f7c..c5bb2210ab 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1469,6 +1469,38 @@ Property riscv_cpu_options[] = { DEFINE_PROP_END_OF_LIST(), }; +/* + * RVA22U64 defines some 'named features' or 'synthetic extensions' + * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa + * and Zicclsm. We do not implement caching in QEMU so we'll consider + * all these named features as always enabled. + * + * There's no riscv,isa update for them (nor for zic64b, despite it + * having a cfg offset) at this moment. + */ +static RISCVCPUProfile RVA22U64 = { + .name = "rva22u64", + .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU, + .ext_offsets = { + CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause), + CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb), + CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin), + CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr), + CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom), + CPU_CFG_OFFSET(ext_zicbop), CPU_CFG_OFFSET(ext_zicboz), + + /* mandatory named features for this profile */ + CPU_CFG_OFFSET(zic64b), + + RISCV_PROFILE_EXT_LIST_END + } +}; + +RISCVCPUProfile *riscv_profiles[] = { + &RVA22U64, + NULL, +}; + static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf12f34082..e4d5d69207 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -66,6 +66,18 @@ const char *riscv_get_misa_ext_description(uint32_t bit); #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) +typedef struct riscv_cpu_profile { + const char *name; + uint32_t misa_ext; + bool enabled; + bool user_set; + const int32_t ext_offsets[]; +} RISCVCPUProfile; + +#define RISCV_PROFILE_EXT_LIST_END -1 + +extern RISCVCPUProfile *riscv_profiles[]; + /* Privileged specification version */ enum { PRIV_VERSION_1_10_0 = 0, From patchwork Wed Nov 1 20:41:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1858090 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=K/JofTD3; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SLJvh3DvGz1yQ5 for ; Thu, 2 Nov 2023 07:46:40 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyI34-0002lB-AX; Wed, 01 Nov 2023 16:42:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyI32-0002ka-Mv for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:44 -0400 Received: from mail-yb1-xb31.google.com ([2607:f8b0:4864:20::b31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyI2z-0000kc-J2 for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:43 -0400 Received: by mail-yb1-xb31.google.com with SMTP id 3f1490d57ef6-d9b9adaf291so195569276.1 for ; Wed, 01 Nov 2023 13:42:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698871360; x=1699476160; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NzlbiQ+OWiuQaLiREzwSbJ6YhgK4c0yS/a9TyPGRRgU=; b=K/JofTD3x13u2FOHCjjlWyS9Lzgkj12ZuIctznqkQAv2bO1px4iAFk4SSYwY1YeD10 o8fNXn8qEHhWBOGjxW1v/YhPRlUy88etr/FiNWAue+NVOBzX69Sv1B2nJQmllto4CqU3 fWAtFnMZXNtC8SMTZ+ESTewBojiDtm9fRDL5aPt11h14ZNWdhuq8nJtO4PaRZ2zkrxYs OM4D+7jWEzQT/xA1SiNdCm5ljQEKtGhDGLZJKlUj52tpiXxUm9s3LZ7z9fRGbs5Snw47 rcheNdoZ7MWb1PXBtwVeKM+ovW3m2rEC5hanYhQGssPQqbhwF9rewXMlL+PsxH75riQr 7saw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698871360; x=1699476160; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NzlbiQ+OWiuQaLiREzwSbJ6YhgK4c0yS/a9TyPGRRgU=; b=ILUNUg5peohasyoleydP9bPPxQmpC+sgOEZeDpxoAnIAcSVJQdbFbx5KziSelF4pU/ V+aSCI7sql5mEHQE6BcvwC55Eey9Icuk+d4kHhc3Mm/Tdv5KLBuEBSXHW35BzT3Fprhv Xg6RTbMb+ZCsGvrKfqOlfssJtHQf6i70ByT8D0+q8MkZ7XedzVmWjMzcAerYpuBiJDxM 0oPjSGj8Qdj2u3ipDyap3APw50ir14VV+Ahf8qfBWohi6eDnmJmqHF69lOUmhQXRz3O4 SatXGwMSLkuKFCowB8aSZOxhi1Fmmf3SF+UGdmBUN+GVZSsW+chiLd+7jhMOnDKmUQJz s9MQ== X-Gm-Message-State: AOJu0YxjEpcKu4cylSfewj4NjYrui/e2hATXvv2IIB7fSFEiFgxdEvY5 AoWUjsUoXnd1X1zNxF5Npgyq8A8PLKuNeBTZbJQ= X-Google-Smtp-Source: AGHT+IHVcgcZSR3doe7k8NWo7ga9mtZrLooAmtr8tqO3LDReahoE7SYemV/cDeWvDFlACrnNtwOt9Q== X-Received: by 2002:a25:cfd1:0:b0:d9a:b70c:d32b with SMTP id f200-20020a25cfd1000000b00d9ab70cd32bmr14273649ybg.41.1698871360326; Wed, 01 Nov 2023 13:42:40 -0700 (PDT) Received: from grind.. ([179.193.10.161]) by smtp.gmail.com with ESMTPSA id z187-20020a2533c4000000b00d9cc49edae9sm329724ybz.63.2023.11.01.13.42.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 13:42:40 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v8 11/19] target/riscv/kvm: add 'rva22u64' flag as unavailable Date: Wed, 1 Nov 2023 17:41:56 -0300 Message-ID: <20231101204204.345470-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231101204204.345470-1-dbarboza@ventanamicro.com> References: <20231101204204.345470-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::b31; envelope-from=dbarboza@ventanamicro.com; helo=mail-yb1-xb31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org KVM does not have the means to support enabling the rva22u64 profile. The main reasons are: - we're missing support for some mandatory rva22u64 extensions in the KVM module; - we can't make promises about enabling a profile since it all depends on host support in the end. We'll revisit this decision in the future if needed. For now mark the 'rva22u64' profile as unavailable when running a KVM CPU: $ qemu-system-riscv64 -machine virt,accel=kvm -cpu rv64,rva22u64=true qemu-system-riscv64: can't apply global rv64-riscv-cpu.rva22u64=true: 'rva22u64' is not available with KVM Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Reviewed-by: Andrew Jones --- target/riscv/kvm/kvm-cpu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index a11c0e4a99..c5167d474a 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -393,7 +393,7 @@ static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, } if (value) { - error_setg(errp, "extension %s is not available with KVM", + error_setg(errp, "'%s' is not available with KVM", propname); } } @@ -474,6 +474,11 @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); + + /* We don't have the needed KVM support for profiles */ + for (i = 0; riscv_profiles[i] != NULL; i++) { + riscv_cpu_add_kvm_unavail_prop(cpu_obj, riscv_profiles[i]->name); + } } static int kvm_riscv_get_regs_core(CPUState *cs) From patchwork Wed Nov 1 20:41:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1858073 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=XhYx8A9x; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SLJqk3Z9Lz1yQt for ; Thu, 2 Nov 2023 07:43:13 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyI39-0002oo-3n; Wed, 01 Nov 2023 16:42:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyI35-0002mF-0H for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:47 -0400 Received: from mail-yb1-xb34.google.com ([2607:f8b0:4864:20::b34]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyI33-0000l7-7e for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:46 -0400 Received: by mail-yb1-xb34.google.com with SMTP id 3f1490d57ef6-d9fe0a598d8so187032276.2 for ; Wed, 01 Nov 2023 13:42:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698871363; x=1699476163; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uSoX6rjUU/2n4CNyFV+Vzk+TYtUfPnVoeFyLwZTJRVo=; b=XhYx8A9xDKcw9KjAOILWDC4JEJFqw6jKO17rAaPd96Hs+hyGXTT4rMJWsUKDkTb0Nt uv4gkRotlkqEbmL5HcF5JGvE20k6+WkGk8h9+Be+5O3WJX0+hS4mURmflIeBH9Wp6l69 Oa9mAk6my1lVQoeI9LL4iMFyyIv946zeWjYsI6h8DbkaI6tm/90k/n/g7lY2o70DOfuI ik+MYVR3gn2s6QCvvQ9VuGSciF/2/qRpUsxKO+T7elFHkcdpX/4/3PT5d0Cyk5aJ7/Cx n9CkO4kC6vRrFmYqcV3Ckfc6e21PqrIjihf5zDSK+VqcWd5MIevnu9KzfnQniEKkCo3z mznA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698871363; x=1699476163; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uSoX6rjUU/2n4CNyFV+Vzk+TYtUfPnVoeFyLwZTJRVo=; b=Mk2Oh9oa0zY11sIN8wjrRjTTHYkGJ4Tjq7KvwXuS825S+pbVb1GApJHGOU8DiYUCON 7sP5q5MohMwo00/zFKFLNcoTnP0lzB8sel3fPSlzZKVqcO+cvy53VsUAW0vEoXd0WA4N F+vePXD9bGoqgYOtWDeidadgMF7o17mcHbG/ttfSlK28Lz1C7uCho1pW2GlkCqXPj87V S38wgMmclXax9jM877vXljf2rhWF1wJOcweA922yNS5cky2OICySn2MtbwoIJyELwYhH d+E5sKvx6A63+Ud6Tbe4f9iZvlxkcrixbZHAhOoEZKJITfDvPyyWuoJIk/dGCSQT5tUl yhLw== X-Gm-Message-State: AOJu0Yx+PgqyIbgjs6+HohalBgFYl1+dEHdIMcbCgPhY023KdNOzJLy6 os8/uUiHgnfvOVBWY15tlRkp5TzCUYbXZ8niEyU= X-Google-Smtp-Source: AGHT+IHUx8ILxlgHEYDR2/jTGiC0u9FvFhHh9bYjnz9CeEn2JSMHxllJ9diCM40XI5nGSxv7pL59Gg== X-Received: by 2002:a5b:5ca:0:b0:da0:5ba2:6275 with SMTP id w10-20020a5b05ca000000b00da05ba26275mr15123606ybp.34.1698871362869; Wed, 01 Nov 2023 13:42:42 -0700 (PDT) Received: from grind.. ([179.193.10.161]) by smtp.gmail.com with ESMTPSA id z187-20020a2533c4000000b00d9cc49edae9sm329724ybz.63.2023.11.01.13.42.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 13:42:42 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v8 12/19] target/riscv/tcg: add user flag for profile support Date: Wed, 1 Nov 2023 17:41:57 -0300 Message-ID: <20231101204204.345470-13-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231101204204.345470-1-dbarboza@ventanamicro.com> References: <20231101204204.345470-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::b34; envelope-from=dbarboza@ventanamicro.com; helo=mail-yb1-xb34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The TCG emulation implements all the extensions described in the RVA22U64 profile, both mandatory and optional. The mandatory extensions will be enabled via the profile flag. We'll leave the optional extensions to be enabled by hand. Given that this is the first profile we're implementing in TCG we'll need some ground work first: - all profiles declared in riscv_profiles[] will be exposed to users. TCG is the main accelerator we're considering when adding profile support in QEMU, so for now it's safe to assume that all profiles in riscv_profiles[] will be relevant to TCG; - we'll not support user profile settings for vendor CPUs. The flags will still be exposed but users won't be able to change them; - profile support, albeit available for all non-vendor CPUs, will be based on top of the new 'rv64i' CPU. Setting a profile to 'true' means enable all mandatory extensions of this profile, setting it to 'false' will disable all mandatory profile extensions of the CPU, which will obliterate preset defaults. This is not a problem for a bare CPU like rv64i but it can allow for silly scenarios when using other CPUs. E.g. an user can do "-cpu rv64,rva22u64=false" and have a bunch of default rv64 extensions disabled. The recommended way of using profiles is the rv64i CPU, but users are free to experiment. For now we'll handle multi-letter extensions only. MISA extensions need additional steps that we'll take care later. At this point we can boot a Linux buildroot using rva22u64 using the following options: -cpu rv64i,rva22u64=true,sv39=true,g=true,c=true,s=true Note that being an usermode/application profile we still need to explicitly set 's=true' to enable Supervisor mode to boot Linux. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 63 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index a577cd795a..cfe7375c42 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -821,6 +821,67 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) } } +static void cpu_set_profile(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPUProfile *profile = opaque; + RISCVCPU *cpu = RISCV_CPU(obj); + bool value; + int i, ext_offset; + + if (object_dynamic_cast(obj, TYPE_RISCV_VENDOR_CPU) != NULL) { + error_setg(errp, "Profile %s is not available for vendor CPUs", + profile->name); + return; + } + + if (cpu->env.misa_mxl != MXL_RV64) { + error_setg(errp, "Profile %s only available for 64 bit CPUs", + profile->name); + return; + } + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + profile->user_set = true; + profile->enabled = value; + + for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { + ext_offset = profile->ext_offsets[i]; + + if (profile->enabled) { + cpu_validate_multi_ext_priv_ver(&cpu->env, ext_offset); + } + + g_hash_table_insert(multi_ext_user_opts, + GUINT_TO_POINTER(ext_offset), + (gpointer)profile->enabled); + isa_ext_update_enabled(cpu, ext_offset, profile->enabled); + } +} + +static void cpu_get_profile(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPUProfile *profile = opaque; + bool value = profile->enabled; + + visit_type_bool(v, name, &value, errp); +} + +static void riscv_cpu_add_profiles(Object *cpu_obj) +{ + for (int i = 0; riscv_profiles[i] != NULL; i++) { + const RISCVCPUProfile *profile = riscv_profiles[i]; + + object_property_add(cpu_obj, profile->name, "bool", + cpu_get_profile, cpu_set_profile, + NULL, (void *)profile); + } +} + static bool cpu_ext_is_deprecated(const char *ext_name) { return isupper(ext_name[0]); @@ -948,6 +1009,8 @@ static void riscv_cpu_add_user_properties(Object *obj) riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); + riscv_cpu_add_profiles(obj); + for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { qdev_property_add_static(DEVICE(obj), prop); } From patchwork Wed Nov 1 20:41:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1858074 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=jSRSJWEb; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SLJrH2Bclz1yQq for ; Thu, 2 Nov 2023 07:43:43 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyI3C-0002qr-6d; Wed, 01 Nov 2023 16:42:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyI39-0002ph-Su for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:51 -0400 Received: from mail-yw1-x1133.google.com ([2607:f8b0:4864:20::1133]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyI35-0000le-73 for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:51 -0400 Received: by mail-yw1-x1133.google.com with SMTP id 00721157ae682-5ac376d311aso2945397b3.1 for ; Wed, 01 Nov 2023 13:42:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698871365; x=1699476165; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BtLP1bmnrYx23NpyRO7vqdrXdO3+B48ws0vPcDyjVGM=; b=jSRSJWEbEMmrmuQDbHrBweafahNAB6CdYiNjyu9GAZJLLTPAlCjLYFvNMAgCERiUAR 2QHij3a1iCVQME/fFY72KBBPLDFzucerapCGvALsGpNfsCJ4BdqtoS2+Qt5PF3Jlfoxi xdCguJKOuT30VUFw/3M/Iu0MCnWJhhUcFo0HZFludBDJqljYgEytEnHM4jzTuvEavCSb GAaoJEV3CU89nDuXo1DgmxIh8Y2fqoR/tiCqE5ibN/Q6OchyCdxWnAhlIByJ/ItHaUVN CGCqfIsNWvysc4/8jHHaSWK6hGPLQdPLRa83O7w1hY1csgjGD2pjQ9R7l7IFCeoibHD8 HDKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698871365; x=1699476165; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BtLP1bmnrYx23NpyRO7vqdrXdO3+B48ws0vPcDyjVGM=; b=NCGgzRgGsMVDipzhFwHzoWC/LGq/k4uUFzNIIu0Z/fMhQrWdATGQNV5Qj2kMCmsBus kzS8bn5CncsT21R7Dx6D7PDfwM/2uFhwOhEsipaVACzqvvQeb49s/aNkYY3pK5T4A9io ENDJxHvEobOEXff0vhjhEWi3C6mkj8eEqeC875TrRuwwjH/gSgOc5wfJANlRBzT7AKDI sbfz3qMWlsfng5s+AyHk9dOljiyUIIOWS6dEysxcPv04m+bit8iuIXr1yMAIFRI6AJi7 sDhn6cWJObuSrECDvKKEt9Tzt171ioBXquvOpzuth4QEp67AjNpYxOR7xUfi4eFNgIgR sfcA== X-Gm-Message-State: AOJu0YwFuGou9L3SoTrEG5r8ag46jAi73n4Y1LS4wl5RO+TgibiZLPuf vTdT+xplEBxRRtLCOB3O/12iOVQZ6O497vs3YuM= X-Google-Smtp-Source: AGHT+IGNjpeLENCopJztg0a/TBE5umBZJ1o/UUGGYUplRvRKJpnBYqn5haibxN+p/HLLNclMOBzWGw== X-Received: by 2002:a25:aa85:0:b0:d9a:5244:32e5 with SMTP id t5-20020a25aa85000000b00d9a524432e5mr18212655ybi.35.1698871365432; Wed, 01 Nov 2023 13:42:45 -0700 (PDT) Received: from grind.. ([179.193.10.161]) by smtp.gmail.com with ESMTPSA id z187-20020a2533c4000000b00d9cc49edae9sm329724ybz.63.2023.11.01.13.42.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 13:42:45 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v8 13/19] target/riscv/tcg: add MISA user options hash Date: Wed, 1 Nov 2023 17:41:58 -0300 Message-ID: <20231101204204.345470-14-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231101204204.345470-1-dbarboza@ventanamicro.com> References: <20231101204204.345470-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1133; envelope-from=dbarboza@ventanamicro.com; helo=mail-yw1-x1133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We already track user choice for multi-letter extensions because we needed to honor user choice when enabling/disabling extensions during realize(). We refrained from adding the same mechanism for MISA extensions since we didn't need it. Profile support requires tne need to check for user choice for MISA extensions, so let's add the corresponding hash now. It works like the existing multi-letter hash (multi_ext_user_opts) but tracking MISA bits options in the cpu_set_misa_ext_cfg() callback. Note that we can't re-use the same hash from multi-letter extensions because that hash uses cpu->cfg offsets as keys, while for MISA extensions we're using MISA bits as keys. After adding the user hash in cpu_set_misa_ext_cfg(), setting default values with object_property_set_bool() in add_misa_properties() will end up marking the user choice hash with them. Set the default value manually to avoid it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index cfe7375c42..dd9eea3d0e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -34,6 +34,7 @@ /* Hash that stores user set extensions */ static GHashTable *multi_ext_user_opts; +static GHashTable *misa_ext_user_opts; static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) { @@ -733,6 +734,10 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, return; } + g_hash_table_insert(misa_ext_user_opts, + GUINT_TO_POINTER(misa_bit), + (gpointer)value); + prev_val = env->misa_ext & misa_bit; if (value == prev_val) { @@ -796,6 +801,7 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { */ static void riscv_cpu_add_misa_properties(Object *cpu_obj) { + CPURISCVState *env = &RISCV_CPU(cpu_obj)->env; bool use_def_vals = riscv_cpu_is_generic(cpu_obj); int i; @@ -816,7 +822,13 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) NULL, (void *)misa_cfg); object_property_set_description(cpu_obj, name, desc); if (use_def_vals) { - object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL); + if (misa_cfg->enabled) { + env->misa_ext |= bit; + env->misa_ext_mask |= bit; + } else { + env->misa_ext &= ~bit; + env->misa_ext_mask &= ~bit; + } } } } @@ -1061,6 +1073,7 @@ static void tcg_cpu_instance_init(CPUState *cs) RISCVCPU *cpu = RISCV_CPU(cs); Object *obj = OBJECT(cpu); + misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); riscv_cpu_add_user_properties(obj); From patchwork Wed Nov 1 20:41:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1858082 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=U48gc6R3; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SLJtL4pTrz1yQ5 for ; Thu, 2 Nov 2023 07:45:30 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyI3C-0002qk-4L; Wed, 01 Nov 2023 16:42:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyI39-0002pl-TN for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:51 -0400 Received: from mail-yw1-x1129.google.com ([2607:f8b0:4864:20::1129]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyI37-0000mH-71 for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:51 -0400 Received: by mail-yw1-x1129.google.com with SMTP id 00721157ae682-5a877e0f0d8so12071097b3.1 for ; Wed, 01 Nov 2023 13:42:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698871368; x=1699476168; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dlAN1vaJtp5YKaguKIaH0R7B/VGngPd/SycEVccU/h4=; b=U48gc6R3np7ZzHeU5il8fjqOmEXEwTDwA/kD9hFt6ax5wtb0s0hiuLoQUjAEugK4OE gqnJxn9LaSdCw3st9waED8amVWbMTbIlQD6TtsLwkeK1ZEvxeZva9lWFtnQ9vM3RXW1d 1cinSriZxrgE+iosRKjtCKMioym7oAJciTvAQYGQ3dYB5aB3U6OB8pgEj9DNJmX1vxqt ubTwbVSNWU1Wph+sqXlpf4uQIkPR4y1hIjELt6ZF0KY2bH/KnQ3JnMuroHiEznkaVFJN xcSsk2AbfPhzQ9LtmdmfiIGYiP01RLFMbjormzJNIeO8SmTc+MOhaOL34wzUJDhO3YmA ngtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698871368; x=1699476168; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dlAN1vaJtp5YKaguKIaH0R7B/VGngPd/SycEVccU/h4=; b=C0HrNVaJ8AxRvSYwEuqERWO0mGTgHCsUhsG3b4S9sVzKpuPH6JIEwmYpWIFYgQJneL 28dxZ1sYL+wKFHmDBYNB42PW3y8y7EAmFfk03Q+zaLiE/DVAlJqe2ZnIloq8ukKxRKMb xnhGs7A+rP/boTEweCWMmRPYks7drpr7HZ8Rz3sP7jt8FRJt8GowHzVW5HF5bsOABY1i vbuAf30JUzYvHwiHZJSEzohg0BAl+BVtCkvLcjTwqpGbwP8LmMG8THN525fM1kTxovGw XojN1HKpcaGt1I7PfSjXl9u7dukQa3FYI2D0iLrW393oL7m+UkIn4/soUGVdy5gGf+7O dfgg== X-Gm-Message-State: AOJu0YxKdIXfK9ELuhcoTiY/wQjRPHgTFcitnHXfqctoeY0HYcb3Tnp9 9neBdav4D5jYoTnWl5j6o6YRx4acCVb8jf5cdSg= X-Google-Smtp-Source: AGHT+IHB2JAl6Xio84qVh32tuL5sz4J9xjc/jDZi7zeoy9P9GjDmc/KMD2oLJAnsVGQ/K711ag53zw== X-Received: by 2002:a25:440a:0:b0:da0:adac:f00f with SMTP id r10-20020a25440a000000b00da0adacf00fmr2888606yba.28.1698871367946; Wed, 01 Nov 2023 13:42:47 -0700 (PDT) Received: from grind.. ([179.193.10.161]) by smtp.gmail.com with ESMTPSA id z187-20020a2533c4000000b00d9cc49edae9sm329724ybz.63.2023.11.01.13.42.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 13:42:47 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v8 14/19] target/riscv/tcg: add riscv_cpu_write_misa_bit() Date: Wed, 1 Nov 2023 17:41:59 -0300 Message-ID: <20231101204204.345470-15-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231101204204.345470-1-dbarboza@ventanamicro.com> References: <20231101204204.345470-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1129; envelope-from=dbarboza@ventanamicro.com; helo=mail-yw1-x1129.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We have two instances of the setting/clearing a MISA bit from env->misa_ext and env->misa_ext_mask pattern. And the next patch will end up adding one more. Create a helper to avoid code repetition. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 44 ++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 21 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index dd9eea3d0e..707da775a0 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -42,6 +42,20 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) GUINT_TO_POINTER(ext_offset)); } +static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, + bool enabled) +{ + CPURISCVState *env = &cpu->env; + + if (enabled) { + env->misa_ext |= bit; + env->misa_ext_mask |= bit; + } else { + env->misa_ext &= ~bit; + env->misa_ext_mask &= ~bit; + } +} + static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -744,20 +758,14 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, return; } - if (value) { - if (vendor_cpu) { - g_autofree char *cpuname = riscv_cpu_get_name(cpu); - error_setg(errp, "'%s' CPU does not allow enabling extensions", - cpuname); - return; - } - - env->misa_ext |= misa_bit; - env->misa_ext_mask |= misa_bit; - } else { - env->misa_ext &= ~misa_bit; - env->misa_ext_mask &= ~misa_bit; + if (value && vendor_cpu) { + g_autofree char *cpuname = riscv_cpu_get_name(cpu); + error_setg(errp, "'%s' CPU does not allow enabling extensions", + cpuname); + return; } + + riscv_cpu_write_misa_bit(cpu, misa_bit, value); } static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, @@ -801,7 +809,6 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { */ static void riscv_cpu_add_misa_properties(Object *cpu_obj) { - CPURISCVState *env = &RISCV_CPU(cpu_obj)->env; bool use_def_vals = riscv_cpu_is_generic(cpu_obj); int i; @@ -822,13 +829,8 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) NULL, (void *)misa_cfg); object_property_set_description(cpu_obj, name, desc); if (use_def_vals) { - if (misa_cfg->enabled) { - env->misa_ext |= bit; - env->misa_ext_mask |= bit; - } else { - env->misa_ext &= ~bit; - env->misa_ext_mask &= ~bit; - } + riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit, + misa_cfg->enabled); } } } From patchwork Wed Nov 1 20:42:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1858092 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=eV6XqYCh; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SLJw155Nxz1yQ5 for ; Thu, 2 Nov 2023 07:46:57 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyI3D-0002rL-5D; Wed, 01 Nov 2023 16:42:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyI3C-0002qs-58 for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:54 -0400 Received: from mail-yb1-xb2f.google.com ([2607:f8b0:4864:20::b2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyI3A-0000mq-Lc for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:53 -0400 Received: by mail-yb1-xb2f.google.com with SMTP id 3f1490d57ef6-d9ad67058fcso200700276.1 for ; Wed, 01 Nov 2023 13:42:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698871370; x=1699476170; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zLO3dp+mWG+xJnWmyXtKFLploomzW4poqdousI7nZAE=; b=eV6XqYChAKDpehai4FzslHcj4dEZGZY4OUDgN4L2CWpS8xL3dKfLNoOrJstM9f/wp9 J5Qn69KIYF3SPC6m9HUABcjfc370lHdv9RwqOeZe+6piC95zjmNCJ4rd21+pbDDhB+t5 fRh9tnNqU0rrhGllvqy9C1+DitBm5e1TPzrgiNRbmwo7rHJA6fhcK5e/aHttAUkNo1sg y734ienMLOhrV0IttBfvY0FS8GvWtE2ISOzwOjHhZ0v3iLpmc8tiZrAcf2X6w+c7YoY0 2AjRKQ/W3+D09UFFRVFyV++TBZjoEzYzI/HrP7oVsAEJRGOOj6yV7qZbVJAB93V7km9B 6OPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698871370; x=1699476170; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zLO3dp+mWG+xJnWmyXtKFLploomzW4poqdousI7nZAE=; b=LR9FaIZDn7OxtKpYaN6+TrRqDWSBtaa79NqlVIXhY2Y+VXNm3EX93afUN90FeeJxA5 w1g5982nYRzG+20HW3QP2uqlDpgPzER/jg6e0wo5NxATdaZwtelOjvNQf20mB+Rgf05V KNC0Km9mUEnAhRGI6GI5VyuTkqk4wXp3A5F2s9ztKAw6EtsCHNhTa45jaJLss7qfmgCe R5mYaSRQi48vD3+m6iUD9HoTxa0qsaRvhZLc758jFeBpTJyUyKwwMXg/FfVRcxJGisym kNIxTi5+NFCBFJE9n0dspr5nGMn7WVAZw4pZV/vnZjlGSX0dWoJPRFFcpKqkhM2AcxHs XexQ== X-Gm-Message-State: AOJu0YzUTEDQhSYqYL2v043WbCXMsraAuNfIV/Ntk6CN/NldFSzwSgPW /DyeZlFCpViuWBrpGK6BQDTfw9VRuVWK25gCUG4= X-Google-Smtp-Source: AGHT+IHdHaWs1RxI5DnJ2sdlPwxejSCNHiujB4TZFYpWZDKpjP/Dc65sxZjUcP4RLbGqEmV28Oz6Vw== X-Received: by 2002:a25:ec03:0:b0:d86:5844:a897 with SMTP id j3-20020a25ec03000000b00d865844a897mr15878999ybh.5.1698871370537; Wed, 01 Nov 2023 13:42:50 -0700 (PDT) Received: from grind.. ([179.193.10.161]) by smtp.gmail.com with ESMTPSA id z187-20020a2533c4000000b00d9cc49edae9sm329724ybz.63.2023.11.01.13.42.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 13:42:50 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v8 15/19] target/riscv/tcg: handle profile MISA bits Date: Wed, 1 Nov 2023 17:42:00 -0300 Message-ID: <20231101204204.345470-16-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231101204204.345470-1-dbarboza@ventanamicro.com> References: <20231101204204.345470-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::b2f; envelope-from=dbarboza@ventanamicro.com; helo=mail-yb1-xb2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The profile support is handling multi-letter extensions only. Let's add support for MISA bits as well. We'll go through every known MISA bit. If the profile doesn't declare the bit as mandatory, ignore it. Otherwise, set the bit in env->misa_ext and env->misa_ext_mask. Now that we're setting profile MISA bits, one can use the rv64i CPU to boot Linux using the following options: -cpu rv64i,rva22u64=true,rv39=true,s=true,zifencei=true In the near future, when rva22s64 (where, 's', 'zifencei' and sv39 are mandatory), is implemented, rv64i will be able to boot Linux loading rva22s64 and no additional flags. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 707da775a0..4b3e20545a 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -862,6 +862,27 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name, profile->user_set = true; profile->enabled = value; + for (i = 0; misa_bits[i] != 0; i++) { + uint32_t bit = misa_bits[i]; + + if (!(profile->misa_ext & bit)) { + continue; + } + + if (bit == RVI && !profile->enabled) { + /* + * Disabling profiles will not disable the base + * ISA RV64I. + */ + continue; + } + + g_hash_table_insert(misa_ext_user_opts, + GUINT_TO_POINTER(bit), + (gpointer)value); + riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); + } + for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { ext_offset = profile->ext_offsets[i]; From patchwork Wed Nov 1 20:42:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1858084 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=TvVjzYi2; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SLJtM6k86z1yQs for ; Thu, 2 Nov 2023 07:45:31 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyI3G-0002sS-HN; Wed, 01 Nov 2023 16:42:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyI3F-0002sH-Pq for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:57 -0400 Received: from mail-yb1-xb31.google.com ([2607:f8b0:4864:20::b31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyI3E-0000nU-CE for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:57 -0400 Received: by mail-yb1-xb31.google.com with SMTP id 3f1490d57ef6-d9fe0a598d8so187217276.2 for ; Wed, 01 Nov 2023 13:42:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698871373; x=1699476173; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mWO+9Z7Zky8teICfCxCS0aM7RNTTSpKadlq/tPtIWB4=; b=TvVjzYi2KEp5cVjZOazqc1nUBwkpwpHlNNIdYIvPe4m3grS97Ss5suZBN9tcv3qFWe FjRTp0XqEUGNR/6s+I2b2DTB/5K6xqHi1bg6RyHh8fcmqCRi/Jmk8ks8abvNtllE+LqC 69YEXdnT/qV7XOMSQfUkmDaNx/8dmqjPtFn8WzxkoWipAk+jb1V++s5+RD4SIQT2UNvq KaiAeUIGhqHLrCWU7gZWPNtqYL/Pj4XAZXVxeojFt+g/RRF4ls1J5eeSMWN1uRLrikMg e/mfzE/+OZ/ZU1EenefcYg08wu/3W8/taxrPAzxdvHw/RvDTNhtTx9iun6S6DI1t4aaW 0fqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698871373; x=1699476173; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mWO+9Z7Zky8teICfCxCS0aM7RNTTSpKadlq/tPtIWB4=; b=HG1Mz0XcpVLp+DwOuJ7Jlm/ngkfFDwr8ZstsIM7e22jaJabcfixKH5pzxz/qUBc7C+ mFZqg2nvt3p+73J/RRnyufgeBeqTuAYx1pVBwCHv5qrrJOdh+hYr/tpbzJwECoFWo3A9 UkTVYRqQAP7sVCZt9X+z7pbozYHrD0FvujqQBxc0H4YkMC3a+8ATAQxM8IwrqXqjTmnD bJD17I7Kc5s7hbp5NK3gFpAzvtQzHpbfZLcskH9IEnE+4Xi6mriTTbTpQ/Op0CVai4IO s+CPN73TNSMfJFyj6hqeKyGPFLJ+JKEJMm0ccVCbWdZzqQiL3F+Jb+Wlb1DT6cTZpsHY qa3g== X-Gm-Message-State: AOJu0YzKQKyCzCi2fgifC8rJxJsfMWRMHZw3lGhesH3ph1JkZPkj3CpA pw5kRbo6OmTKZk9ZLn941h93jo2rRa4p6Mxk36k= X-Google-Smtp-Source: AGHT+IF1OltIDPwrrLMdnvpkWOUAwF1OR1zBnAfm7cVIwaFctqoN0rGkSTjwbrP4VZyKixLos5ViOw== X-Received: by 2002:a25:244:0:b0:da3:b555:6474 with SMTP id 65-20020a250244000000b00da3b5556474mr3008444ybc.49.1698871373083; Wed, 01 Nov 2023 13:42:53 -0700 (PDT) Received: from grind.. ([179.193.10.161]) by smtp.gmail.com with ESMTPSA id z187-20020a2533c4000000b00d9cc49edae9sm329724ybz.63.2023.11.01.13.42.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 13:42:52 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v8 16/19] target/riscv/tcg: add hash table insert helpers Date: Wed, 1 Nov 2023 17:42:01 -0300 Message-ID: <20231101204204.345470-17-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231101204204.345470-1-dbarboza@ventanamicro.com> References: <20231101204204.345470-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::b31; envelope-from=dbarboza@ventanamicro.com; helo=mail-yb1-xb31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Previous patches added several g_hash_table_insert() patterns. Add two helpers, one for each user hash, to make the code cleaner. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 4b3e20545a..042f28a093 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -42,6 +42,18 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) GUINT_TO_POINTER(ext_offset)); } +static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) +{ + g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), + (gpointer)value); +} + +static void cpu_misa_ext_add_user_opt(uint32_t bit, bool value) +{ + g_hash_table_insert(misa_ext_user_opts, GUINT_TO_POINTER(bit), + (gpointer)value); +} + static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, bool enabled) { @@ -748,9 +760,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, return; } - g_hash_table_insert(misa_ext_user_opts, - GUINT_TO_POINTER(misa_bit), - (gpointer)value); + cpu_misa_ext_add_user_opt(misa_bit, value); prev_val = env->misa_ext & misa_bit; @@ -877,9 +887,7 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name, continue; } - g_hash_table_insert(misa_ext_user_opts, - GUINT_TO_POINTER(bit), - (gpointer)value); + cpu_misa_ext_add_user_opt(bit, profile->enabled); riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); } @@ -890,9 +898,7 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name, cpu_validate_multi_ext_priv_ver(&cpu->env, ext_offset); } - g_hash_table_insert(multi_ext_user_opts, - GUINT_TO_POINTER(ext_offset), - (gpointer)profile->enabled); + cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); isa_ext_update_enabled(cpu, ext_offset, profile->enabled); } } @@ -955,9 +961,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, multi_ext_cfg->name, lower); } - g_hash_table_insert(multi_ext_user_opts, - GUINT_TO_POINTER(multi_ext_cfg->offset), - (gpointer)value); + cpu_cfg_ext_add_user_opt(multi_ext_cfg->offset, value); prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset); From patchwork Wed Nov 1 20:42:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1858080 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=OHKS19Xs; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SLJsz1yqlz1yQ5 for ; Thu, 2 Nov 2023 07:45:11 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyI3J-0002vH-8J; Wed, 01 Nov 2023 16:43:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyI3H-0002sb-9C for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:59 -0400 Received: from mail-yb1-xb35.google.com ([2607:f8b0:4864:20::b35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyI3F-0000nn-Hv for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:42:59 -0400 Received: by mail-yb1-xb35.google.com with SMTP id 3f1490d57ef6-d8a000f6a51so190395276.3 for ; Wed, 01 Nov 2023 13:42:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698871375; x=1699476175; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/xPklFCPqsEmwPARqk+T7J33Jnys5Dkd7LaVGICZuWE=; b=OHKS19Xs2JyoK4L7NpzJwTzCVLvwPhyDLqxEiFW5X7mrP6i+wff2wyXeo0acG+gytV YIaPBgK7uGABibjxPxEoAwLHHdfLQkJk89ygvQfL/Rus16VtyM0jPJ+431MdUKCzI5g4 Jn0Chj0hSRy8AhcMT8h5mNW7nEwYN5Twt5DEhst6pZhGTTY2ocJQbveZnHiJ3svp3UyJ m2Jw+FB39jLekDN9i6cS4yWcprm6oj3q7QxA8OXi1vgW5mbRYufVTQNifwfTizFKX5iS 5c+jnByDrUYjZxEhhfsI4oziCICqzEX0EuWHd/AJszIxgfxGQKFyI+Uyr52Ud67QBseL URLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698871375; x=1699476175; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/xPklFCPqsEmwPARqk+T7J33Jnys5Dkd7LaVGICZuWE=; b=uaDltWPKLh3n43OB/ZALelwCQg5Y98L5LeP+94fw8cQJ2nNa3cc0P/RSeTAt8a1IiS uonZxfDGOx5tIs+CX8Im6ulG0J3c+HiOs5yxCHhXZ9xCH1qQ3oXPCSezpYNxwFcie8e3 wpRMqHrzmIPyHAPCWyzRalYP5J3TdBCO552l32cAEdTQIu8OKILt4i0pT+WOWSMIGbsf AZ14qPk3glHQSz+MTPfM6HEJ/V32YccPGpL11h/g+SSeND6ZOc/7GH0PNvC34GUjOfAg NSFkXkefNGtBNnQ0OZ8sdfiZqI2hljpE1Oosv7KBgtmXd7wy/dj7qbEmRS+ImbXGeAum litg== X-Gm-Message-State: AOJu0YxTQke3gxPESJOGMwFW2a8dS5Y2X8R+gpSWRREhRnbMzzgiKEOI SfRwyfBp/mxoYbx4hGk8pHASjTS/xzrpVVQEk+4= X-Google-Smtp-Source: AGHT+IEpBn73tmovX1c9TSnOcq9Hxx+1jXxcSNzX1f1WuDG27gwFJkSQHWAXz3RKSM5vjmAe65uDDQ== X-Received: by 2002:a5b:e8e:0:b0:da3:76d3:e4fb with SMTP id z14-20020a5b0e8e000000b00da376d3e4fbmr5763439ybr.26.1698871375617; Wed, 01 Nov 2023 13:42:55 -0700 (PDT) Received: from grind.. ([179.193.10.161]) by smtp.gmail.com with ESMTPSA id z187-20020a2533c4000000b00d9cc49edae9sm329724ybz.63.2023.11.01.13.42.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 13:42:55 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v8 17/19] target/riscv/tcg: honor user choice for G MISA bits Date: Wed, 1 Nov 2023 17:42:02 -0300 Message-ID: <20231101204204.345470-18-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231101204204.345470-1-dbarboza@ventanamicro.com> References: <20231101204204.345470-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::b35; envelope-from=dbarboza@ventanamicro.com; helo=mail-yb1-xb35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org RVG behaves like a profile: a single flag enables a set of bits. Right now we're considering user choice when handling RVG and zicsr/zifencei and ignoring user choice on MISA bits. We'll add user warnings for profiles when the user disables its mandatory extensions in the next patch. We'll do the same thing with RVG now to keep consistency between RVG and profile handling. First and foremost, create a new RVG only helper to avoid clogging riscv_cpu_validate_set_extensions(). We do not want to annoy users with RVG warnings like we did in the past (see 9b9741c38f), thus we'll only warn if RVG was user set and the user disabled a RVG extension in the command line. For every RVG MISA bit (IMAFD), zicsr and zifencei, the logic then becomes: - if enabled, do nothing; - if disabled and not user set, enable it; - if disabled and user set, throw a warning that it's a RVG mandatory extension. This same logic will be used for profiles in the next patch. Note that this is a behavior change, where we would error out if the user disabled either zicsr or zifencei. As long as users are explicitly disabling things in the command line we'll let them have a go at it, at least in this step. We'll error out later in the validation if needed. Other notable changes from the previous RVG code: - use riscv_cpu_write_misa_bit() instead of manually updating both env->misa_ext and env->misa_ext_mask; - set zicsr and zifencei directly. We're already checking if they were user set and priv version will never fail for these extensions, making cpu_cfg_ext_auto_update() redundant. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 73 +++++++++++++++++++++++++------------- 1 file changed, 48 insertions(+), 25 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 042f28a093..91459f2ce9 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -42,6 +42,12 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) GUINT_TO_POINTER(ext_offset)); } +static bool cpu_misa_ext_is_user_set(uint32_t misa_bit) +{ + return g_hash_table_contains(misa_ext_user_opts, + GUINT_TO_POINTER(misa_bit)); +} + static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) { g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), @@ -336,6 +342,46 @@ static void riscv_cpu_validate_named_features(RISCVCPU *cpu) riscv_cpu_validate_zic64b(cpu); } +static void riscv_cpu_validate_g(RISCVCPU *cpu) +{ + const char *warn_msg = "RVG mandates disabled extension %s"; + uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD}; + bool send_warn = cpu_misa_ext_is_user_set(RVG); + + for (int i = 0; i < ARRAY_SIZE(g_misa_bits); i++) { + uint32_t bit = g_misa_bits[i]; + + if (riscv_has_ext(&cpu->env, bit)) { + continue; + } + + if (!cpu_misa_ext_is_user_set(bit)) { + riscv_cpu_write_misa_bit(cpu, bit, true); + continue; + } + + if (send_warn) { + warn_report(warn_msg, riscv_get_misa_ext_name(bit)); + } + } + + if (!cpu->cfg.ext_zicsr) { + if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr))) { + cpu->cfg.ext_zicsr = true; + } else if (send_warn) { + warn_report(warn_msg, "zicsr"); + } + } + + if (!cpu->cfg.ext_zifencei) { + if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei))) { + cpu->cfg.ext_zifencei = true; + } else if (send_warn) { + warn_report(warn_msg, "zifencei"); + } + } +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. @@ -345,31 +391,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) CPURISCVState *env = &cpu->env; Error *local_err = NULL; - /* Do some ISA extension error checking */ - if (riscv_has_ext(env, RVG) && - !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && - riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && - riscv_has_ext(env, RVD) && - cpu->cfg.ext_zicsr && cpu->cfg.ext_zifencei)) { - - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr)) && - !cpu->cfg.ext_zicsr) { - error_setg(errp, "RVG requires Zicsr but user set Zicsr to false"); - return; - } - - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei)) && - !cpu->cfg.ext_zifencei) { - error_setg(errp, "RVG requires Zifencei but user set " - "Zifencei to false"); - return; - } - - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zicsr), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zifencei), true); - - env->misa_ext |= RVI | RVM | RVA | RVF | RVD; - env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD; + if (riscv_has_ext(env, RVG)) { + riscv_cpu_validate_g(cpu); } if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { From patchwork Wed Nov 1 20:42:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1858086 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=QzKowOBB; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SLJtR22svz1yQ5 for ; Thu, 2 Nov 2023 07:45:35 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyI3M-0002wd-7f; Wed, 01 Nov 2023 16:43:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyI3J-0002vp-IJ for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:43:02 -0400 Received: from mail-yb1-xb30.google.com ([2607:f8b0:4864:20::b30]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyI3H-0000oJ-Sx for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:43:01 -0400 Received: by mail-yb1-xb30.google.com with SMTP id 3f1490d57ef6-d84c24a810dso195269276.2 for ; Wed, 01 Nov 2023 13:42:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698871378; x=1699476178; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eyxJ5o1XNCLKUofFvbhHGkWjPnphVBJQklnymO7Q2oI=; b=QzKowOBB98CiOZjzXZj3Z+ncgpXXaharnT0aPb8rcopRI0OrKv7fEnFniylvdYGbFs GbUnOHDIQN0j2+BjVXDo9C0TP9e2Wu8Zg3hwqyZM4QnCblBX4osA/VSNwXT1T6zh8asl HzXiD3F5bda/gnBMbrJIAZSQPPt5dHX+k9pU43iZBVNzET8VtW7k9TqeewqyLMFpbYDL VmnteGPWckeptxZsccLVfP/CtSkqcnekFWuzokVGQOd8L9WLbbm7ToPf46509ln6TN1O szo7zgpYxr5xEYwFN9WNCwZWi/81Ak/q+xka55/zuOfoYVmPp1BuF1xBpYRCaGhuvb6I FODQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698871378; x=1699476178; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eyxJ5o1XNCLKUofFvbhHGkWjPnphVBJQklnymO7Q2oI=; b=vQTo7QXbNO8CnA6n5eoM+Tg1IBJMxY2kG3O3ypHUA4N506Wi/lgv5GrXE096vwDiC4 kuHjgiGoGvWGTyoJ9lf04f1Og9KrCpdlBetJHY/hAriR8d5NLkMYRyiAN5G4FT9zWZBa YLLuviMAZiCtCX66Zql1Yv33kx6dj+mlZzyWIfLCzjXg1OhUFF89bENxr/VamwLB8G/3 y5ypNLL7L2sC40GlS8+gafcJKsqeFonv63Triiy5trWqw+ZKfJl1fRxsiImL6kC+b8id SwzHYLu7+NrG6SCVIy167K8deYe0xW+e/jJBPj3MxkqVssFp6WSmmfvQSg8Dif6BxItw TNew== X-Gm-Message-State: AOJu0Yyb2lmPWcYZK/1MH7EZeKr6WprBrQa2VZeEN9fRMPD02cRCT3Yk FAQ5o1Rk5byJKXdkJMMO39aABIrG0o31p2ijImQ= X-Google-Smtp-Source: AGHT+IH3iuovcn1PIn5e/o5laFm2W6aFWB4GTtix018zJXIVieBbQGb9RfOhQLtkhbsZ/PL8HIQAnQ== X-Received: by 2002:a25:b31e:0:b0:d9a:e6d3:ae1c with SMTP id l30-20020a25b31e000000b00d9ae6d3ae1cmr14674024ybj.53.1698871378255; Wed, 01 Nov 2023 13:42:58 -0700 (PDT) Received: from grind.. ([179.193.10.161]) by smtp.gmail.com with ESMTPSA id z187-20020a2533c4000000b00d9cc49edae9sm329724ybz.63.2023.11.01.13.42.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 13:42:57 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v8 18/19] target/riscv/tcg: validate profiles during finalize Date: Wed, 1 Nov 2023 17:42:03 -0300 Message-ID: <20231101204204.345470-19-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231101204204.345470-1-dbarboza@ventanamicro.com> References: <20231101204204.345470-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::b30; envelope-from=dbarboza@ventanamicro.com; helo=mail-yb1-xb30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Enabling a profile and then disabling some of its mandatory extensions is a valid use. It can be useful for debugging and testing. But the common expected use of enabling a profile is to enable all its mandatory extensions. Add an user warning when mandatory extensions from an enabled profile are disabled in the command line. We're also going to disable the profile flag in this case since the profile must include all the mandatory extensions. This flag can be exposed by QMP to indicate the actual profile state after the CPU is realized. After this patch, this will throw warnings: -cpu rv64,rva22u64=true,zihintpause=false,zicbom=false,zicboz=false qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension zihintpause qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension zicbom qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension zicboz Note that the following will NOT throw warnings because the profile is being enabled last, hence all its mandatory extensions will be enabled: -cpu rv64,zihintpause=false,zicbom=false,zicboz=false,rva22u64=true Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 69 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 91459f2ce9..ecf2bcd7ad 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -147,6 +147,26 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) g_assert_not_reached(); } +static const char *cpu_cfg_ext_get_name(uint32_t ext_offset) +{ + const RISCVCPUMultiExtConfig *feat; + const RISCVIsaExtData *edata; + + for (edata = isa_edata_arr; edata->name != NULL; edata++) { + if (edata->ext_enable_offset == ext_offset) { + return edata->name; + } + } + + for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { + if (feat->offset == ext_offset) { + return feat->name; + } + } + + g_assert_not_reached(); +} + static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) { const RISCVCPUMultiExtConfig *feat; @@ -664,6 +684,54 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) riscv_cpu_disable_priv_spec_isa_exts(cpu); } +static void riscv_cpu_validate_profile(RISCVCPU *cpu, + RISCVCPUProfile *profile) +{ + const char *warn_msg = "Profile %s mandates disabled extension %s"; + bool send_warn = profile->user_set && profile->enabled; + bool profile_impl = true; + int i; + + for (i = 0; misa_bits[i] != 0; i++) { + uint32_t bit = misa_bits[i]; + + if (!(profile->misa_ext & bit)) { + continue; + } + + if (!riscv_has_ext(&cpu->env, bit)) { + profile_impl = false; + + if (send_warn) { + warn_report(warn_msg, profile->name, + riscv_get_misa_ext_name(bit)); + } + } + } + + for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { + int ext_offset = profile->ext_offsets[i]; + + if (!isa_ext_is_enabled(cpu, ext_offset)) { + profile_impl = false; + + if (send_warn) { + warn_report(warn_msg, profile->name, + cpu_cfg_ext_get_name(ext_offset)); + } + } + } + + profile->enabled = profile_impl; +} + +static void riscv_cpu_validate_profiles(RISCVCPU *cpu) +{ + for (int i = 0; riscv_profiles[i] != NULL; i++) { + riscv_cpu_validate_profile(cpu, riscv_profiles[i]); + } +} + void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) { CPURISCVState *env = &cpu->env; @@ -682,6 +750,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) } riscv_cpu_validate_named_features(cpu); + riscv_cpu_validate_profiles(cpu); if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { /* From patchwork Wed Nov 1 20:42:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1858088 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=deuqh4ds; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SLJvK09DPz1yQs for ; Thu, 2 Nov 2023 07:46:21 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyI3O-0002xH-Fs; Wed, 01 Nov 2023 16:43:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyI3N-0002wy-7D for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:43:05 -0400 Received: from mail-yw1-x112b.google.com ([2607:f8b0:4864:20::112b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyI3K-0000oh-O7 for qemu-devel@nongnu.org; Wed, 01 Nov 2023 16:43:04 -0400 Received: by mail-yw1-x112b.google.com with SMTP id 00721157ae682-5a7c95b8d14so2974687b3.3 for ; Wed, 01 Nov 2023 13:43:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698871381; x=1699476181; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=52R6Eg8XXxFu2Bm2dvauXbc+AXEa1/gdYft/MoiQmhc=; b=deuqh4ds8EmyaJZGvskb+JRBTJhj2mRwNkJeOqyVR2pSI7P6moAWA3rm7IG5YiVPV1 LG2ntVDcx1HUttO0/peD6TrpcCLnksIkDTd2PUMDP/ZsnR9ioZYvfYtxjCMjEUHEbvAu GU/JaSsNJQhHjAjW9/Dqre5M+NNRI6Rbb6Wm0PR8UiXwxvBMkx44+DFmyy91nnXplH6E 5YEYmUdijsUv8FcbNJN4bDCcYvPfO7pQ78ouZic+aNmxLqqVKx4DJP9J1NSQ2wcjmuBN 6uiinTIwxzAGvU+WpLE9Yrr6bV58WiJvAc0wCB6lbpa9ou/qNf7L2A4Crf7zK3KtCAKs Twvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698871381; x=1699476181; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=52R6Eg8XXxFu2Bm2dvauXbc+AXEa1/gdYft/MoiQmhc=; b=VNVgr8AQANLzZKd5N1HflxsaYxVRF445DYw3c3Pf93Mg8a7aNupwjuudXaKj5RemG3 FXBc5/uhPjFGOQC1HXG03VGnN7Z1xmOGD8DBHPA+EgqkS1bgQ3pjdYi//tPLVr0F2QHX e6a5gSR7oFjPuv8CrqQla4XGtniq1uEUkjCskAdu0whog8ZuqXFuLgPjtdcts84YXJB4 WL+BG9kJM76RTVlV/RVxy8xHOnED1oAJuJiwDFpRp89WzoPqIjo/UVhxvDw7l46R+SpX cDfxrC4hNoB7IMML1UklFsid+mk2xd5X7ay9H+Zdv8sWJC1qwOPUag5NBtjR8mtbJyhQ M4iQ== X-Gm-Message-State: AOJu0Yxu0g6v0cIK6+GR1PHtIn4GpVzWRHVZRrLbkFCfuyaw6WsTN7Lk zeyER+9DrO/oMccq+w4yOQEA/kuVFsNo0Op0BUA= X-Google-Smtp-Source: AGHT+IEWhffg4w8FZhoTovVRS1DmqqawUqlKQgWuX7ZmyV6nWKmf8aUAvTvi6XItcPZ1va+MN8Mgxw== X-Received: by 2002:a05:6902:1892:b0:d9c:cc27:cc4a with SMTP id cj18-20020a056902189200b00d9ccc27cc4amr15324195ybb.32.1698871380888; Wed, 01 Nov 2023 13:43:00 -0700 (PDT) Received: from grind.. ([179.193.10.161]) by smtp.gmail.com with ESMTPSA id z187-20020a2533c4000000b00d9cc49edae9sm329724ybz.63.2023.11.01.13.42.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 13:43:00 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v8 19/19] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion Date: Wed, 1 Nov 2023 17:42:04 -0300 Message-ID: <20231101204204.345470-20-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231101204204.345470-1-dbarboza@ventanamicro.com> References: <20231101204204.345470-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::112b; envelope-from=dbarboza@ventanamicro.com; helo=mail-yw1-x112b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Expose all profile flags for all CPUs when executing query-cpu-model-expansion. This will allow callers to quickly determine if a certain profile is implemented by a given CPU. This includes vendor CPUs - the fact that they don't have profile user flags doesn't mean that they don't implement the profile. After this change it's possible to quickly determine if our stock CPUs implement the existing rva22u64 profile. Here's a few examples: $ ./build/qemu-system-riscv64 -S -M virt -display none -qmp tcp:localhost:1234,server,wait=off $ ./scripts/qmp/qmp-shell localhost:1234 Welcome to the QMP low-level shell! Connected to QEMU 8.1.50 - As expected, the 'max' CPU implements the rva22u64 profile. (QEMU) query-cpu-model-expansion type=full model={"name":"max"} {"return": {"model": {"name": "rv64", "props": {... "rva22u64": true, ...}}}} - rv64 is missing "zba", "zbb", "zbs", "zkt" and "zfhmin": query-cpu-model-expansion type=full model={"name":"rv64"} {"return": {"model": {"name": "rv64", "props": {... "rva22u64": false, ...}}}} query-cpu-model-expansion type=full model={"name":"rv64", "props":{"zba":true,"zbb":true,"zbs":true,"zkt":true,"zfhmin":true}} {"return": {"model": {"name": "rv64", "props": {... "rva22u64": true, ...}}}} We have no vendor CPUs that supports rva22u64 (veyron-v1 is the closest - it is missing just 'zkt'). In short, aside from the 'max' CPU, we have no CPUs that supports rva22u64 by default. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/riscv-qmp-cmds.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c index 5ada279776..205aaabeb9 100644 --- a/target/riscv/riscv-qmp-cmds.c +++ b/target/riscv/riscv-qmp-cmds.c @@ -116,6 +116,19 @@ static void riscv_obj_add_named_feats_qdict(Object *obj, QDict *qdict_out) } } +static void riscv_obj_add_profiles_qdict(Object *obj, QDict *qdict_out) +{ + RISCVCPUProfile *profile; + QObject *value; + + for (int i = 0; riscv_profiles[i] != NULL; i++) { + profile = riscv_profiles[i]; + value = QOBJECT(qbool_from_bool(profile->enabled)); + + qdict_put_obj(qdict_out, profile->name, value); + } +} + static void riscv_cpuobj_validate_qdict_in(Object *obj, QObject *props, const QDict *qdict_in, Error **errp) @@ -220,6 +233,7 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type, riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_experimental_exts); riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_vendor_exts); riscv_obj_add_named_feats_qdict(obj, qdict_out); + riscv_obj_add_profiles_qdict(obj, qdict_out); /* Add our CPU boolean options too */ riscv_obj_add_qdict_prop(obj, qdict_out, "mmu");