From patchwork Tue Oct 31 15:37:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Bradford X-Patchwork-Id: 1857658 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=17sNoYau; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SKZ9s5M92z1yQ5 for ; Wed, 1 Nov 2023 02:41:21 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qxqrB-0002aQ-05; Tue, 31 Oct 2023 11:40:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qxqr2-0002Tb-TT for qemu-devel@nongnu.org; Tue, 31 Oct 2023 11:40:33 -0400 Received: from mail-lf1-x136.google.com ([2a00:1450:4864:20::136]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qxqqx-0003hm-Mk for qemu-devel@nongnu.org; Tue, 31 Oct 2023 11:40:32 -0400 Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-507adc3381cso8270885e87.3 for ; Tue, 31 Oct 2023 08:40:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1698766815; x=1699371615; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AU56d0AHzdjZ3iZpQHBfBuZj17xFnNf+U1/aKtUrEJI=; b=17sNoYauIo5qYJG2D9SpyDi803Qku3fRq9IiNW0KtcEHsLVIvlauG9dpg9S7pPz9U8 FmtnBooZGeeIpHyKDAVn6tyQXqhe50rdh3Z5+qa6jlkNwDgKbY59Hvi7FRcaFd/5bP0y S3IiLYO7xOnfHe3NKHI7koPvofxAdiPqHRwKRTZWSK/ZBGLhJmVqioeYSXbRRQAnhv3g O8oDbI+tgAY4ZCqBk+HY2SkjcKzwt78iINwo6sfaB24bESPaSjMOCeaSXQObBOyIUke0 c6i9A0M6Yd/KZOx5Po6iW66DAO4vWsS+pEGaflpJ8j/8S44MlMcGXpn5YG9yJHt1VoNL sENA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698766815; x=1699371615; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AU56d0AHzdjZ3iZpQHBfBuZj17xFnNf+U1/aKtUrEJI=; b=R8s161CdASt7G6m7NKpQhB9NFLjVPeUopYtsq/WeZi40ZJe8BPILp2jnqqE4Qc0ucr 8WDcyFexkelJxgyQf3rKGiVGMSK/z+897foFYCvUHqwUK8sGlisNF63elvEiZDX3/9bE NQosjomQwfPq5PYDXT3inPKr+48BE79YMk+4cxGQJJjZg7Ht2Rl8DdbEIHlG97bGcrhU wVHls2gCe6tJYPh4zWRViAbcZuoRrxroTW+MvUeTlrNhpdZch2KCnBHQIuAdtr+wE6dz 2rHSTD/iWCEnqaJ7V7EMwtVIEdPCFJagP/zSyLqWYfJDVm/GDVrlB6/WxWmhyyo2v9uf GfHQ== X-Gm-Message-State: AOJu0YwXN1wMuNJprlFmR6Lxw/zfg6TsDAeChseyLCY7IhsVfz0hIvHT AiFznVzjJ2xKmUfQOAM1oEj3w10nSnTvlNE48Rq3rg== X-Google-Smtp-Source: AGHT+IHK9khzs5qC/g/rvYIDQJIo/51bhD6BGg5gLBR0Cb0qL6zgWTFjAvd2+/cXtmWi/wr7itTLGQ== X-Received: by 2002:ac2:5235:0:b0:500:d4d9:25b5 with SMTP id i21-20020ac25235000000b00500d4d925b5mr8844500lfl.56.1698766815137; Tue, 31 Oct 2023 08:40:15 -0700 (PDT) Received: from rockhopper.. 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[217.169.11.214]) by smtp.gmail.com with ESMTPSA id r12-20020a05600c458c00b003fbe4cecc3bsm2094613wmo.16.2023.10.31.08.40.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Oct 2023 08:40:14 -0700 (PDT) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford , Weiwei Li Subject: [PATCH v5 1/5] target/riscv: Propagate error from PMU setup Date: Tue, 31 Oct 2023 15:37:13 +0000 Message-ID: <20231031154000.18134-2-rbradford@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231031154000.18134-1-rbradford@rivosinc.com> References: <20231031154000.18134-1-rbradford@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=rbradford@rivosinc.com; helo=mail-lf1-x136.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org More closely follow the QEMU style by returning an Error and propagating it there is an error relating to the PMU setup. Further simplify the function by removing the num_counters parameter as this is available from the passed in cpu pointer. Signed-off-by: Rob Bradford Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Reviewed-by: Atish Patra --- target/riscv/pmu.c | 19 +++++++++---------- target/riscv/pmu.h | 3 ++- target/riscv/tcg/tcg-cpu.c | 8 +++++++- 3 files changed, 18 insertions(+), 12 deletions(-) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 36f6307d28..13801ccb78 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -434,22 +434,21 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx) } -int riscv_pmu_init(RISCVCPU *cpu, int num_counters) +void riscv_pmu_init(RISCVCPU *cpu, Error **errp) { - if (num_counters > (RV_MAX_MHPMCOUNTERS - 3)) { - return -1; + uint8_t pmu_num = cpu->cfg.pmu_num; + + if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) { + error_setg(errp, "Number of counters exceeds maximum available"); + return; } cpu->pmu_event_ctr_map = g_hash_table_new(g_direct_hash, g_direct_equal); if (!cpu->pmu_event_ctr_map) { - /* PMU support can not be enabled */ - qemu_log_mask(LOG_UNIMP, "PMU events can't be supported\n"); - cpu->cfg.pmu_num = 0; - return -1; + error_setg(errp, "Unable to allocate PMU event hash table"); + return; } /* Create a bitmask of available programmable counters */ - cpu->pmu_avail_ctrs = MAKE_32BIT_MASK(3, num_counters); - - return 0; + cpu->pmu_avail_ctrs = MAKE_32BIT_MASK(3, pmu_num); } diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 2bfb71ba87..88e0713296 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -17,13 +17,14 @@ */ #include "cpu.h" +#include "qapi/error.h" bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, uint32_t target_ctr); bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr); void riscv_pmu_timer_cb(void *priv); -int riscv_pmu_init(RISCVCPU *cpu, int num_counters); +void riscv_pmu_init(RISCVCPU *cpu, Error **errp); int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index a28918ab30..ed3eb991c0 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -614,7 +614,13 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp) } if (cpu->cfg.pmu_num) { - if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { + riscv_pmu_init(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return false; + } + + if (cpu->cfg.ext_sscofpmf) { cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, riscv_pmu_timer_cb, cpu); } From patchwork Tue Oct 31 15:37:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Bradford X-Patchwork-Id: 1857662 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=aMUFt+Yk; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SKZBQ72fHz1yQ5 for ; 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[217.169.11.214]) by smtp.gmail.com with ESMTPSA id r12-20020a05600c458c00b003fbe4cecc3bsm2094613wmo.16.2023.10.31.08.40.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Oct 2023 08:40:15 -0700 (PDT) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford , Weiwei Li Subject: [PATCH v5 2/5] target/riscv: Don't assume PMU counters are continuous Date: Tue, 31 Oct 2023 15:37:14 +0000 Message-ID: <20231031154000.18134-3-rbradford@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231031154000.18134-1-rbradford@rivosinc.com> References: <20231031154000.18134-1-rbradford@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=rbradford@rivosinc.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Check the PMU available bitmask when checking if a counter is valid rather than comparing the index against the number of PMUs. Signed-off-by: Rob Bradford Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- target/riscv/csr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4b4ab56c40..a6ea38e0ba 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -183,7 +183,8 @@ static RISCVException zcmt(CPURISCVState *env, int csrno) #if !defined(CONFIG_USER_ONLY) static RISCVException mctr(CPURISCVState *env, int csrno) { - int pmu_num = riscv_cpu_cfg(env)->pmu_num; + RISCVCPU *cpu = env_archcpu(env); + uint32_t pmu_avail_ctrs = cpu->pmu_avail_ctrs; int ctr_index; int base_csrno = CSR_MHPMCOUNTER3; @@ -192,7 +193,7 @@ static RISCVException mctr(CPURISCVState *env, int csrno) base_csrno += 0x80; } ctr_index = csrno - base_csrno; - if (!pmu_num || ctr_index >= pmu_num) { + if ((BIT(ctr_index) & pmu_avail_ctrs >> 3) == 0) { /* The PMU is not enabled or counter is out of range */ return RISCV_EXCP_ILLEGAL_INST; } From patchwork Tue Oct 31 15:37:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Bradford X-Patchwork-Id: 1857659 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=j0rqD5fd; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SKZ9w1jKNz1yQ5 for ; Wed, 1 Nov 2023 02:41:24 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qxqr8-0002Yl-4i; Tue, 31 Oct 2023 11:40:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qxqr1-0002PC-FL for qemu-devel@nongnu.org; Tue, 31 Oct 2023 11:40:31 -0400 Received: from mail-lj1-x233.google.com ([2a00:1450:4864:20::233]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qxqqx-0003iZ-Mf for qemu-devel@nongnu.org; Tue, 31 Oct 2023 11:40:31 -0400 Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2c5056059e0so83277361fa.3 for ; Tue, 31 Oct 2023 08:40:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1698766817; x=1699371617; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9mMVXx6ZKHS/Xdo2ieyq9Ad+4Pt4SoIMtAgRB3f52yc=; b=j0rqD5fdza/bMiBzrftEjc3PQ3O9AUQKc9TX/kICZgwn9VNyt0yDVqLk3Oex+E/BqT +I5N1XqKF5ABlZY+FehTUgxUpC2qKOvHjI8xCgmjsSSAiOTCBuJ2g3ueP46jExAZz2lK W0vkOtWStK6nJ9SOX9i4RZKkVwKeDzAIp/ZPBsHPOXSrVHVBCXzGgxtfioXgdr+cXqso U9xZ9rVRhe05UCiBdIbbON6y4VFmvIR5oydKcyUus+oh0OjF9QVHgJqF/P3wKniTmHuY Bf8AB01cVZkpiJMULdGrbOHs8Cp46QMXUd46mirRya39aumWidUwNNrin1iyZRaT3wAB wAjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698766817; x=1699371617; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9mMVXx6ZKHS/Xdo2ieyq9Ad+4Pt4SoIMtAgRB3f52yc=; b=vUTAS9FTSQCm4JF4vD59kBbkt3ldo6/XrCIoCJ4R+xAvuE9FmoUwNiEVcjySPhrgKQ IxbyMdxeGRKAHNXuVASVIpatXI+D4aH5zrSPLrQNndmiRS7lOu8P4LWwCJI0LruLlctM BlTSH+0D1oRvSAUrDZTeitnwtqv3nR3mKJ5U67/3rvuNfrYMnaT/wFoZ9t5Xgx+8emim tY1LfxbhZj4WIzpznQcP5dhXRsmttOLdw9ngpLliNB+HrrkN2y4FkptIELV190/V6gyz yibKp/BJxLgeGtTr+oCZVIdvsUIck2B9rkHezmvuPAp9sPFcXq3NCUXN4IFYavgB6Ia6 xkdg== X-Gm-Message-State: AOJu0YykhKXNYJFFX2i0zy+1DcvOnoa5YL9YJBQqzf4eUzNmNhzRSzjI 1Ygv9/i/gI/gXwI1m+bCvDXfOo+asMa0u08FKBR7yA== X-Google-Smtp-Source: AGHT+IFRkGg8wFvbyo6XvhxF/jE5rgx6/au+IvVHbhiztAPeusn7m+zQ7JBrEtkBAFzd/X8rH8njBQ== X-Received: by 2002:a2e:ba88:0:b0:2c5:18a9:620b with SMTP id a8-20020a2eba88000000b002c518a9620bmr7948677ljf.23.1698766817381; Tue, 31 Oct 2023 08:40:17 -0700 (PDT) Received: from rockhopper.. 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[217.169.11.214]) by smtp.gmail.com with ESMTPSA id r12-20020a05600c458c00b003fbe4cecc3bsm2094613wmo.16.2023.10.31.08.40.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Oct 2023 08:40:16 -0700 (PDT) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford , Weiwei Li Subject: [PATCH v5 3/5] target/riscv: Use existing PMU counter mask in FDT generation Date: Tue, 31 Oct 2023 15:37:15 +0000 Message-ID: <20231031154000.18134-4-rbradford@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231031154000.18134-1-rbradford@rivosinc.com> References: <20231031154000.18134-1-rbradford@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::233; envelope-from=rbradford@rivosinc.com; helo=mail-lj1-x233.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org During the FDT generation use the existing mask containing the enabled counters rather then generating a new one. Using the existing mask will support the use of discontinuous counters. Signed-off-by: Rob Bradford Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- hw/riscv/virt.c | 2 +- target/riscv/pmu.c | 6 +----- target/riscv/pmu.h | 2 +- 3 files changed, 3 insertions(+), 7 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 9de578c756..241681f98d 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -722,7 +722,7 @@ static void create_fdt_pmu(RISCVVirtState *s) pmu_name = g_strdup_printf("/pmu"); qemu_fdt_add_subnode(ms->fdt, pmu_name); qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); - riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name); + riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name); g_free(pmu_name); } diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 13801ccb78..7ddf4977b1 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -34,13 +34,9 @@ * to provide the correct value as well. Heterogeneous PMU per hart is not * supported yet. Thus, number of counters are same across all harts. */ -void riscv_pmu_generate_fdt_node(void *fdt, int num_ctrs, char *pmu_name) +void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name) { uint32_t fdt_event_ctr_map[15] = {}; - uint32_t cmask; - - /* All the programmable counters can map to any event */ - cmask = MAKE_32BIT_MASK(3, num_ctrs); /* * The event encoding is specified in the SBI specification diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 88e0713296..505fc850d3 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -28,6 +28,6 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp); int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx); -void riscv_pmu_generate_fdt_node(void *fdt, int num_counters, char *pmu_name); +void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name); int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); From patchwork Tue Oct 31 15:37:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Bradford X-Patchwork-Id: 1857660 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=bMOfhy+H; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SKZB42vDzz1yQ5 for ; Wed, 1 Nov 2023 02:41:32 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qxqr4-0002Tr-Fg; Tue, 31 Oct 2023 11:40:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qxqr0-0002O3-UL for qemu-devel@nongnu.org; Tue, 31 Oct 2023 11:40:30 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qxqqx-0003jc-Ql for qemu-devel@nongnu.org; Tue, 31 Oct 2023 11:40:30 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-4083f61312eso44961485e9.3 for ; Tue, 31 Oct 2023 08:40:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1698766818; x=1699371618; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0dJrVwBEdmfAgS9OLeWwtGKmvnxoPN9IUw1QMaB//MA=; b=bMOfhy+Hbe63YP4IsMEngeFAkW+3MinZO1T39LOgpxpJhBUJeICtyqgQrSBIgoWPsq eSk9bE5EF5ZkvfFUv3D9G3evG1DulRZorCw1bT1OoXQYugEk//LpP/X2lCp88wrbqWZp HwcwIEhSBS9Hjbs8J0IVnJ37bmJBsriTKsj/6UI/js67zkYhK2havPYxJFeGzjgNH+mB lcVjjiJEUKb8KOiU8FnDUieFHIV2D4ujSVfKBy3dRA6F1sm05JX2Sn7weA5gS4TomzLE gXWHD1+b9OemHKmTxc2p9/l8hTcJWLMhDpRnGsgltuZ9PvvMjEEWsaQ+zBOoBD15Wavo drkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698766818; x=1699371618; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0dJrVwBEdmfAgS9OLeWwtGKmvnxoPN9IUw1QMaB//MA=; b=xUJ2w4iTLD+yCN3+wkDf+wQxzwj19ZKNgFSMu3ThLduw9lT6AP5Dq8yjIfAyFRdOdZ GdwbjTpt0V2Xq9cOjuHwszcd995vYQjZMwvR43vL/06LkfQ2gCneE7NIxiN3Y/h8GnBF GF84o7MRiZ02dkn7Wm8Qb4QueQDUx76tN86E5k8/2q8B84Y18y6e+MY1wzqNu25tl2PV GZNJ3m71SVd68IYcz/woThPsFbjB7Ng8/EM6iEDMAqiqbbtyX8yjRNo3X3t65a3TZMLL 8wJTDi8ryiVsAxBYnadl0HiPlwDPa3bePrNatoYu3+VjOH2VxFP2mO8myQlzHltya5mg Qoeg== X-Gm-Message-State: AOJu0YxiJl83uTvjr2TVLkH2BA9WgSRuRKJCuANAuup5ayoMR8/e24l5 BaR4ShvSqdxoe/ymT44tM58fqTzIW3k9UYc61Kh3gg== X-Google-Smtp-Source: AGHT+IGdVYcQgUxnblbi+osRsR1ddEQE6bobo6n4y41NOYteO7w4wUBPmNqBsFh3EkdYbv2FTj0n/g== X-Received: by 2002:a05:600c:46d1:b0:405:3a3d:6f53 with SMTP id q17-20020a05600c46d100b004053a3d6f53mr11374604wmo.3.1698766818631; Tue, 31 Oct 2023 08:40:18 -0700 (PDT) Received: from rockhopper.. (214.11.169.217.in-addr.arpa. [217.169.11.214]) by smtp.gmail.com with ESMTPSA id r12-20020a05600c458c00b003fbe4cecc3bsm2094613wmo.16.2023.10.31.08.40.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Oct 2023 08:40:17 -0700 (PDT) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford , Weiwei Li Subject: [PATCH v5 4/5] target/riscv: Add "pmu-mask" property to replace "pmu-num" Date: Tue, 31 Oct 2023 15:37:16 +0000 Message-ID: <20231031154000.18134-5-rbradford@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231031154000.18134-1-rbradford@rivosinc.com> References: <20231031154000.18134-1-rbradford@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=rbradford@rivosinc.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Using a mask instead of the number of PMU devices supports the accurate emulation of platforms that have a discontinuous set of PMU counters. The "pmu-num" property now generates a warning when used by the user on the command line. Rather than storing the value for "pmu-num" convert it directly to the mask if it is specified (overwriting the default "pmu-mask" value) likewise the value is calculated from the mask if the property value is obtained. In the unusual situation that both "pmu-mask" and "pmu-num" are provided then then the order on the command line determines which takes precedence (later overwriting earlier.) Signed-off-by: Rob Bradford Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 40 +++++++++++++++++++++++++++++++++++++- target/riscv/cpu_cfg.h | 2 +- target/riscv/machine.c | 2 +- target/riscv/pmu.c | 15 +++++++------- target/riscv/tcg/tcg-cpu.c | 2 +- 5 files changed, 50 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac4a6c7eec..51accdba5f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1362,8 +1362,46 @@ const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = { DEFINE_PROP_END_OF_LIST(), }; +static void prop_pmu_num_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu = RISCV_CPU(obj); + uint8_t pmu_num; + + visit_type_uint8(v, name, &pmu_num, errp); + + if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) { + error_setg(errp, "Number of counters exceeds maximum available"); + return; + } + + if (pmu_num == 0) { + cpu->cfg.pmu_mask = 0; + } else { + cpu->cfg.pmu_mask = MAKE_64BIT_MASK(3, pmu_num); + } + + warn_report("\"pmu-num\" property is deprecated; use \"pmu-mask\""); +} + +static void prop_pmu_num_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu = RISCV_CPU(obj); + uint8_t pmu_num = ctpop32(cpu->cfg.pmu_mask); + + visit_type_uint8(v, name, &pmu_num, errp); +} + +const PropertyInfo prop_pmu_num = { + .name = "pmu-num", + .get = prop_pmu_num_get, + .set = prop_pmu_num_set, +}; + Property riscv_cpu_options[] = { - DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), + DEFINE_PROP_UINT32("pmu-mask", RISCVCPU, cfg.pmu_mask, MAKE_64BIT_MASK(3, 16)), + {.name = "pmu-num", .info = &prop_pmu_num}, /* Deprecated */ DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 0e6a0f245c..f4e6f273fc 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -123,7 +123,7 @@ struct RISCVCPUConfig { bool ext_xtheadsync; bool ext_XVentanaCondOps; - uint8_t pmu_num; + uint32_t pmu_mask; char *priv_spec; char *user_spec; char *bext_spec; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index c7c862cdd3..9f6e3f7a6d 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -313,7 +313,7 @@ static bool pmu_needed(void *opaque) { RISCVCPU *cpu = opaque; - return cpu->cfg.pmu_num; + return (cpu->cfg.pmu_mask > 0); } static const VMStateDescription vmstate_pmu_ctr_state = { diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 7ddf4977b1..0e7d58b8a5 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -18,14 +18,13 @@ #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/error-report.h" #include "cpu.h" #include "pmu.h" #include "sysemu/cpu-timers.h" #include "sysemu/device_tree.h" #define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ -#define MAKE_32BIT_MASK(shift, length) \ - (((uint32_t)(~0UL) >> (32 - (length))) << (shift)) /* * To keep it simple, any event can be mapped to any programmable counters in @@ -184,7 +183,7 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx) CPURISCVState *env = &cpu->env; gpointer value; - if (!cpu->cfg.pmu_num) { + if (!cpu->cfg.pmu_mask) { return 0; } value = g_hash_table_lookup(cpu->pmu_event_ctr_map, @@ -432,9 +431,12 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx) void riscv_pmu_init(RISCVCPU *cpu, Error **errp) { - uint8_t pmu_num = cpu->cfg.pmu_num; + if (cpu->cfg.pmu_mask & (COUNTEREN_CY | COUNTEREN_TM | COUNTEREN_IR)) { + error_setg(errp, "\"pmu-mask\" contains invalid bits (0-2) set"); + return; + } - if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) { + if (ctpop32(cpu->cfg.pmu_mask) > (RV_MAX_MHPMCOUNTERS - 3)) { error_setg(errp, "Number of counters exceeds maximum available"); return; } @@ -445,6 +447,5 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp) return; } - /* Create a bitmask of available programmable counters */ - cpu->pmu_avail_ctrs = MAKE_32BIT_MASK(3, pmu_num); + cpu->pmu_avail_ctrs = cpu->cfg.pmu_mask; } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ed3eb991c0..53c52389b9 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -613,7 +613,7 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp) riscv_timer_init(cpu); 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[217.169.11.214]) by smtp.gmail.com with ESMTPSA id r12-20020a05600c458c00b003fbe4cecc3bsm2094613wmo.16.2023.10.31.08.40.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Oct 2023 08:40:19 -0700 (PDT) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford , libvir-list@redhat.com (reviewer:Incompatible changes) Subject: [PATCH v5 5/5] docs/about/deprecated: Document RISC-V "pmu-num" deprecation Date: Tue, 31 Oct 2023 15:37:17 +0000 Message-ID: <20231031154000.18134-6-rbradford@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231031154000.18134-1-rbradford@rivosinc.com> References: <20231031154000.18134-1-rbradford@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22e; envelope-from=rbradford@rivosinc.com; helo=mail-lj1-x22e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This has been replaced by a "pmu-mask" property that provides much more flexibility. Signed-off-by: Rob Bradford Acked-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- docs/about/deprecated.rst | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 4e0eb2fe02..60c26bc410 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -413,6 +413,18 @@ Specifying the iSCSI password in plain text on the command line using the used instead, to refer to a ``--object secret...`` instance that provides a password via a file, or encrypted. +CPU device properties +''''''''''''''''''''' + +``pmu-num=n`` on RISC-V CPUs (since 8.2) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +In order to support more flexible counter configurations this has been replaced +by a ``pmu-mask`` property. If set of counters is continuous then the mask can +be calculated with ``((2 ^ n) - 1) << 3``. The least significant three bits +must be left clear. + + Backwards compatibility -----------------------