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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e16-20020a5d5950000000b0032f7d1e2c7csm5912914wri.95.2023.10.30.10.40.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 10:40:03 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/3] target/arm: Enable FEAT_MOPS insns in user-mode emulation Date: Mon, 30 Oct 2023 17:39:58 +0000 Message-Id: <20231030174000.3792225-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231030174000.3792225-1-peter.maydell@linaro.org> References: <20231030174000.3792225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In user-mode emulation, we need to set the SCTLR_EL1.MSCEn bit to avoid all the FEAT_MOPS insns UNDEFing. Signed-off-by: Peter Maydell --- target/arm/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index aa4e006f21a..cdb37ce5512 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -295,6 +295,8 @@ static void arm_cpu_reset_hold(Object *obj) env->cp15.sctlr_el[1] |= SCTLR_TSCXT; /* Disable access to Debug Communication Channel (DCC). */ env->cp15.mdscr_el1 |= 1 << 12; + /* Enable FEAT_MOPS */ + env->cp15.sctlr_el[1] |= SCTLR_MSCEN; #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { From patchwork Mon Oct 30 17:39:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1857206 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=muzNiCZk; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SK0vB3288z1yQW for ; Tue, 31 Oct 2023 04:41:42 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qxWFM-0000Xy-08; Mon, 30 Oct 2023 13:40:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qxWFF-0000V4-FI for qemu-devel@nongnu.org; Mon, 30 Oct 2023 13:40:09 -0400 Received: from mail-lf1-x12c.google.com ([2a00:1450:4864:20::12c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qxWFC-0000Ha-FQ for qemu-devel@nongnu.org; Mon, 30 Oct 2023 13:40:09 -0400 Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-5079f3f3d7aso7215912e87.1 for ; Mon, 30 Oct 2023 10:40:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698687604; x=1699292404; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=8ZNFOWWtLsTPgYHbvU45OdcAlg5gVb5D/Mp59sG/PFg=; b=muzNiCZkS2WfLPy85aW9hChSkUPZAxwYTwP9H6LfSCzjbX5B9Df6DDu20MricDr3ex Sf1zbU94sSjQX6bPKMwvTZqO+wO0XIgMOHUcjEPbHhfiaMT7Ok2Kgb6G5SIllzbQDdxh D3cfn/iZ1PS5ulnS/Y0nZMKYZvw6p7pp2Drlt8TCq8aKeP6I3FLUodvsef91fvnznvt8 +2Nb9ER/x6Ij+7zBOi1SaO7h8HkNBDoGsxkf9MwQhgcMQL3hNR4C1osSFIOxjQt6+kFQ /VHLYb6PKWR4gAU2ro4pr+8isls/IgUcgoSGNR6tJhC4aFR9kx6KKvbGHw19W0OGccEv gAqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698687604; x=1699292404; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8ZNFOWWtLsTPgYHbvU45OdcAlg5gVb5D/Mp59sG/PFg=; b=HUZePW/kFSqREAelRqMKWUcABpxqhuXkY4vOPDyJnR5zFNJPGzIVZ2CKFI/KTR7ai6 oJjuvlGwd+ZPX/G6+d8Bh4JkmAtL/VnhrRHFG72wZDwvaxCuYVS31yCSmJ9qXYxyPs1A 90+nNHVhDSdNODZZ+0fFKsPpgzlvcRd5vWrpG6eMgDy3Nunbi04dnItJQEh2leVkTFcw qXvKQx2Bw1QNkWWerysHer5y17qSovosqYiq++Jg1JrQr/7UeBUUNwZqr3kD50o2ddbN 3XeT9hOoGBFIJNuTb6XjTJOY4jKiKH+buS1a2wXKG4b4LYHVOWtwrcppI0YG4IlzprhI RQyg== X-Gm-Message-State: AOJu0YzLlmus1QUOQ6YmmKNQBUZfBP5rkPd+6zpiLxzYJ/845I1VYzUV 3hGbgkdHG6dvNygzPrBqvIDSs2Z/BD0aqQZk7r0= X-Google-Smtp-Source: AGHT+IEBR3fFML3WV4FbpYYol+Q4K2LQNS0YaSnDnBTonNeDQ1AtnSFBWH/Yf01hhtJpbUgjc7IDuw== X-Received: by 2002:ac2:44a9:0:b0:507:ba75:b016 with SMTP id c9-20020ac244a9000000b00507ba75b016mr7968685lfm.3.1698687604413; Mon, 30 Oct 2023 10:40:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e16-20020a5d5950000000b0032f7d1e2c7csm5912914wri.95.2023.10.30.10.40.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 10:40:03 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/3] linux-user: Report AArch64 hwcap2 fields above bit 31 Date: Mon, 30 Oct 2023 17:39:59 +0000 Message-Id: <20231030174000.3792225-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231030174000.3792225-1-peter.maydell@linaro.org> References: <20231030174000.3792225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12c; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The AArch64 ELF hwcap2 field is 64 bits, but our get_elf_hwcap2() works with uint32_t, so it accidentally fails to report any hwcaps over bit 31. Use uint64_t here. The Arm hwcap2 is only 32 bits (because the ELF format makes these fields be the size of "long" in the ABI), but since it shares the prototype declaration for get_elf_hwcap2() it is easier to also expand it to 64 bits. The only hwcap fields we implement already that are affected by this are the HBC and MOPS ones, neither of which were implemented in a previous release, so this doesn't need backporting to older stable branches. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- linux-user/loader.h | 2 +- linux-user/elfload.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/linux-user/loader.h b/linux-user/loader.h index 324e5c872af..9be00da40a4 100644 --- a/linux-user/loader.h +++ b/linux-user/loader.h @@ -61,7 +61,7 @@ uint32_t get_elf_hwcap(void); const char *elf_hwcap_str(uint32_t bit); #endif #if defined(TARGET_AARCH64) || defined(TARGET_ARM) -uint32_t get_elf_hwcap2(void); +uint64_t get_elf_hwcap2(void); const char *elf_hwcap2_str(uint32_t bit); #endif diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 2e3809f03c4..6fb44206fab 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -520,10 +520,10 @@ uint32_t get_elf_hwcap(void) return hwcaps; } -uint32_t get_elf_hwcap2(void) +uint64_t get_elf_hwcap2(void) { ARMCPU *cpu = ARM_CPU(thread_cpu); - uint32_t hwcaps = 0; + uint64_t hwcaps = 0; GET_FEATURE_ID(aa32_aes, ARM_HWCAP2_ARM_AES); GET_FEATURE_ID(aa32_pmull, ARM_HWCAP2_ARM_PMULL); @@ -784,10 +784,10 @@ uint32_t get_elf_hwcap(void) return hwcaps; } -uint32_t get_elf_hwcap2(void) +uint64_t get_elf_hwcap2(void) { ARMCPU *cpu = ARM_CPU(thread_cpu); - uint32_t hwcaps = 0; + uint64_t hwcaps = 0; GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP); GET_FEATURE_ID(aa64_sve2, ARM_HWCAP2_A64_SVE2); From patchwork Mon Oct 30 17:40:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1857203 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=XlKyM7t6; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SK0tB4RLCz1yQW for ; Tue, 31 Oct 2023 04:40:50 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qxWFJ-0000X3-5T; Mon, 30 Oct 2023 13:40:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qxWFG-0000Vv-Qp for qemu-devel@nongnu.org; Mon, 30 Oct 2023 13:40:10 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qxWFC-0000Hk-HZ for qemu-devel@nongnu.org; Mon, 30 Oct 2023 13:40:10 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-32dd70c5401so3044553f8f.0 for ; Mon, 30 Oct 2023 10:40:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698687605; x=1699292405; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=WqVvp3csTiPZFAuQuKekKYsYC9+/xgQvvKPTLe74R7I=; b=XlKyM7t6WfRjbYuviamnM9u/Yydkdmc+jIB+bJeW4pVxWQK99TdQeEcLMjKLADSJq6 bK4ojJPxnzIi1oSi+LTGAtm47ukDOiNXzSCYJ/znulSAqYJn+MDKBshA7NhkRzd2kQKs fXPruDPBQLkQaLjnMR8yBaShavWTAZFhpCkhKWDh7JkH6TxjDAserIBLNm2a56eF5ax6 U+BOvkrV4xwTtID03mk2DE2zcIskW9RBtLgtpgnVgVcQw+OkxeuuOHGprjeJnFn27TQ2 Kq+/6WCSjc47siaZUdfhslFbIDHQkVAq6srxg40ZArLsna+uIs3XQ4MhqcPw8D7Zfs+q ol9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698687605; x=1699292405; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WqVvp3csTiPZFAuQuKekKYsYC9+/xgQvvKPTLe74R7I=; b=j/1wsWzYALNMOWKbJwjSbmLCYMoArpeHXK+u+vwkWiMHWu0nLamYkUYDbREeL5vbqi oMTjFbOOThFSc/anSyKH9dbCpq46AxgIjndBoQ2yXHzbIJD3siEIVi9lpj9hQSCHQ1A3 ytc+JTVLt1nt3VWiQKN+kUyLMOMG4cMzT6nX3qWM5sjH3ksMXVcIEqoe6x8Ude7OQ/F0 08K2gxDXVCAgDuqOScoRBEwysJixriQL7P8cWfu5lT5CnuQTQS88kN/tIC9mc4b5vmLK bBtLpIIDXkUvS4qU/dZggi6DEJn7jCAENDEl3r0/YxH3C3KEzU5g29/jYbnO2vv+jWpt s0RQ== X-Gm-Message-State: AOJu0YxCuTdltcwSMvjTAk2K2NQwq6fjNOv9nnM210dVOVY16OFCOnpL q+QchZiezhkCG1mhNcFZKUdYrA== X-Google-Smtp-Source: AGHT+IHjSGG/lSAnmnoWVDhjWma3hJol5/4oEm/8AYXLMi+dxBXvkyMYWwcEc/eLuZXsBZ4OYnTztQ== X-Received: by 2002:a05:6000:1447:b0:32f:7f6c:72a6 with SMTP id v7-20020a056000144700b0032f7f6c72a6mr4689766wrx.16.1698687605019; Mon, 30 Oct 2023 10:40:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e16-20020a5d5950000000b0032f7d1e2c7csm5912914wri.95.2023.10.30.10.40.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 10:40:04 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/3] target/arm: Make FEAT_MOPS SET* insns handle Xs == XZR correctly Date: Mon, 30 Oct 2023 17:40:00 +0000 Message-Id: <20231030174000.3792225-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231030174000.3792225-1-peter.maydell@linaro.org> References: <20231030174000.3792225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Most of the registers used by the FEAT_MOPS instructions cannot use 31 as a register field value; this is CONSTRAINED UNPREDICTABLE to NOP or UNDEF (we UNDEF). However, it is permitted for the "source value" register for the memset insns SET* to be 31, which (as usual for most data-processing insns) means it should be the zero register XZR. We forgot to handle this case, with the effect that trying to set memory to zero with a "SET* Xd, Xn, XZR" sets the memory to the value that happens to be in the low byte of SP. Handle XZR when getting the SET* data value from the register file. Signed-off-by: Peter Maydell --- target/arm/tcg/helper-a64.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 84f54750fc2..ce4800b8d13 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -1206,6 +1206,15 @@ static void check_setg_alignment(CPUARMState *env, uint64_t ptr, uint64_t size, } } +static uint64_t arm_reg_or_xzr(CPUARMState *env, int reg) +{ + /* + * Runtime equivalent of cpu_reg() -- return the CPU register value, + * for contexts when index 31 means XZR (not SP). + */ + return reg == 31 ? 0 : env->xregs[reg]; +} + /* * For the Memory Set operation, our implementation chooses * always to use "option A", where we update Xd to the final @@ -1226,7 +1235,7 @@ static void do_setp(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc, int rd = mops_destreg(syndrome); int rs = mops_srcreg(syndrome); int rn = mops_sizereg(syndrome); - uint8_t data = env->xregs[rs]; + uint8_t data = arm_reg_or_xzr(env, rs); uint32_t memidx = FIELD_EX32(mtedesc, MTEDESC, MIDX); uint64_t toaddr = env->xregs[rd]; uint64_t setsize = env->xregs[rn]; @@ -1286,7 +1295,7 @@ static void do_setm(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc, int rd = mops_destreg(syndrome); int rs = mops_srcreg(syndrome); int rn = mops_sizereg(syndrome); - uint8_t data = env->xregs[rs]; + uint8_t data = arm_reg_or_xzr(env, rs); uint64_t toaddr = env->xregs[rd] + env->xregs[rn]; uint64_t setsize = -env->xregs[rn]; uint32_t memidx = FIELD_EX32(mtedesc, MTEDESC, MIDX); @@ -1349,7 +1358,7 @@ static void do_sete(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc, int rd = mops_destreg(syndrome); int rs = mops_srcreg(syndrome); int rn = mops_sizereg(syndrome); - uint8_t data = env->xregs[rs]; + uint8_t data = arm_reg_or_xzr(env, rs); uint64_t toaddr = env->xregs[rd] + env->xregs[rn]; uint64_t setsize = -env->xregs[rn]; uint32_t memidx = FIELD_EX32(mtedesc, MTEDESC, MIDX);