From patchwork Mon Oct 23 09:46:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 1853605 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=QU+gTMP2; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDVS23d6hz23jn for ; Mon, 23 Oct 2023 20:36:02 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qurL5-0005lK-1T; Mon, 23 Oct 2023 05:35:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurL3-0005l0-EV for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:09 -0400 Received: from mgamail.intel.com ([192.198.163.7]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurL1-000515-It for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:09 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698053708; x=1729589708; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YC4cLHG5Ot3FNIJG1fOkplASOnZFJvLnF/OKwjmaqso=; b=QU+gTMP2bmnnYDrNzDIBHtIa6uOHZ/DSVJRPPVwcrbQV2scXbn8orWoQ h284+KK7s7nREE7corsbywPt5fY30U3tISaqOOOIoOot1QAZXRcEOFKy4 eqTS6He/Avm+8JhKS14RYQiO1TeTlryJMpyxzXvl7FdLlUjJ2mGJ2KNsF ysdTzFzzGRLSaMGKlIut8Y/7RHgYSEb+RIFQ8Xsvnrr+18WXXlsA5Wa3l iQZiQbMVd0cb9n/jnwLP1G7GjoHcRI2KdbkEtd6LPEm47d7esDAYK/Il4 uKouU9+cHUuoSG2ABHoxL+/xAaU+q0mjDYUkb8B7DdDGdsF+b+tNASfjr A==; X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="8359479" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="8359479" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 02:35:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="707882899" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="707882899" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga003.jf.intel.com with ESMTP; 23 Oct 2023 02:35:00 -0700 From: Zhao Liu To: "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Eduardo Habkost , Yanan Wang Cc: Marcel Apfelbaum , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH v3 01/16] tests: test-smp-parse: Add the test for cores/threads per socket helpers Date: Mon, 23 Oct 2023 17:46:20 +0800 Message-Id: <20231023094635.1588282-2-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> References: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.198.163.7; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Zhao Liu Use the different ways to calculate cores/threads per socket, so that the new CPU topology levels won't be missed in these 2 helpes: * machine_topo_get_cores_per_socket() * machine_topo_get_threads_per_socket() Test the commit a1d027be95bc3 ("machine: Add helpers to get cores/ threads per socket"). Suggested-by: Igor Mammedov Signed-off-by: Zhao Liu Acked-by: Igor Mammedov Reviewed-by: Michael S. Tsirkin --- tests/unit/test-smp-parse.c | 67 ++++++++++++++++++++++++++++++------- 1 file changed, 54 insertions(+), 13 deletions(-) diff --git a/tests/unit/test-smp-parse.c b/tests/unit/test-smp-parse.c index fdc39a846ca6..24972666a74d 100644 --- a/tests/unit/test-smp-parse.c +++ b/tests/unit/test-smp-parse.c @@ -394,20 +394,47 @@ static char *smp_config_to_string(const SMPConfiguration *config) config->has_maxcpus ? "true" : "false", config->maxcpus); } -static char *cpu_topology_to_string(const CpuTopology *topo) +/* Use the different calculation than machine_topo_get_threads_per_socket(). */ +static unsigned int cpu_topology_get_threads_per_socket(const CpuTopology *topo) +{ + /* Check the divisor to avoid invalid topology examples causing SIGFPE. */ + if (!topo->sockets) { + return 0; + } else { + return topo->max_cpus / topo->sockets; + } +} + +/* Use the different calculation than machine_topo_get_cores_per_socket(). */ +static unsigned int cpu_topology_get_cores_per_socket(const CpuTopology *topo) +{ + /* Check the divisor to avoid invalid topology examples causing SIGFPE. */ + if (!topo->threads) { + return 0; + } else { + return cpu_topology_get_threads_per_socket(topo) / topo->threads; + } +} + +static char *cpu_topology_to_string(const CpuTopology *topo, + unsigned int threads_per_socket, + unsigned int cores_per_socket) { return g_strdup_printf( "(CpuTopology) {\n" - " .cpus = %u,\n" - " .sockets = %u,\n" - " .dies = %u,\n" - " .clusters = %u,\n" - " .cores = %u,\n" - " .threads = %u,\n" - " .max_cpus = %u,\n" + " .cpus = %u,\n" + " .sockets = %u,\n" + " .dies = %u,\n" + " .clusters = %u,\n" + " .cores = %u,\n" + " .threads = %u,\n" + " .max_cpus = %u,\n" + " .threads_per_socket = %u,\n" + " .cores_per_socket = %u,\n" "}", topo->cpus, topo->sockets, topo->dies, topo->clusters, - topo->cores, topo->threads, topo->max_cpus); + topo->cores, topo->threads, topo->max_cpus, + threads_per_socket, cores_per_socket); } static void check_parse(MachineState *ms, const SMPConfiguration *config, @@ -415,14 +442,26 @@ static void check_parse(MachineState *ms, const SMPConfiguration *config, bool is_valid) { g_autofree char *config_str = smp_config_to_string(config); - g_autofree char *expect_topo_str = cpu_topology_to_string(expect_topo); - g_autofree char *output_topo_str = NULL; + g_autofree char *expect_topo_str = NULL, *output_topo_str = NULL; + unsigned int expect_threads_per_socket, expect_cores_per_socket; + unsigned int ms_threads_per_socket, ms_cores_per_socket; Error *err = NULL; + expect_threads_per_socket = + cpu_topology_get_threads_per_socket(expect_topo); + expect_cores_per_socket = + cpu_topology_get_cores_per_socket(expect_topo); + expect_topo_str = cpu_topology_to_string(expect_topo, + expect_threads_per_socket, + expect_cores_per_socket); + /* call the generic parser */ machine_parse_smp_config(ms, config, &err); - output_topo_str = cpu_topology_to_string(&ms->smp); + ms_threads_per_socket = machine_topo_get_threads_per_socket(ms); + ms_cores_per_socket = machine_topo_get_cores_per_socket(ms); + output_topo_str = cpu_topology_to_string(&ms->smp, ms_threads_per_socket, + ms_cores_per_socket); /* when the configuration is supposed to be valid */ if (is_valid) { @@ -433,7 +472,9 @@ static void check_parse(MachineState *ms, const SMPConfiguration *config, (ms->smp.clusters == expect_topo->clusters) && (ms->smp.cores == expect_topo->cores) && (ms->smp.threads == expect_topo->threads) && - (ms->smp.max_cpus == expect_topo->max_cpus)) { + (ms->smp.max_cpus == expect_topo->max_cpus) && + (ms_threads_per_socket == expect_threads_per_socket) && + (ms_cores_per_socket == expect_cores_per_socket)) { return; } From patchwork Mon Oct 23 09:46:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 1853602 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=gaMC5d3E; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDVRC3JJpz23jn for ; Mon, 23 Oct 2023 20:35:18 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qurL7-0005lN-0N; Mon, 23 Oct 2023 05:35:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurL4-0005lC-LA for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:10 -0400 Received: from mgamail.intel.com ([192.198.163.7]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurL1-00050v-Ur for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:10 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698053708; x=1729589708; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BV4zRSza02ipSLTe/Y1zf6heqAPpP7n9dOeBFk+YZv0=; b=gaMC5d3EaER/mlMBAkF7R3QcMBKhKNqtD2e+eWMflF0bgXBcdveg5pOl 9IldsMyWyVmoJPESfzi/Dv1jOMaCFKvgEjpE0dPpV1AnkBZBV1To9fTCf YfwOfnFARC+mb3XmTCz6lCla5Rur4AqtV6nrFAP+kOn6N1L5dAkkyp5aG e+ZBWDkHUvRj5aE6lb14FzlOXdfBsTnv7JCSAXn9lyLg2UTMIX/xhF3SV QDRdGvH+9pwMECR1XogLfmCZ8O8U0UKF8N5wEfTm99TCrPok+6wWnxpN7 OhYkqL4oC8Xbm7DW8u/9zNGavTPoNpjDOZAYxoWXfsRMop3oIq4fYoYYj w==; X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="8359518" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="8359518" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 02:35:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="707883013" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="707883013" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga003.jf.intel.com with ESMTP; 23 Oct 2023 02:35:04 -0700 From: Zhao Liu To: "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Eduardo Habkost , Yanan Wang Cc: Marcel Apfelbaum , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH v3 02/16] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 count test Date: Mon, 23 Oct 2023 17:46:21 +0800 Message-Id: <20231023094635.1588282-3-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> References: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.198.163.7; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Zhao Liu Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be added to test the type 4 count. Signed-off-by: Zhao Liu Reviewed-by: Michael S. Tsirkin --- tests/data/acpi/q35/APIC.type4-count | 0 tests/data/acpi/q35/DSDT.type4-count | 0 tests/data/acpi/q35/FACP.type4-count | 0 tests/qtest/bios-tables-test-allowed-diff.h | 3 +++ 4 files changed, 3 insertions(+) create mode 100644 tests/data/acpi/q35/APIC.type4-count create mode 100644 tests/data/acpi/q35/DSDT.type4-count create mode 100644 tests/data/acpi/q35/FACP.type4-count diff --git a/tests/data/acpi/q35/APIC.type4-count b/tests/data/acpi/q35/APIC.type4-count new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/tests/data/acpi/q35/DSDT.type4-count b/tests/data/acpi/q35/DSDT.type4-count new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/tests/data/acpi/q35/FACP.type4-count b/tests/data/acpi/q35/FACP.type4-count new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8bf4..0ce6f8fc72ee 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,4 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/q35/APIC.type4-count", +"tests/data/acpi/q35/DSDT.type4-count", +"tests/data/acpi/q35/FACP.type4-count", From patchwork Mon Oct 23 09:46:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 1853604 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=YSdqXRXH; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDVRZ629Yz23jn for ; Mon, 23 Oct 2023 20:35:38 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qurL9-0005m6-JJ; Mon, 23 Oct 2023 05:35:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurL8-0005ly-Mj for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:14 -0400 Received: from mgamail.intel.com ([192.198.163.7]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurL6-0005D1-UA for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:14 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698053713; x=1729589713; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=duigBkwGN2u0TvuyTSbhMPw1jX5ZSRoTbJw4Cz9rBMo=; b=YSdqXRXH6pvaItq7c0sAP1gEVzyfJwFCLIGOAq2bDWvC33FALkoDnbqC qlyIA19LqOAPMVcQpgYRFCPy2RGQ4rFbW6plqhkV6XeGQ9Eohe5x3CAsJ UDHbt223FxBaSd8JVexuyl1yXLdqDAB6wGt2Dt9z+7EXZ0nYvAIYUWyC7 pKKx+q3V2ONt7W4J+4rKonZ24q4hrbbyFbXadtmYSQSSXlMNW2ZqW/Htu WiDe2GEoRaBliWcc+TzpBcaDL8/QInvizGMTQ7Z+GhkICBnMIeNORuaaR /+GhJE1K9lRpvPygK3uZqXnDKMcYicAi0HxBNUWVg0DKOHvGZZaAQzX/R A==; X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="8359543" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="8359543" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 02:35:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="707883064" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="707883064" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga003.jf.intel.com with ESMTP; 23 Oct 2023 02:35:07 -0700 From: Zhao Liu To: "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Eduardo Habkost , Yanan Wang Cc: Marcel Apfelbaum , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH v3 03/16] tests: bios-tables-test: Add test for smbios type4 count Date: Mon, 23 Oct 2023 17:46:22 +0800 Message-Id: <20231023094635.1588282-4-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> References: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.198.163.7; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Zhao Liu This tests the commit d79a284a44bb7 ("hw/smbios: Fix smbios_smp_sockets calculation"). In smbios_get_tables() (hw/smbios/smbios.c), smbios type4 table is built for each socket, so the count of type4 tables should be equal to the number of sockets. Thus for the topology in this case, there're the following considerations: 1. The topology should include multiple sockets to ensure smbios could create type4 tables for each socket. 2. In addition to sockets, for the more general topology, we should also configure as many topology levels as possible (multiple dies, no module since x86 hasn't supported it), to ensure that smbios is able to exclude the effect of other topology levels to create the type4 tables only for sockets. 3. The original miscalculation bug also misused "smp.cpus", so it's necessary to configure "cpus" (presented threads for machine) and "maxcpus" (total threads for machine) as well to make sure that configuring unpluged CPUs in smp (cpus < maxcpus) does not affect the correctness of the count of type4 tables. Based on these considerations, select the topology as the follow: -smp cpus=100,maxcpus=120,sockets=5,dies=2,cores=4,threads=3 The expected count of type4 tables = sockets (5). Suggested-by: Igor Mammedov Signed-off-by: Zhao Liu Reviewed-by: Michael S. Tsirkin --- Changes since v1: * Added description of the consideration for topology selection of this case in commit message. (Igor) --- tests/qtest/bios-tables-test.c | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 9f4bc15aaba9..cdbfb5155967 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -97,6 +97,7 @@ typedef struct { uint16_t smbios_core_count2; uint8_t *required_struct_types; int required_struct_types_len; + int type4_count; QTestState *qts; } test_data; @@ -673,12 +674,21 @@ static void smbios_cpu_test(test_data *data, uint32_t addr, } } +static void smbios_type4_count_test(test_data *data, int type4_count) +{ + int expected_type4_count = data->type4_count; + + if (expected_type4_count) { + g_assert_cmpuint(type4_count, ==, expected_type4_count); + } +} + static void test_smbios_structs(test_data *data, SmbiosEntryPointType ep_type) { DECLARE_BITMAP(struct_bitmap, SMBIOS_MAX_TYPE+1) = { 0 }; SmbiosEntryPoint *ep_table = &data->smbios_ep_table; - int i = 0, len, max_len = 0; + int i = 0, len, max_len = 0, type4_count = 0; uint8_t type, prv, crt; uint64_t addr; @@ -704,6 +714,7 @@ static void test_smbios_structs(test_data *data, SmbiosEntryPointType ep_type) if (type == 4) { smbios_cpu_test(data, addr, ep_type); + type4_count++; } /* seek to end of unformatted string area of this struct ("\0\0") */ @@ -747,6 +758,8 @@ static void test_smbios_structs(test_data *data, SmbiosEntryPointType ep_type) for (i = 0; i < data->required_struct_types_len; i++) { g_assert(test_bit(data->required_struct_types[i], struct_bitmap)); } + + smbios_type4_count_test(data, type4_count); } static void test_acpi_load_tables(test_data *data) @@ -970,6 +983,22 @@ static void test_acpi_q35_tcg(void) free_test_data(&data); } +static void test_acpi_q35_tcg_type4_count(void) +{ + test_data data = { + .machine = MACHINE_Q35, + .variant = ".type4-count", + .required_struct_types = base_required_struct_types, + .required_struct_types_len = ARRAY_SIZE(base_required_struct_types), + .type4_count = 5, + }; + + test_acpi_one("-machine smbios-entry-point-type=64 " + "-smp cpus=100,maxcpus=120,sockets=5," + "dies=2,cores=4,threads=3", &data); + free_test_data(&data); +} + static void test_acpi_q35_tcg_core_count2(void) { test_data data = { @@ -2147,6 +2176,8 @@ int main(int argc, char *argv[]) if (has_kvm) { qtest_add_func("acpi/q35/kvm/xapic", test_acpi_q35_kvm_xapic); qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar); + qtest_add_func("acpi/q35/type4-count", + test_acpi_q35_tcg_type4_count); qtest_add_func("acpi/q35/core-count2", test_acpi_q35_tcg_core_count2); } From patchwork Mon Oct 23 09:46:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 1853606 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=CiFOaH2x; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDVSD0dntz23jn for ; Mon, 23 Oct 2023 20:36:12 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qurLF-0005rU-5s; Mon, 23 Oct 2023 05:35:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLD-0005pW-3h for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:19 -0400 Received: from mgamail.intel.com ([192.198.163.7]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurL9-0005D1-A1 for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:18 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698053716; x=1729589716; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=u7RoCg+e4LPdikeh9xMzZrS0jfcndakJlWd7mgG+uTg=; b=CiFOaH2x/34y6OJbZv5OcDnPIIKiQLU+7UN5sU672pSjM8SiFg1lNZBM ujX4+Fa4N7Lg4XdxwJS1IBgcQVjwzC5JrSCu2XXRUYXg9K4c4/WsjJlLh 1+onT3VV+y150R7oi2KiC+HKhOTWTfUvR7dG1xSjrBUIUZHwMeCUVtEFZ 1uHLOTEQQ0wbFCZZX47f3T0emW5XgBVTO4ZLTugt02wH7MwL7K8RkfOth UYgtZG38Vww9c8fs4ceZKrPF5gxmSjEYLlEQrOqFEyapAYETWFRy56TX/ bo+YAVMJeXUtS0No7XSnB1tLotQhX05RelN7Ybx28FyrVe+A6mKs6Pmq7 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="8359575" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="8359575" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 02:35:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="707883093" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="707883093" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga003.jf.intel.com with ESMTP; 23 Oct 2023 02:35:10 -0700 From: Zhao Liu To: "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Eduardo Habkost , Yanan Wang Cc: Marcel Apfelbaum , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH v3 04/16] tests: bios-tables-test: Add ACPI table binaries for smbios type4 count test Date: Mon, 23 Oct 2023 17:46:23 +0800 Message-Id: <20231023094635.1588282-5-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> References: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.198.163.7; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Zhao Liu Following the guidelines in tests/qtest/bios-tables-test.c, this is step 5 and 6. Changes in the tables: FACP: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-W37791, Wed Aug 23 10:36:32 2023 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0002 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 1 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000484A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 1 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + ... APIC: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-687791, Wed Aug 23 10:36:32 2023 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000430 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : C5 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 [snip] +[3E4h 0996 1] Subtable Type : 00 [Processor Local APIC] +[3E5h 0997 1] Length : 08 +[3E6h 0998 1] Processor ID : 77 +[3E7h 0999 1] Local Apic ID : 9E +[3E8h 1000 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[3ECh 1004 1] Subtable Type : 01 [I/O APIC] +[3EDh 1005 1] Length : 0C +[3EEh 1006 1] I/O Apic ID : 00 +[3EFh 1007 1] Reserved : 00 +[3F0h 1008 4] Address : FEC00000 +[3F4h 1012 4] Interrupt : 00000000 + +[3F8h 1016 1] Subtable Type : 02 [Interrupt Source Override] +[3F9h 1017 1] Length : 0A +[3FAh 1018 1] Bus : 00 +[3FBh 1019 1] Source : 00 +[3FCh 1020 4] Interrupt : 00000002 +[400h 1024 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[402h 1026 1] Subtable Type : 02 [Interrupt Source Override] +[403h 1027 1] Length : 0A +[404h 1028 1] Bus : 00 +[405h 1029 1] Source : 05 +[406h 1030 4] Interrupt : 00000005 +[40Ah 1034 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[40Ch 1036 1] Subtable Type : 02 [Interrupt Source Override] +[40Dh 1037 1] Length : 0A +[40Eh 1038 1] Bus : 00 +[40Fh 1039 1] Source : 09 +[410h 1040 4] Interrupt : 00000009 +[414h 1044 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[416h 1046 1] Subtable Type : 02 [Interrupt Source Override] +[417h 1047 1] Length : 0A +[418h 1048 1] Bus : 00 +[419h 1049 1] Source : 0A +[41Ah 1050 4] Interrupt : 0000000A +[41Eh 1054 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[420h 1056 1] Subtable Type : 02 [Interrupt Source Override] +[421h 1057 1] Length : 0A +[422h 1058 1] Bus : 00 +[423h 1059 1] Source : 0B +[424h 1060 4] Interrupt : 0000000B +[428h 1064 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[42Ah 1066 1] Subtable Type : 04 [Local APIC NMI] +[42Bh 1067 1] Length : 06 +[42Ch 1068 1] Processor ID : FF +[42Dh 1069 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[42Fh 1071 1] Interrupt Input LINT : 01 + ... DSDT: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of /tmp/aml-8G8791, Wed Aug 23 10:36:32 2023 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x0000489D (18589) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0xDB + * OEM ID "BOCHS " + * OEM Table ID "BXPC " + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + [snip] + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + } [snip] + Processor (C077, 0x77, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x77)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x77, 0x9E, 0x01, 0x00, 0x00, 0x00 // ..w..... + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x77) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x77, Arg0, Arg1, Arg2) + } + } + } + } + ... Signed-off-by: Zhao Liu Reviewed-by: Michael S. Tsirkin --- tests/data/acpi/q35/APIC.type4-count | Bin 0 -> 1072 bytes tests/data/acpi/q35/DSDT.type4-count | Bin 0 -> 18589 bytes tests/data/acpi/q35/FACP.type4-count | Bin 0 -> 244 bytes tests/qtest/bios-tables-test-allowed-diff.h | 3 --- 4 files changed, 3 deletions(-) diff --git a/tests/data/acpi/q35/APIC.type4-count b/tests/data/acpi/q35/APIC.type4-count index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..ab60a6ef065d8ce53ae93d311d3777d2d4afb9f6 100644 GIT binary patch literal 1072 zcmXxjX)mKu7{>9_YU}A{8~a-OZpzsAwwBgf>(n~-!C>rL5ClOG1VQjwyzxDJ5_Ev|p!(#Wi9Ts`1gb+$r6yp8Et0V-fRH#;?j|Meb z)apP55|BH3=GAfaQqR0!I2mejiE6Z7K`EDe+elf zo_%BjMkQf%GRCA}Y#PR;qa_35voIkW6LT=hipjZ{l834Jm{x%4g_u!{nI)K2irM9u zQ-MD#(OQkUHq5i*uNus+#ezC4bYhVUiyN?{2}_%?tOd*6SkZ=+?O4@`)m>=oM!N?c zJy_F=wf$H(fc1mu975MHHjH577&eV#^8~g`V(S#Tr?G7Y+h?(34m;8of!Q`;?#f0%hq@0RR91 literal 0 HcmV?d00001 diff --git a/tests/data/acpi/q35/DSDT.type4-count b/tests/data/acpi/q35/DSDT.type4-count index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..edc23198cdb47a981bcbc82bc8e392b815abb554 100644 GIT binary patch literal 18589 zcmb81No*V0c804+N}`ICL`n1{%eE}fGfB;!$s#FI5@m{%JW)2O!M5a)9%Q$>+4U|Byj2$2yloJ?UOnfWdvDb}b*~J>UQquj zp7Wh^io+pqT{B%yPyZ%o80PO%m+V}*Cv~-G_rO2XFbvfAHnGGDhW6p``HYB^P{ ztmfN_c0LxY=JM%q@<%HetlC`pgVmXQ+K5gxRWFt8z}tIc6)auroFKdPY2fEkpT21wi2A|Pl)Zi@KH;lRZ9KW-&I-D*gZPs~9 zak3b*V{rqzFO}Q(Slz$aW*A{S<@oO(-@kwVuUs0DmquhFdJ<0_p18{EqFtUgL+`>? zu<|B?h7HGOdf+DAQ+Zv^jKM?o?_nzdj};nrDwY|8J5rN{k{SAuhoNDoCT9vg#eDi| zPsL14*yBd@K+(>O`6~O+djGz@gdX*m=CXl|${{?wVMLE5A!ai#WYzJeCVXqrRCAG? z&vfHQolrPyn1r1`xG{}+co<%-%^Pd;VK_JMjaPH#+^e~lrqv`*@cIGI*;fGddHyg2 zi+MY1M8j41Yu1<0imYBX@%%>Y-?Qgtu{2%m7=QY@BNPZhu8GOA3oNB)GCjFfr1}5@3-|1pyZ6xCVHnQ#_co&jwGQ4J^`eZQzkk@nF(E z8$EqCvPj3Z(c34Ow9h6_pG}@Vo4kF3N&5_X`V4yd40`(nllIx{>9g6>XS26YFlnEb zr%%h%r{(PvOxkD2(`U%jXUN+pn6%HZr_Zpb&#<>oFlnDHo<3VVeYSY}1e5mJ>glu9 z(`T!pc6j>i z@b(EN?X%O2s^M zPcUhpFvj?M7JFCP=IL{rw@)x>pW8isZuj)L-P;N> zr1KuXn?*YB@w<7X^TrJ(Mmm#Zk0<9IPtHBwoM7^tK^UM(GC)Vmc}UHMsRxi5=^0ZLqPfO1zBi31c&r%xE5+?Ped041(CK)EZ6!~qJX(eOV+7P~wUMl)JJ>9H3x2eZm0czAO?3C~?IB%3WC`4p1vWsxvIi7O6J?#d!@fP(4t2?Lb-vPc-9#1#i9cV&?{ zK*4nSgaOKZStJZl;)(;5yRt|epkO+E!T{yIED{DNam4}3U0Ea!P%xc7VSsX976}8C zxZ(iit}GGBn(gzi35~G z;s7O)FhEHp3{Vn@1C&JK040$yKuIJFP!fp)ltkhHC6O>d!Ezp57@%OmBgRf94p1=R zVQ@^0bj~ddP_UeH3j-7^=iK4|1=BgVI6%RKHIS|BoisMEgkotb z8Evno^JU`|YU?#S(uNBf=wX+by{%d>?x8x#j>ZMKAJrh z-8_4$vRc62`C1IDLW$lj-$$gkNqU>5x0Uqv2h!UjeOhVWf)%j;_qk7#^l6qpt)x$X zAbnb-%GACW#o(q~xujFLX{f%F-XKC7m0_=xmbl0M7QXO;BX52VkE^rLF}#*aup zO45(A^rK4p(GR2_73p(o`lgRapCjpWEPYN%pZh@i9HbB6+mV_+!qYo%9`MlsUhaHx z(t9l0$X@dB2Vd6$r@oA>b}tS-FK9S^Y*U=}y6o`c;6sFlczna6Aj0YZHm*Lr`x{?ZNvxEZYARw!)P+ zhtWtHJ$5lOY1;Y8vT2tJmrYoDkKs+$H2k(*NW=1e2YUMLa%Q3j+|$YF9$2@|Pv(Pl z0}obKzxXHLEW0!S74a%XKk*pW!7r>dL^Idz>FhP%y0x}sd|^Yk%P38h@#Xc<+LGl% zo#5J!x{vDs>VB>pP!Dk3h1m-HdvKYYTOf>k#S`*J0E)*Da{iT(_dm zaNUMF%XI{F9LmR<+fj@9J5Y=IJ5h`Jqo_swTTqMox1tvHZ$mBW-;P?;zXP?XzYDdf zeZAT|1Q*`{@tiW{d-W0`g=epME!eFi~4&}i~9GW7WMB(E$TmjTGW3KwW$9P zYEl1T)S~_)s73upQH%PIp%(QYM=k0 z??)}_A3!bYA4DzcA3`naA4Vs6T^R)SpEy>K{cd>d&DT_2*HG`o~a<`o~d=`X^9}`U|K< z{gbFg{g+US`ir0kMEz5!Mg1kzqW&^!QU5e*QU45TQU7JsqW&wWMg3P%i~6sj7WH38 zE$XkJ7WL1f7WLmiE$Y9CTGU@fE$Xj<9u)P@p%(SeqZaiqpceHnq89bvLM`gQjat-y z2eqhw3ALzy8MUbYE^1N#J=CK9`=~|z4^WHxAEFlZKSC|)uY(>E^*=@}>VJY-)c+K< zsQ(#iQU3~RQU7z)qW%}ChnAzcM!1-pY_9B^Jr$tS2d4^Nja3iB1gPWn={5BZoGW#! z4X(m!_e_j$)S`t3oHZYp$W&24*pwd~-D;QZ$>0at2-=gGD;>V~bz`A!F8+||SX(sf z#$w&9)s49y3gKU_)y!`ftWTh``huF1b*vtQQMtbDTlFXm%Z1;rH?PfE?;+1`>zm!b zzF#|aIF0KIUt*DS#>yO&_5INLfab>LHH_2+%U{>d4BQEED+{MEZP z!_bc5hb{vzw!;%UxPeb^_*ha%PPd1wpaJX2xJnUih5a7WA#BE2TE1KPJQIM>I9tH* zgu>#08)}*?G*lHInqnrwm<*FcOad+lV2&190e;JOIX)lbgk6s1gRfFfJ(f?B`rrz? zN`g&te4639?N@|p(A-KSxlHkj&OKM_EQ}C2<9yzOtlA0uG7@i<13APKlq@bnN z6r`k}B#p37|K4XoGa)szoj0_mW=d+7q$DneDQDawB&$WO$)Y4nl2W*&rjSB}6lzsT zAxa8Kk_}&*R8p9b!V#4erlhbWrQrgGN@^jbmUflYLP;%>lz|HxDyfx_T02xyD6cVg)xTI*8 zN{UiaRFVd8p+X_S@`g*=(yfxVP|_Aj8pJgUg#;@bE@|s7m9&+Two1|vE>9>VSk!Py z+jgs@ZIrZ4l7``ei%Qx~NZZ*~O8Ty{oszao(g<9DQAs-pX~$l*rX7^DLz0rPqd_Hg z5mHyLO6sDdE=fwk1savKlaO}qS4lf5X{RLFaKT0;brVwe0hQEEN!^l^h6^|l+-IpefxCMK0?}eQYG!9qFn2-(+sHDS`bXbx`j_9N#gmh$3B^{xpBa)Ons*{cq($Qg+ zbd-{gN>b{WPC7n z*K3LsQaq`W;*=DZq(nj|B?u{zQb`F)N=Q;)pHAu{q`tID>Z7DSN$T&{N&SS>pHWHu zl+-Ut0|Po~fRF~@S^<2NA>XA2C}}{F1_yQ0AR!IrRMH?N4NB6`kWLyRq@lb@8lt2j zNg5v3NyCIRJf@O{DQQ@eMn-hf2qBG3sH71}8j+;rX`OVMkWLp=(rHRMElH^}I_V4{ zotacgXDI26B-v+m(pf?}TU1GBDe0^vrO)Z4bA)tmN+q46q;ry#Ij@t>6VmyTN;*$T z=Orn7K_^`xqzlt3=>jEPa7q2Ki#q8dAzhqNNf#;Uq9nzWItebByYF<#%PJ{JNl8gc zq;wKoEq6(&t11aMvAF9`DM{+HbrM`CcS-g&m4y3IT#_wG{b`*9*T`K``npQOttBog zElC3zodlOvT~cONCE+d+mz0sD!K_Y#E8{LHdqXARh7XsNm879jodg%fUDD`Hm4tgY zT+*l{4d-+cTn~3ixtdDCZ5S>oCrKlDos=h}{G3Y4Q&L`%l4Ck)jF86WRnizGjY(2! zTqlha()glE8mFXjNwOz&(gYz*+)_yslr$kp>4HvzjRWo(FWgp11xhMNQf5*oO%l@N zl1iGSq)AE2UeZaI2V7 zlr$wtiIPq#5mM=aN-9xONs{`?ItjKUxQ|`=p-L)KQdyGvr*#tS7;#C{b(J(tNz;-v zFr$-Z2x;cAN}8dh8A%$vtdlMi(&Z;A=`tlx6Xu6P0wGlCDcqs-lxBgj9K{k}8x` zktBOoC(RPl?58SemXc;ADSbmH-5{hJf1;9ZP|^)a%G}gRHwo$HE0uJUl5R>;wyKk= zgjD@gl~kpqs!JM-)pSygkZP}0QjL;ok`$lQNpplW_eLenQPP|wCFXU~JR!}ms-$^J znwO-$1)a1&NDF_ak`^dwL6Z6xbF!^uq`Q=KSCUfqbkaRSy7yNq=^iEBlO+4TPP$J>_kXF9?o-lz zNlHJ^Ne>9=!PhG30VO?WnB|V{}Cz90nR3|+pq^Eza zlAco1Q%UN7rjwo#(zCx&NzW+hnIsLY=%f`wTKQX*v_eTMk~H{SCp{;m=f6=&&nfA- zBn`dLNiPWL#owu<7nJk@NYS0JX%;pBS2MAMA-4MB23p*=6e(=sJ8Ic4L9p$^V~pTH z+5zYj7HQ$vR@iTjBw?d7-@}Z@$>wF)o;{tkU;_efm}Z-odm4KhP5AYZ%Ia94m@C4! z0v!S;X_Jl6I_q8dUD(_X8?TSdLi%!FwWBd$LhYdYs~y3B<+EU;4p;+t54I6GBOiv! z>dEXC8Jj26h%D&|9fE(hzCD?beaZ&RN_*7b$e%qgYuDm18mZOq5KQpqr!R z*f2NX5i0p@7b#<*anxgB!W?r753Pv%(QOz>-wnoId5pH0X)< zn)v^l;QwMxrSQhan{?2CZR}GS)LFb4#hYBPvf4kMN<%UH$8h|xp9p(`?G5-SY`3#&E4 z_(rUjQS%f3C;nit_cbFY>`MhVrUAS+kNMgEv)>5zMp(>&(zNYX6M{TgJVV!wx?u); k4HL_0D`%79y!#9|m3SZ}4*20fB#f^~_-_Ll_+6a;1CLN!@c;k- literal 0 HcmV?d00001 diff --git a/tests/data/acpi/q35/FACP.type4-count b/tests/data/acpi/q35/FACP.type4-count index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..31fa5dd19c213034eef4eeefa6a04e61dadd8a2a 100644 GIT binary patch literal 244 zcmZ>BbPo8!z`($~*~#D8BUr&HBEVSz2pEB4AU24G0Y(N+hD|^Y6El!tgNU*~X%LSC z$X0-fGcm9T0LA|E|L2FOWMD92VqjR>!otAF!NBm72Obk1 YBHITON2VDSAnpK(F*YFF1LDH~0O^Si0RR91 literal 0 HcmV?d00001 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index 0ce6f8fc72ee..dfb8523c8bf4 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,4 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/q35/APIC.type4-count", -"tests/data/acpi/q35/DSDT.type4-count", -"tests/data/acpi/q35/FACP.type4-count", From patchwork Mon Oct 23 09:46:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 1853610 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=oGdISxEt; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDVSq515Kz23jq for ; Mon, 23 Oct 2023 20:36:43 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qurLG-0005tM-Fp; Mon, 23 Oct 2023 05:35:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLF-0005rV-4i for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:21 -0400 Received: from mgamail.intel.com ([192.198.163.7]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLD-0005De-7N for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:20 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698053719; x=1729589719; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=A17dN6g0x1K1cvV0J+mWjIOyeIxG7GCXIQ55LC424gA=; b=oGdISxEtjbpDewHGBx28kKSdr1jDcbpwmJlUzRqknuIHau/DzgrnvMHT Sxa4kxOWtr1XF5P0646MPg6H3eIZXe9MJ0gfXFxrbEn4/UCHpcnrb3eSR i6mJkyZGsjHOrdqtGyPvxCjBviVvSjUCMv6IpuKTO6HE3jHUnra1tqwdQ Qd5gdEzlYaIuUHiHyX9eo2F4z5nZOrsf/G8bwqqOxc4gy3I/oitL1uP9L aDIZ5J6ydi9ZW7WsmkC57KdLpfQfm9hI50m+SGhb89n0QnBKzyIoeGs8/ xngtXy7Z3N6U4YdAlKgjTgtVzhExolmtjIYjmNL80NVUQvQLblgL6uQaK w==; X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="8359595" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="8359595" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 02:35:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="707883133" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="707883133" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga003.jf.intel.com with ESMTP; 23 Oct 2023 02:35:14 -0700 From: Zhao Liu To: "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Eduardo Habkost , Yanan Wang Cc: Marcel Apfelbaum , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH v3 05/16] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core count test Date: Mon, 23 Oct 2023 17:46:24 +0800 Message-Id: <20231023094635.1588282-6-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> References: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.198.163.7; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Zhao Liu Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be added to test the type 4 core count field. Signed-off-by: Zhao Liu Reviewed-by: Michael S. Tsirkin --- tests/data/acpi/q35/APIC.core-count | 0 tests/data/acpi/q35/DSDT.core-count | 0 tests/data/acpi/q35/FACP.core-count | 0 tests/qtest/bios-tables-test-allowed-diff.h | 3 +++ 4 files changed, 3 insertions(+) create mode 100644 tests/data/acpi/q35/APIC.core-count create mode 100644 tests/data/acpi/q35/DSDT.core-count create mode 100644 tests/data/acpi/q35/FACP.core-count diff --git a/tests/data/acpi/q35/APIC.core-count b/tests/data/acpi/q35/APIC.core-count new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/tests/data/acpi/q35/DSDT.core-count b/tests/data/acpi/q35/DSDT.core-count new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/tests/data/acpi/q35/FACP.core-count b/tests/data/acpi/q35/FACP.core-count new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8bf4..b9bc1961309a 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,4 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/q35/APIC.core-count", +"tests/data/acpi/q35/DSDT.core-count", +"tests/data/acpi/q35/FACP.core-count", From patchwork Mon Oct 23 09:46:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 1853607 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=jYzV+1v2; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDVSX713yz23jn for ; Mon, 23 Oct 2023 20:36:28 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qurLI-0005ts-B0; Mon, 23 Oct 2023 05:35:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLG-0005tU-M4 for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:22 -0400 Received: from mgamail.intel.com ([192.198.163.7]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLE-0005D1-Ug for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:22 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698053721; x=1729589721; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DMrGDHV8au5Ua0y3CZ6ipFw2AiHlhTyp79T9DSb+Jhw=; b=jYzV+1v2/Rskmx+Y/zkh+5TGBb1vcMUFKFfRC1j+I9ocTpgCVxn64QJ0 k6dZjOEOMIdapm0153r64zXKdQcmP8a6xX7eBBrwmCohAQDTymUqiwrqj FHIgU7mU2UIGYoZk3VHKjveyIU1xz4/0rrZwj+hI1MsiK11yXG4Q3eZWz rhiXWzUKZNuwXpfSpXXK5nB8VCzV/UJnLxJ/yL6cwus03cUQNOFa9H146 /HxfSK98M63vr6Z+G8rB00gobcesrjZKZuxfzvEUdstsplMZaYkGN4m9Q GSFNZ5TsY0968ZrXunU6RV1JoAnBkCcr3SDEa4H271CPXevxV21v28dWC A==; X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="8359623" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="8359623" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 02:35:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="707883179" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="707883179" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga003.jf.intel.com with ESMTP; 23 Oct 2023 02:35:17 -0700 From: Zhao Liu To: "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Eduardo Habkost , Yanan Wang Cc: Marcel Apfelbaum , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH v3 06/16] tests: bios-tables-test: Add test for smbios type4 core count Date: Mon, 23 Oct 2023 17:46:25 +0800 Message-Id: <20231023094635.1588282-7-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> References: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.198.163.7; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Zhao Liu This tests the commit 196ea60a734c3 ("hw/smbios: Fix core count in type4"). In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of cores in the socket is not more than 255, then smbios type4 table encodes cores per socket into the core count field. So for the topology in this case, there're the following considerations: 1. cores per socket should be not more than 255 to ensure we could cover the core count field. 2. The original bug was that cores per socket was miscalculated, so now we should include as many topology levels as possible (mutiple sockets & dies, no module since x86 hasn't supported it) to cover more general topology scenarios, to ensure that the cores per socket encoded in the core count field is correct. Based on these considerations, select the topology with multiple sockets and dies: -smp 54,sockets=2,dies=3,cores=3,threads=3 The expected core count = cores per socket = cores (3) * dies (3) = 9. Suggested-by: Igor Mammedov Signed-off-by: Zhao Liu Reviewed-by: Michael S. Tsirkin --- Changes since v1: * Added description of the consideration for topology selection of this case in commit message. (Igor) --- tests/qtest/bios-tables-test.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index cdbfb5155967..c20f6f73d09e 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -999,6 +999,23 @@ static void test_acpi_q35_tcg_type4_count(void) free_test_data(&data); } +static void test_acpi_q35_tcg_core_count(void) +{ + test_data data = { + .machine = MACHINE_Q35, + .variant = ".core-count", + .required_struct_types = base_required_struct_types, + .required_struct_types_len = ARRAY_SIZE(base_required_struct_types), + .smbios_core_count = 9, + .smbios_core_count2 = 9, + }; + + test_acpi_one("-machine smbios-entry-point-type=64 " + "-smp 54,sockets=2,dies=3,cores=3,threads=3", + &data); + free_test_data(&data); +} + static void test_acpi_q35_tcg_core_count2(void) { test_data data = { @@ -2178,6 +2195,8 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar); qtest_add_func("acpi/q35/type4-count", test_acpi_q35_tcg_type4_count); + qtest_add_func("acpi/q35/core-count", + test_acpi_q35_tcg_core_count); qtest_add_func("acpi/q35/core-count2", test_acpi_q35_tcg_core_count2); } From patchwork Mon Oct 23 09:46:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 1853611 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=AuEJ6KLG; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDVSz6QVSz23jn for ; Mon, 23 Oct 2023 20:36:51 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qurLN-0005wW-2v; Mon, 23 Oct 2023 05:35:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLM-0005wM-3k for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:28 -0400 Received: from mgamail.intel.com ([192.198.163.7]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLI-0005Hg-Ru for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:27 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698053725; x=1729589725; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RquOyGhpqU2wg5rCL84lj2sxhGi2DhSufg0c7JD3u80=; b=AuEJ6KLGq2/ySRk+L5CDNe0Vo3yLB5fTwaCquiPIwlAkiYmvJPvm1dEO u7uydOsDJ2nolF33R7aC8yekbTFio4pHlPUARoAqhW/COUhtD2LHQF9I2 fLWjvcT76+MZSL9/1YXcdY1GxauaiCeWR+rsy6d+Jhh0aVTn94vUpGxGD 18amOHU4/vC0zeEVJwWaKZPoWqjb9Wdt+Ims1gop8v0a4T1O6pWX2LYlP OLSEZueynMU04Q3x6BRmyyZeiB5cQE0x4oAodnGdqW+6IUSFX3XY0+EY7 h9jNJY0xuRKDuTBXh86fSydR9AwtUBbxCQ3vodiuhgNxWB9JpMPLEO5I2 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="8359633" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="8359633" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 02:35:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="707883223" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="707883223" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga003.jf.intel.com with ESMTP; 23 Oct 2023 02:35:19 -0700 From: Zhao Liu To: "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Eduardo Habkost , Yanan Wang Cc: Marcel Apfelbaum , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH v3 07/16] tests: bios-tables-test: Add ACPI table binaries for smbios type4 core count test Date: Mon, 23 Oct 2023 17:46:26 +0800 Message-Id: <20231023094635.1588282-8-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> References: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.198.163.7; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Zhao Liu Following the guidelines in tests/qtest/bios-tables-test.c, this is step 5 and 6. Changes in the tables: FACP: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-Y6WW91, Wed Aug 23 15:43:43 2023 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0002 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 1 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000484A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 1 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 ... APIC: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-FFXW91, Wed Aug 23 15:43:43 2023 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000220 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 3C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 [snip] +[1D4h 0468 1] Subtable Type : 00 [Processor Local APIC] +[1D5h 0469 1] Length : 08 +[1D6h 0470 1] Processor ID : 35 +[1D7h 0471 1] Local Apic ID : 6A +[1D8h 0472 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[1DCh 0476 1] Subtable Type : 01 [I/O APIC] +[1DDh 0477 1] Length : 0C +[1DEh 0478 1] I/O Apic ID : 00 +[1DFh 0479 1] Reserved : 00 +[1E0h 0480 4] Address : FEC00000 +[1E4h 0484 4] Interrupt : 00000000 + +[1E8h 0488 1] Subtable Type : 02 [Interrupt Source Override] +[1E9h 0489 1] Length : 0A +[1EAh 0490 1] Bus : 00 +[1EBh 0491 1] Source : 00 +[1ECh 0492 4] Interrupt : 00000002 +[1F0h 0496 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[1F2h 0498 1] Subtable Type : 02 [Interrupt Source Override] +[1F3h 0499 1] Length : 0A +[1F4h 0500 1] Bus : 00 +[1F5h 0501 1] Source : 05 +[1F6h 0502 4] Interrupt : 00000005 +[1FAh 0506 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[1FCh 0508 1] Subtable Type : 02 [Interrupt Source Override] +[1FDh 0509 1] Length : 0A +[1FEh 0510 1] Bus : 00 +[1FFh 0511 1] Source : 09 +[200h 0512 4] Interrupt : 00000009 +[204h 0516 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[206h 0518 1] Subtable Type : 02 [Interrupt Source Override] +[207h 0519 1] Length : 0A +[208h 0520 1] Bus : 00 +[209h 0521 1] Source : 0A +[20Ah 0522 4] Interrupt : 0000000A +[20Eh 0526 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[210h 0528 1] Subtable Type : 02 [Interrupt Source Override] +[211h 0529 1] Length : 0A +[212h 0530 1] Bus : 00 +[213h 0531 1] Source : 0B +[214h 0532 4] Interrupt : 0000000B +[218h 0536 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[21Ah 0538 1] Subtable Type : 04 [Local APIC NMI] +[21Bh 0539 1] Length : 06 +[21Ch 0540 1] Processor ID : FF +[21Dh 0541 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[21Fh 0543 1] Interrupt Input LINT : 01 ... DSDT: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of /tmp/aml-9ZXW91, Wed Aug 23 15:43:43 2023 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00003271 (12913) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0xAF + * OEM ID "BOCHS " + * OEM Table ID "BXPC " + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } [snip] + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + + If ((Arg0 == One)) + { + Notify (C001, Arg1) + } [snip] + If ((Arg0 == 0x35)) + { + Notify (C035, Arg1) + } + } [snip] + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + } [snip] + Processor (C035, 0x35, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x35)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x35, 0x6A, 0x01, 0x00, 0x00, 0x00 // ..5j.... + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x35) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x35, Arg0, Arg1, Arg2) + } + } ... Signed-off-by: Zhao Liu Reviewed-by: Michael S. Tsirkin --- tests/data/acpi/q35/APIC.core-count | Bin 0 -> 544 bytes tests/data/acpi/q35/DSDT.core-count | Bin 0 -> 12913 bytes tests/data/acpi/q35/FACP.core-count | Bin 0 -> 244 bytes tests/qtest/bios-tables-test-allowed-diff.h | 3 --- 4 files changed, 3 deletions(-) diff --git a/tests/data/acpi/q35/APIC.core-count b/tests/data/acpi/q35/APIC.core-count index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..d9d7ca9a896159791f6e74842d02786dc2608cb3 100644 GIT binary patch literal 544 zcmXxh*-pYh7(n5_rLA2+0RaKGf`EYgcISn(YQP%{EZ zC}OsRxiZdIaG{F%8W!qUO#f5d#RmIQ6U!~Ev~j6})h^b0SnuQV8LkX)HNv%XT))8Z z5*tHoj&S1&TM4$u*qPwwEq3p)caQxkZav`kBknxm?lbPa;QlKfyy4+H9(~~PC!Tz1 jjjVpV@0ngrUrimlY+ISr<$3?*s{?!sg0w8>S6%T3A7&l_ literal 0 HcmV?d00001 diff --git a/tests/data/acpi/q35/DSDT.core-count b/tests/data/acpi/q35/DSDT.core-count index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..a24b04cbdbf09383b933a42a2a15182545543a87 100644 GIT binary patch literal 12913 zcmb80O>A4)b;s}HheSP+5=BwpvPH|1Eq{unB-_)XMaV}|k}b+KDbGww1EeHRDtQ8g z&5VIK0|T}ONG1jfbVi+^OU*z5x=UBx)<8GyZgw4@t1i09HVEQXl>fQ+J-&1AlY!U^ z>YT@Oe&?J=^8I=5qsz_m_CFMauzp**@2oeor4Q>)7XK_E1ljaAwGnwFS})3_wYC)x zMXc7#xU}(5ie;{sOAptqf7$Q+y3_gemmO=TD|Ww4eZ9NW{rrp0uArc&yItERBXw`2 z-7K|RhZ{q6XCoJDuWytS#qaD`tnDZ(9BV(^D2vQyfBSyZiM;w)IOPxW$6L{({oxTi z)vEpP@*ihse(>uLJ}tifoB#RItB>sn0t)yW!{6mDJ#;?n*ylUPsjrR>tml+2pUWSQ ze03zBR>xBGOt(WvzDcMF^{sl&$>jy6Z#0Kz?U`SW3z48xPXGSx^z`&UlqpirL~1j0lTIF;xYmoh)7-Y= zuM>8x^)f|{gX0ggcqnIEFPfFRc&Yv?VMp*iwdmAiPNv{h?Z@$Xa`IZkQoVJ%zV zD1Vr3S*1mqrlr`>&u=svR!1Tk8d>F|ljTq`2ytSDl2>7nDsb~2@b zx;&rdzIQsIIBQfyo)Nkm(Lm3=8S7|#`QVj@;MXQoC$5tggz%+K4(&!GpWs))aQiD=N#1L9Mt9<)aQiD z=N!`J9Ma|-(&vQB=S*pHrnEUz`kZk2oWt6j!`hs~`kZk2oM~;&v^Hm2pA#;hb3~hS zM4NL&pA#;hGo#I!(dNwPbHe3wj%ss`YIBb2bHe3wj%jm_X>*S0bHe3wLdMiJOJ0@6 zwK>Q2IpOj-C$u>yv^gjAIpOj-CuL^Qy%J8!%#wStn^c*O?^0&jjh)gmr?ku|Jrgd^ zoYpd@wajTf6E4r3(K2VW%o#lsF3&utWuDVA&*_0RT`%S`VYe_myJ7jC$e z=_$#qR&!RXIjh%%t7^s|phYI2Yt0RmmSSqbMqyV#;h?N?!f?Ez5Kt8--$a(6EU!Nc zMOA1|K;e3$K|ockC!j2p1XP9g1Qag1@dQ-Gx*pX8)l*E$^v)OwC|q`2TvL*>ATyIVYsEU=D z5KtCM0;)n~CJ889Z%zoPij|oVP!>u8szPNZ2`F6e^@M<`SeXd{WuYXXDpY2YfWr0W zgn+78nF#@9p(LOxRA!QZ!u95afT~!T2?1rHB%mr(W|Dxy_2z_ts#uu`0cD{ipej^m zl7PbX=7fN%SeXd{WuYXXDpY2YfWr0Wgn+78nF#@9p(LOxRA!QZ!u95afT~!T2?1rH zB%mr(W|Dxy_2z_ts#uu`0cD{ipej^ml7PbX=7fN%SeXd{WuYXXDpY2YfWr0Wgn+78 znF#@9p(LOxRA!QZ!u95afT~!T2?1rHB%mr(W|Dxy_2z_ts#uu`0cD{ipej^ml7PbX z=7fN%SeXd{WuYXXDpY2YfWr0Wgn+78nF#@9p(LOxRA!QZ!u95afT~!T2?1rHB%mr( zW|Dxy_2z_ts#uu`0cD{ipej^ml7PbX=7fO4V*(0~3n*MJpm3RhvP=jl%OnA1nIxbr z69URIA)qXi1e9fxfU-;oD9eO^vP=?CmPrE2G9jQW69URINkCa92`I~ifWq@$T?i;V zykhcXl7Pa+%iy_`>782$C_L}nLO|hp=avK%u6J%pK;dE!WU37b6~~DqxmZ1+1?e|^ z^rx5^*?55U|M9?Q_KSUSVh^0y@yyD`1E(b-39NoiBPjF^M6y{}My#=J1$3@~c5H5QahtT!RI!rsA2%47HovMR7tc z)Ef_qnc;SMqbZ(~ZNHF5hG;{BBAkZw$J@e!jMz~^j4$Kjhr z0H=`YwXb1VC3k^ahwJvErLec*UT;*IUb{9f5@WZzbHjO;tg9w7TYW!q#Il^rL$r0fLQj3;iWV`)OknQ$A zNw(Yn6xnY7(`38-&yel*e~xUo|MO(K{m+u^_Me4aaQnYNw%h+4*>3+A$#(mnC)@3R zfo!+`OJuwKUnbk_f01mr|0`s>{a+>9?f)9tZvWTGcKg3Uw%h+rvfcid$aeeB!CrRz z&y(%;Um)A!YN zeSW(35bibwp4q&2(#h1K^qG3MLY9dF;Y@yJZOmypTd}u{5p%XGAEZO4U9s1-9)DX& zA3e6Z;&IpNbj8lMwZuOib*!)V>|28?bzLki&?MuL2 zu}7DiJrro=&mJzoLO)M;&pyw!0q1^mJMotDeD>QVz{kn!9-MJ*x^~DsN}*58gE-A+ zcGvp+4lYhP5*I-?74gQ7ozUAGm)}}(dpK^#1oq8nHI^B~eeLZy4I}msp0qx%M39=7 z3pFhji=bYrWy#cd+ZBhL#W0q{tP`eyjZdnP^gE!{Opg-^Nlv22u|xRE==EcVe9|)R zB$_0sbdMB{n4~Z#g?-WrwALhHjnN}Tq9!TANfDp4O3P4VIxH7@q-dW>igHraC*8uv zsY!yU_egy)lhnsaeLm?nHd0LzzQp%P{c;J8w}kh~+5Mc<@00G}4Puh;vxpukW}7|5 zI4S0n-jm;Q^moAkBMqcX(f}t7_@p8&`i(PgGm<@Ql59@0eNu_G4h&M9k>Y8S6z8P4 zPjc|}&?F@oDUmTr2~JA*q%t;YO;VDPlA|Um$w^6{RKdorNg8CN!7-CG$Vr1fsfvwU zlZ5ZDy?4RTgh?9Wq@f-upQF{AamKN}>yc8ECMm^9DW8<5MVdjv(ym7uo-#?poHXo{ z3bZ~mNLbbNNNM@ABmQYgb5hzTEz{D>AYnn*BaK`zdm7=S5uda|t1^RxwOo&snKMZl zPRjVCRa%f4BrM~4q|tekG|EY%KIs;%#S9Wwa6Qu4f=L?Vq%og#o0ee)35&NLY5bB& z8t0^OpL7Qs%O+`pktP;R(gY_>_@wu+(QJ|?8ENv0Nt)!ONuN~2om-PM#Yj_EP0|!6 zP5Gn}Hlj_^G$T#_z$8s`(zH)D&(?3QkIdjSOMdW%ak+ANm-wi zzYru{V5AG{Cg}nvUGPbTxgcqdk>)l`(i|tv`K0BGLDEG=x_H+lUF4*TK51n>NSbG) z`MOD(=cIX`w7L)^Eilr;1CzACNee#d)}(I>rkB}lr$NLSuBNmn@OicczD4U(=h($x=5(p65n>XS;> zf~0GVbnS;G=^7_p^GVM2An7_IUH?0ibe)r~`=s)XAn67p-RPL48=Q2*Csl3+NjDkk z=8j3a$w@bTQgtavT4JQ7U6ZuLNlQJ_vb&tq)>8Pva!)yPk4;jJlX5;OpAYtwXQcc` zCMnNJd7o4$1W5%(D*VVK6*#Hjla`l*q-920-Zx3hoV4tdR#t+f6-HV)Fi9(%wBnOi zSA(QgMp}Jhl2$os6{O5GHbSwf+pgpa!ri{5O;OsTN!3QxE~)%=uiO&88@K=ci=+st zCB-R~x7MsTi8l!=hT~R3u7dxFr{5%ceiAviIF z!kWNl`jtm0-&}5|`y#Yk0ehvLjz#Q{jZF!7tMm+wk@{=@WoRAVtbX9An;*#smD)q> zq7*3F=r|QkMQIB?RhfPyf1_QSqF1qX7;ols?O3~5ZeW_L&D?%F1(ZhPIb+~e`R7NxEKRAT3cS19{w<0F&(KV|hI>N%+?Xh@_zjGn^s?OK$ zKkQ`BbPo8!z`($~*~#D8BUr&HBEVSz2pEB4AU24G0Y(N+hD|^Y6El!tgNU*~X%LSC z$X0-fGcm9T0LA|E|L2FOWMD92VqjR>!otAF!NBm72Obk1 YBHITON2VDSAnpK(F*YFF1LDH~0O^Si0RR91 literal 0 HcmV?d00001 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index b9bc1961309a..dfb8523c8bf4 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,4 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/q35/APIC.core-count", -"tests/data/acpi/q35/DSDT.core-count", -"tests/data/acpi/q35/FACP.core-count", From patchwork Mon Oct 23 09:46:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 1853618 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=WKq1omln; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDVWT4CPFz23jn for ; Mon, 23 Oct 2023 20:39:01 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qurLP-0005x7-3W; Mon, 23 Oct 2023 05:35:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLN-0005wd-7N for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:29 -0400 Received: from mgamail.intel.com ([192.198.163.7]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLL-0005Jb-9i for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:28 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698053727; x=1729589727; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=D818Q5CyhBAcJKraZAXGH0Tc24je8m+TqG7hyARIZE4=; b=WKq1omlnK4iWf38BCyOBKy5loYiJQyI69DzSIpkI3Zy7UXt/pbS2GKIV 2gO04zXaJoPfI4kwIcmaGIaO4ekVyevGRnsjFlq7p9kZFHOLeSPUXJ2rE 8qYmQpJPfg97vzjWHRDNUwEhqGMKS492/Psec3L063pyqqm2hYtd/ffAC Y7PYd/WSbKGomJcpslRdd5D/iiONU4eIsXYF8yrocEMFDcK+NNfw6FQ09 PfQ/fFl6QsdCD2kpT6AeHXiwHsB7LhtbbuK6uR1SC5gPf/S/5zaLPcYpn Usm8dCayxX9bjfDRCgr0/YL9l5PfmylrGq0kA39rOhDpX6cHI9LRGeuSg Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="8359640" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="8359640" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 02:35:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="707883247" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="707883247" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga003.jf.intel.com with ESMTP; 23 Oct 2023 02:35:23 -0700 From: Zhao Liu To: "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Eduardo Habkost , Yanan Wang Cc: Marcel Apfelbaum , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH v3 08/16] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core count2 test Date: Mon, 23 Oct 2023 17:46:27 +0800 Message-Id: <20231023094635.1588282-9-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> References: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.198.163.7; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Zhao Liu Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be changed about the type 4 core count2 test case. Signed-off-by: Zhao Liu Reviewed-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test-allowed-diff.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8bf4..0f95d1344b2c 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,3 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/q35/APIC.core-count2", +"tests/data/acpi/q35/DSDT.core-count2", From patchwork Mon Oct 23 09:46:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 1853613 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=dDPrLY6M; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDVTH4m87z23jn for ; Mon, 23 Oct 2023 20:37:07 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qurLQ-0005xg-Bb; Mon, 23 Oct 2023 05:35:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLP-0005xH-9r for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:31 -0400 Received: from mgamail.intel.com ([192.198.163.7]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLN-0005Hg-FP for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:31 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698053730; x=1729589730; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4Dfu9ZqoPZTAoGtRyaqA9NaQufTr4E1/ifxw51jjGuI=; b=dDPrLY6Mpm1ttS1G6Xu8xxDM4E1pKzAh+j1d9Hwt29I2jZ1ydmi4DPLR viaGxTAZITei3DtEkb3W0KC5IHI2nqndhUkRg3uIwgMVJcW0NcwLL+Fis OtYhfNWmVrPsCXzcboK6yzeVLxWixVpTStj1VGpI5DSjKO1Rp0BPB3NWw WYa6EFTBVomlmxQv4bToNt4JCtk2bslPkdbUZguU2fefKR5NpbMnU4Xk3 veVYkXIZKrFEqI0oLQkhRJhmnW932ooWyV9Al6Kg3DSu3xy3UeD8DmqdN VkwRLl50PGCZz25bDsvzTSe53jYrAE6a6OdVZc51zO49sMmXCAdGHZjnu w==; X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="8359648" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="8359648" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 02:35:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="707883275" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="707883275" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga003.jf.intel.com with ESMTP; 23 Oct 2023 02:35:25 -0700 From: Zhao Liu To: "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Eduardo Habkost , Yanan Wang Cc: Marcel Apfelbaum , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH v3 09/16] tests: bios-tables-test: Extend smbios core count2 test to cover general topology Date: Mon, 23 Oct 2023 17:46:28 +0800 Message-Id: <20231023094635.1588282-10-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> References: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.198.163.7; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Zhao Liu The commit 196ea60a734c3 ("hw/smbios: Fix core count in type4") fixed the miscalculation of cores per socket. The original core count2 test (with the topology configured by "-smp 275") didn't recognize that topology-related but because it just created a special topology with only one socket and one die by default, ignoring the effect of more topology levels (between socket and core) on the cores per socket calculation. So for the topology in this case, there're the following considerations: 1. cores per socket should be more than 255 to ensure we could cover the core count2 field. 2. The original bug was that cores per socket was miscalculated, so now we should include as many topology levels as possible (multiple sockets or dies, no module since x86 hasn't supported it) to cover more general topology scenarios, to ensure that the cores per socket encoded in the core count2 field is correct. Based on these considerations, select the topology with multiple dies: -smp 260,dies=2,cores=130,threads=1 Note, here we doesn't configure multiple sockets to avoid the error ("kvm_init_vcpu: kvm_get_vcpu failed (*): Too many open files") if user uses the default ulimit seeting on his machine. And the cores per socket calculation for multiple sockets has already been covered by the core count test case, so that only multiple dies configuration is enough. The expected core count2 = cores per socket = cores (130) * dies (2) = 260. Suggested-by: Igor Mammedov Signed-off-by: Zhao Liu Acked-by: Igor Mammedov Reviewed-by: Michael S. Tsirkin --- Changes since v1: * Added description of the consideration for topology selection of this case in commit message. (Igor) --- tests/qtest/bios-tables-test.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index c20f6f73d09e..f3af20cf2c7f 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1024,10 +1024,12 @@ static void test_acpi_q35_tcg_core_count2(void) .required_struct_types = base_required_struct_types, .required_struct_types_len = ARRAY_SIZE(base_required_struct_types), .smbios_core_count = 0xFF, - .smbios_core_count2 = 275, + .smbios_core_count2 = 260, }; - test_acpi_one("-machine smbios-entry-point-type=64 -smp 275", &data); + test_acpi_one("-machine smbios-entry-point-type=64 " + "-smp 260,dies=2,cores=130,threads=1", + &data); free_test_data(&data); } From patchwork Mon Oct 23 09:46:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 1853614 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=nWCyISTd; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDVTg6mC5z23jn for ; Mon, 23 Oct 2023 20:37:27 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qurLW-00068M-ML; Mon, 23 Oct 2023 05:35:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLV-00063y-B6 for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:37 -0400 Received: from mgamail.intel.com ([192.198.163.7]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLR-0005P6-Mm for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:36 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698053734; x=1729589734; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1DK1irtwfUqkvzPMnw/BUwQ38cmxNI4XNtNTgvNgmEY=; b=nWCyISTdxTguEkxGczwOxS6AfxceB+ao4d9LTnEsW7epeGTpRKmNWk/s rvTvkaBBsbX5mttl4w8rTQjoXiwnnBSGNmNZpGHDnlG1qr118fkerbaSZ Ac4qqVrkO0nOYTrLbHzXo05yKt5ox2vH5eU5XQUhk4Lb0n/LQHldaxfRg d/LBqn3Z3q9kS83SQDcka7XyzWLEbyJPTFZJgo2349b2Y7H8q7pXWMsY4 iuq2U648pzpdQ681RoaL3ozpkqhloBG8iPt1cNcQRNZcyqHpINS52HnjH ff/ksfRT6xs0pjdukCKtTuzagY58ULmMrDpu2gdiAVOl0lLIzzukCf/e0 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="8359663" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="8359663" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 02:35:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="707883303" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="707883303" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga003.jf.intel.com with ESMTP; 23 Oct 2023 02:35:28 -0700 From: Zhao Liu To: "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Eduardo Habkost , Yanan Wang Cc: Marcel Apfelbaum , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH v3 10/16] tests: bios-tables-test: Update ACPI table binaries for smbios core count2 test Date: Mon, 23 Oct 2023 17:46:29 +0800 Message-Id: <20231023094635.1588282-11-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> References: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.198.163.7; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Zhao Liu Change the core count2 from 275 to 260. Following the guidelines in tests/qtest/bios-tables-test.c, this is step 5 and 6. Changes in the tables: APIC: /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/APIC.core-count2, Wed Aug 23 16:29:51 2023 + * Disassembly of /tmp/aml-KQDX91, Wed Aug 23 16:29:51 2023 * * ACPI Data Table [APIC] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] -[004h 0004 4] Table Length : 000009AE +[004h 0004 4] Table Length : 00000CA6 [008h 0008 1] Revision : 03 -[009h 0009 1] Checksum : CE +[009h 0009 1] Checksum : FA [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 4] Local Apic Address : FEE00000 [028h 0040 4] Flags (decoded below) : 00000001 PC-AT Compatibility : 1 [02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] [02Dh 0045 1] Length : 08 [02Eh 0046 1] Processor ID : 00 [02Fh 0047 1] Local Apic ID : 00 [030h 0048 4] Flags (decoded below) : 00000001 Processor Enabled : 1 @@ -1051,1256 +1051,1136 @@ [42Ch 1068 1] Subtable Type : 00 [Processor Local APIC] [42Dh 1069 1] Length : 08 [42Eh 1070 1] Processor ID : 80 [42Fh 1071 1] Local Apic ID : 80 [430h 1072 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Runtime Online Capable : 0 [434h 1076 1] Subtable Type : 00 [Processor Local APIC] [435h 1077 1] Length : 08 [436h 1078 1] Processor ID : 81 [437h 1079 1] Local Apic ID : 81 [438h 1080 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Runtime Online Capable : 0 -[43Ch 1084 1] Subtable Type : 00 [Processor Local APIC] -[43Dh 1085 1] Length : 08 -[43Eh 1086 1] Processor ID : 82 -[43Fh 1087 1] Local Apic ID : 82 -[440h 1088 4] Flags (decoded below) : 00000001 - Processor Enabled : 1 - Runtime Online Capable : 0 - -[444h 1092 1] Subtable Type : 00 [Processor Local APIC] -[445h 1093 1] Length : 08 -[446h 1094 1] Processor ID : 83 -[447h 1095 1] Local Apic ID : 83 -[448h 1096 4] Flags (decoded below) : 00000001 - Processor Enabled : 1 - Runtime Online Capable : 0 [snip] - -[964h 2404 1] Subtable Type : 01 [I/O APIC] -[965h 2405 1] Length : 0C -[966h 2406 1] I/O Apic ID : 00 -[967h 2407 1] Reserved : 00 -[968h 2408 4] Address : FEC00000 -[96Ch 2412 4] Interrupt : 00000000 - -[970h 2416 1] Subtable Type : 02 [Interrupt Source Override] -[971h 2417 1] Length : 0A -[972h 2418 1] Bus : 00 -[973h 2419 1] Source : 00 -[974h 2420 4] Interrupt : 00000002 -[978h 2424 2] Flags (decoded below) : 0000 +[43Ch 1084 1] Subtable Type : 09 [Processor Local x2APIC] +[43Dh 1085 1] Length : 10 +[43Eh 1086 2] Reserved : 0000 +[440h 1088 4] Processor x2Apic ID : 00000100 +[444h 1092 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[448h 1096 4] Processor UID : 00000082 + +[44Ch 1100 1] Subtable Type : 09 [Processor Local x2APIC] +[44Dh 1101 1] Length : 10 +[44Eh 1102 2] Reserved : 0000 +[450h 1104 4] Processor x2Apic ID : 00000101 +[454h 1108 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[458h 1112 4] Processor UID : 00000083 + [snip] + +[C68h 3176 1] Subtable Type : 02 [Interrupt Source Override] +[C69h 3177 1] Length : 0A +[C6Ah 3178 1] Bus : 00 +[C6Bh 3179 1] Source : 00 +[C6Ch 3180 4] Interrupt : 00000002 +[C70h 3184 2] Flags (decoded below) : 0000 Polarity : 0 Trigger Mode : 0 -[97Ah 2426 1] Subtable Type : 02 [Interrupt Source Override] -[97Bh 2427 1] Length : 0A -[97Ch 2428 1] Bus : 00 -[97Dh 2429 1] Source : 05 -[97Eh 2430 4] Interrupt : 00000005 -[982h 2434 2] Flags (decoded below) : 000D +[C72h 3186 1] Subtable Type : 02 [Interrupt Source Override] +[C73h 3187 1] Length : 0A +[C74h 3188 1] Bus : 00 +[C75h 3189 1] Source : 05 +[C76h 3190 4] Interrupt : 00000005 +[C7Ah 3194 2] Flags (decoded below) : 000D Polarity : 1 Trigger Mode : 3 -[984h 2436 1] Subtable Type : 02 [Interrupt Source Override] -[985h 2437 1] Length : 0A -[986h 2438 1] Bus : 00 -[987h 2439 1] Source : 09 -[988h 2440 4] Interrupt : 00000009 -[98Ch 2444 2] Flags (decoded below) : 000D +[C7Ch 3196 1] Subtable Type : 02 [Interrupt Source Override] +[C7Dh 3197 1] Length : 0A +[C7Eh 3198 1] Bus : 00 +[C7Fh 3199 1] Source : 09 +[C80h 3200 4] Interrupt : 00000009 +[C84h 3204 2] Flags (decoded below) : 000D Polarity : 1 Trigger Mode : 3 -[98Eh 2446 1] Subtable Type : 02 [Interrupt Source Override] -[98Fh 2447 1] Length : 0A -[990h 2448 1] Bus : 00 -[991h 2449 1] Source : 0A -[992h 2450 4] Interrupt : 0000000A -[996h 2454 2] Flags (decoded below) : 000D +[C86h 3206 1] Subtable Type : 02 [Interrupt Source Override] +[C87h 3207 1] Length : 0A +[C88h 3208 1] Bus : 00 +[C89h 3209 1] Source : 0A +[C8Ah 3210 4] Interrupt : 0000000A +[C8Eh 3214 2] Flags (decoded below) : 000D Polarity : 1 Trigger Mode : 3 -[998h 2456 1] Subtable Type : 02 [Interrupt Source Override] -[999h 2457 1] Length : 0A -[99Ah 2458 1] Bus : 00 -[99Bh 2459 1] Source : 0B -[99Ch 2460 4] Interrupt : 0000000B -[9A0h 2464 2] Flags (decoded below) : 000D +[C90h 3216 1] Subtable Type : 02 [Interrupt Source Override] +[C91h 3217 1] Length : 0A +[C92h 3218 1] Bus : 00 +[C93h 3219 1] Source : 0B +[C94h 3220 4] Interrupt : 0000000B +[C98h 3224 2] Flags (decoded below) : 000D Polarity : 1 Trigger Mode : 3 -[9A2h 2466 1] Subtable Type : 0A [Local x2APIC NMI] -[9A3h 2467 1] Length : 0C -[9A4h 2468 2] Flags (decoded below) : 0000 +[C9Ah 3226 1] Subtable Type : 0A [Local x2APIC NMI] +[C9Bh 3227 1] Length : 0C +[C9Ch 3228 2] Flags (decoded below) : 0000 Polarity : 0 Trigger Mode : 0 -[9A6h 2470 4] Processor UID : FFFFFFFF -[9AAh 2474 1] Interrupt Input LINT : 01 -[9ABh 2475 3] Reserved : 000000 +[C9Eh 3230 4] Processor UID : FFFFFFFF +[CA2h 3234 1] Interrupt Input LINT : 01 +[CA3h 3235 3] Reserved : 000000 ... DSDT: /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/q35/DSDT.core-count2, Wed Aug 23 16:29:51 2023 + * Disassembly of /tmp/aml-6DDX91, Wed Aug 23 16:29:51 2023 * * Original Table Header: * Signature "DSDT" - * Length 0x00007EEF (32495) + * Length 0x000083EA (33770) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x52 + * Checksum 0x01 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -4196,107 +4196,32 @@ } If ((Arg0 == 0x0101)) { Notify (C101, Arg1) } If ((Arg0 == 0x0102)) { Notify (C102, Arg1) } If ((Arg0 == 0x0103)) { Notify (C103, Arg1) } - - If ((Arg0 == 0x0104)) - { - Notify (C104, Arg1) - } - - If ((Arg0 == 0x0105)) - { - Notify (C105, Arg1) - } - - If ((Arg0 == 0x0106)) - { - Notify (C106, Arg1) - } - [snip] - If ((Arg0 == 0x0112)) - { - Notify (C112, Arg1) - } } Method (CSTA, 1, Serialized) { Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) \_SB.PCI0.PRES.CSEL = Arg0 Local0 = Zero If ((\_SB.PCI0.PRES.CPEN == One)) { Local0 = 0x0F } Release (\_SB.PCI0.PRES.CPLK) Return (Local0) } @@ -4306,33 +4231,33 @@ \_SB.PCI0.PRES.CSEL = Arg0 \_SB.PCI0.PRES.CEJ0 = One Release (\_SB.PCI0.PRES.CPLK) } Method (CSCN, 0, Serialized) { Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) Name (CNEW, Package (0xFF) {}) Local3 = Zero Local4 = One While ((Local4 == One)) { Local4 = Zero Local0 = One Local1 = Zero - While (((Local0 == One) && (Local3 < 0x0113))) + While (((Local0 == One) && (Local3 < 0x0104))) { Local0 = Zero \_SB.PCI0.PRES.CSEL = Local3 \_SB.PCI0.PRES.CCMD = Zero If ((\_SB.PCI0.PRES.CDAT < Local3)) { Break } If ((Local1 == 0xFF)) { Local4 = One Break } Local3 = \_SB.PCI0.PRES.CDAT @@ -7220,3281 +7145,3281 @@ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry { 0x00, 0x08, 0x81, 0x81, 0x01, 0x00, 0x00, 0x00 // ........ }) Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 { CEJ0 (0x81) } Method (_OST, 3, Serialized) // _OST: OSPM Status Indication { COST (0x81, Arg0, Arg1, Arg2) } } - Processor (C082, 0x82, 0x00000000, 0x00) + Device (C082) { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x82) // _UID: Unique ID Method (_STA, 0, Serialized) // _STA: Status { Return (CSTA (0x82)) } - Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry { - 0x00, 0x08, 0x82, 0x82, 0x01, 0x00, 0x00, 0x00 // ........ + /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, // ........ + /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x00 // ........ }) Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 { CEJ0 (0x82) } Method (_OST, 3, Serialized) // _OST: OSPM Status Indication { COST (0x82, Arg0, Arg1, Arg2) } } - Processor (C083, 0x83, 0x00000000, 0x00) + Device (C083) { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x83) // _UID: Unique ID Method (_STA, 0, Serialized) // _STA: Status { Return (CSTA (0x83)) } - Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry { - 0x00, 0x08, 0x83, 0x83, 0x01, 0x00, 0x00, 0x00 // ........ + /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, // ........ + /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x83, 0x00, 0x00, 0x00 // ........ }) Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 { CEJ0 (0x83) } Method (_OST, 3, Serialized) // _OST: OSPM Status Indication { COST (0x83, Arg0, Arg1, Arg2) } } - Processor (C084, 0x84, 0x00000000, 0x00) + Device (C084) { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x84) // _UID: Unique ID Method (_STA, 0, Serialized) // _STA: Status { Return (CSTA (0x84)) } - Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry { - 0x00, 0x08, 0x84, 0x84, 0x01, 0x00, 0x00, 0x00 // ........ + /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, // ........ + /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00 // ........ }) Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 { CEJ0 (0x84) } Method (_OST, 3, Serialized) // _OST: OSPM Status Indication { COST (0x84, Arg0, Arg1, Arg2) } } [snip] - Processor (C0FE, 0xFE, 0x00000000, 0x00) + Device (C0FE) { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0xFE) // _UID: Unique ID Method (_STA, 0, Serialized) // _STA: Status { Return (CSTA (0xFE)) } - Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry { - 0x00, 0x08, 0xFE, 0xFE, 0x01, 0x00, 0x00, 0x00 // ........ + /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x7C, 0x01, 0x00, 0x00, // ....|... + /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00 // ........ }) Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 { CEJ0 (0xFE) } Method (_OST, 3, Serialized) // _OST: OSPM Status Indication { COST (0xFE, Arg0, Arg1, Arg2) } } ... Signed-off-by: Zhao Liu Reviewed-by: Michael S. Tsirkin --- tests/data/acpi/q35/APIC.core-count2 | Bin 2478 -> 3238 bytes tests/data/acpi/q35/DSDT.core-count2 | Bin 32495 -> 33770 bytes tests/qtest/bios-tables-test-allowed-diff.h | 2 -- 3 files changed, 2 deletions(-) diff --git a/tests/data/acpi/q35/APIC.core-count2 b/tests/data/acpi/q35/APIC.core-count2 index f5da2eb1e8a93d961b39f665f2e8b02acf1aeb3c..4f2428443430b7da8321e9edd816219deb7929a2 100644 GIT binary patch literal 3238 zcmXxmby$@L7>4l=5IyGriroq-c6Un%f(43!4Ju%FCoFWS>+W#f-LAWJ9j?3EZMyH~ zdB%0*{(jUSTwd=(R#8FDzT_ZCIGkOWlV6;cT~d^j7QV#=LBKN&f4Y) zR}&J{TD8=~M74HpwN4#15>ca3H5OBolGNm6H6=x@TUV`DPfbl#>(^HsG*BBhR2wx? z8#h*)G*O#2RhuSZmv`|~NR9m%DTenu*v{Bo(RrPxbBI)UJyLM{(_G*U?YDR|I zv7_3lliInn+NF!ywX52#o7%m*+M|csv!~jtm)g6x+NY1&x3Ai-pW45_I$(f0aG*M9 zkUDsRrAyUi z%hct|)fFq$l`GX%tJKx2)irC>wQJRN>(uq@)eRfejT_ZXo7Byl)h%1pty|S?+tlsb z)g3$3ojcX4Dz&EHirqHX>*|PSvH3X zpKWun@HsYz3!iIq!0>rChYX)@bI|YwHir#gXmjB3MK*^HUu<*m@Fg~f4_|6?0P$ru zhY(+Gr`cE7>GqX22QqvGSJ@m&e6`KN#QW?F`x=`A%IB}OIi&bHn}dq4w>hl%2Aczm zZ?rkI_$Hf!i*L3$y!aNI1B`FAImGxjn}dvRw>ixC4x0mw@3cA8_%54+jqkQO-1r`w z1CH;tIpp|0n}d$;w>j+i0hL z0};N0Cv1iSKWQ@<_$fQre%j8npRpMdzW!O8LBY@23=4kVW?=9OHbaA7v>6=ylFjho zmu&_JzhW~)_*I)h!mrs36Mo%hpzr~kp~44k1`EGoGhFyhn*qab*$f$e+h)-4J2u0H z-?bSy{GQFw;rDF@4}V}YeE36~0mO%Fh7f;bm)alOW%egF0~x-8Pi=-0e`Yh7_;b75 z{=%-XzqBjuuWSZ2d<9?I3@iS|W?=ERHbaZQvl(3cz0L6AA8ZB~|7bJB_$Qk|#y{H( zGycV9pz*IZLydp48EpK!&2ZyCYz7?vX*1;bFPlNfhi!%(|7|ny_#d00$N$<4K0abI z{P?KN9{`wl>^*-7V0Io?+3Y;7wrh4inQz?Bj}GEv;XfXDN=yu!!c#Q*|5Ggd0(~qg Qspcsbe)rMvE&PGOe_jvc0RR91 literal 2478 zcmXZeWl$DT6oBC+KKO#RP*m&=4D137us{*TMz9O9Td}*lI}y7Jv9Q1{3{VuiJJ3D6 zcW3rK=bgE`Kkn?0^$7~_i#2JQO`>n0pMP*Z-_RhxeEMajX`0NUrln+LYSc8evO;TX zw6Q^3TQnHZ&JOME(P%`I3C(7-SkS=%9Ualh37wtM#RXkm(ajCBWWlUiFfD+ZQ7vv0p!oio*W=alil^I1mR7!oh=a z$PgSl6o(DN;lpvn2pl;QM~%YKqjAg_96J`HqjB6g96uf>Ou&f~andB5JQ=48~5zNy?b%rKHR?_4;;XQ2l3D$JbW0B9KoYU@z^muejHDnz>_C2E)Gwf!uWVR zeHzc4!Lw)a+&Mgd9upGq!Ueo|5iecB%a`%W6--RTq$Iq06|Y^x>(}wd4ZL|1Z{5P% zxAD#$yn7e#-NXC$F*z9@Jivz!@zEoE{1{VGFf|pQJi(_=F)awzkI>3U-8>F{Qez({J@_-@z*c>{Tu)M z!M}eoBSSQ~XxcwrnMG-d%su)dZKYb2wpJ}l+o%?$ZB>iX2GydpooZ3qUbQG~R4q!I zREyGP)uOaTwJ7bNT9kHFElNA77Nwn4i_$KtMQK;nqO_apOda&|(&92?wKnUw3^ExE cx{flL^j|P0v%Z1JV#%D$`qTgPOMjvEANV#K5C8xG diff --git a/tests/data/acpi/q35/DSDT.core-count2 b/tests/data/acpi/q35/DSDT.core-count2 index b47891ec10be131a59bf404242241c054ac902f8..3a0cb8c581c8cc630a2ec21712b7f8b75fcad1c8 100644 GIT binary patch delta 7005 zcmZA0cUaYR6vuHcmD)`M6Dpcop=68FRGPxQSQ+I2Hwg|D$rMA)wuyop<*2xEptuoH zapMFxZrr$095})Kguios=lOl^^YGliczw_J`#aCOJ%_q}6KALiUeBHm>ly%joe&wv9npJESpSH!iMaFibUbVckJpBA>RUFW;g2TVT zClndy?K{A$NU%Zdp_&wR(`he=Qe;Mo750h$58R0;z8L& z#nU`hbqzHT)Id<~q6X4!Ri7Ga5U4?*o)R^PzG`aTu-+5pkpL=z`uFj+CD35~uli5^ zD0Se@J~r_bQL)|$z@eZ)>S3xssd<3T=}X-QPWV})$?-1DC!<6ZwmO>c++SYJQ@aj zh#F1HRdH9zpprp(ib_rnGe>b&1c(4t6-3ln6=yXD)EH1Nh#EsWyrgN&e zvnimafO=Kb6#B50`7Wa~->IOcf_hEVRO;7Cx(lEu-K7Fb1@yY0RF~bQT6dSKy9?y* zrqT6Qy1O^zh-p;0wcIw4yPFP!r^DbkMNOxcs<^uupk{!oE@}o%Q^n!U1T_;>4N)_x zSQUqt1}Y8ITcXmaZX5Gm9NsKYvp~HqY8L&Yio=@?YBs2MM9rqHsyMuKQ0bt2MWwqe zFWtJlbj$LL@a9m%wz|BUa>N`8Z)-l1!P=?FyGOWAH(A@=bc#CONxbE&lIbty_2$wGt#NlPa;7l0&k*G{6RmI^g z0ks5_zo;eD@F#N?hnEE^3)IJ=vS_F(4sR)_rJz0$wUiF1;_#M%S_Z0)sAcpwf=;#9<<*lTR?tHo%;Bws!7E{K zeNii^QH1$O4sR8xRiGM(T1BH&ad@jitp*h!YBe2I#o?_1wFcB@qSnwmk>(9KytSa# zg8E$4TI!*S!&?Vx9jGrvt)mr@5?+uIUJjrfKwk>VaoJstb$2B9ad832F+W><%z~HY%ZJ=?gIJ}LZHiBv>Y9pOe#o=uNwFy+9s7+M6qj^IPZ!@UP zpn^ngrrxSJye*)%fO3f1LhDpQ1etb;kcZ7_Hn4E{#cHoBmS!`lvOJE(6(Z72WE<|8@09iVoA`cBji z`a>0mw-eM(P>n_Hq|K^0yj`Gnf%;z5E_y!7ydj6T8`N%4A)nI7&VT6|tC?C)d zg7RH~2DcJ*gc4M7 zct=4U1=U*AQQD)5!#f7*7^pU)j?pXK%o}oe$3Yzj)mGGT>a2>xI|1qhsCJ@G&>~eF z-bqj=L4}JtNq4(Rcupg{LO_LpeiBsZvb#d-?h18x!5rQxijC3TwU;AK(eN1gGQk|) zX&8JO21kfGO@~x*cxOPJ0Tn6g3|0TxoWLltsJyylxT>y0fRA*5a=-ck*yEwceP(`4kL>0L#ugJQ*BFplO@GjE&?z+4# za>PYCu7f$eOECBn4DKrG64m_0ye@}V45}DZw5Vc=RmI_526Y)!H&K^ql`0PJ3aBff zVnkh`r+b(;{jqpkUl>quhP>IX#O02sp z(cLxT@UD|*Pu*P)IpR9K-&5Y$h{L-9gKxm#o}zA0UsW95O;9&M#frK~>s4`hw?N$j z)l1YZvd5Y?(_VCF(IX ph->5iw~Z*SqwOCmjf=AVOX0nvZ2f6t`R{+^*Qa(?$e%Nx`XBpVSA+ln delta 7056 zcmZYDc~DjN6~J*03Oso1!Zc1N({Y@{rcS5tJ(l<0bUK~4HeDh`u|}<1j8RN%v^J(T zMiWs%al_-jf}p5~im0f#;l3m8yW+kf?mMP;`~7mRhd;P;=6&w>{_gqn-pLJZY=S6% z2Y*)M@Q@H_UlA42GBm$6wrE)qn)e>=Zuvpz-)buxS~{ag6h>n|YjYUmv)fX$wINI! z()1x*8`AY5LK~d=V9^GbK16DRTOXpd!J`jWZSd+tv^MzkAx0hA+5GwxtNj$vhd6Br z>O;Ib*lqfdpbd6?NYn;LcGAb;z7AQQ$gZu?^XnG4?8Eo4^M|LQMWv&Sw@pmW$IX2< zmt$mz`iBMWk}TFJONeFUNWiu2T79JdoRXvcoD|bT30X?iTvU#w$0wew1Wo7U0RAFF z=+seMk0N^1D8Qjor;X-%G|{6+1D=yQeGJ!Qh#oTr@DG0%CvoO-olA6XF5m*GU3pyR z5uKL@2$`bo9?SJuqQ{N}?48-lSg>cDrm-l~Sn#-UfV*VOo6lqUB$l5K*rvUBv~N7u zy+BB}G5j|}h;A^SVr*l1>=;_k|yZu9)#5sfO8AQ*R0k~Ca*G#Tw58!0R&Rox@{uNNmm=z(0K|9_^dU^<1Lo&IMd5 zwSOMh^N5}|5763Kv;*_Go=^1r`G5nY4ldw&0nrN<0M-iau@!P%NOWN#puLN65|6!z z>ms6yiU6^Tv0#s5p{B8}i?QH^3jv?XSV}RE6_Z$TF<_^z;?b!kT$d1CQUbU^>a;~% zFCu!;BEVn%Q?%0;bG?}8#ft&Im)cp%bt%!MrGS^Db}iw03DHZI0D8KKlem|1y_D#s zO96|!i3NL>X&URh84F&v3^1&_hnH_RaOFiD|PA`uGbK~W)0vOsngbSy_V>;YXN`% znK()MI1=gJgJ>kTvriYRR#Ey)UNehuP1u_dca=2#Yx;7xZXhYh7Eu_dW!{n zHfkE-b7R39Hv)d}xrlkId90ems;dEWrS@&&dK1x`HUZw2+P|6W%|vhB4EWbR;v|7B zTyG(I%ND?Lse@a&-b(b=t$=Y~7;T?z8`s;2-nI>Jkks}Xu4{;{sR2Cpg|T3tW4op? zp|7#v?b`v<`ie)V?BKB-B(`G*;0&o#cXGXx=$$(OUrL>}i|buP@7e{}wVyai`fjdw z6TN#k;AW|vd$`_1^qxI{zseSE*Iuso61{gX;Ez(f_i??C=zaSDuV#w{d-iJ@TlF^< zynjDnpuc#u_W+L_Ah81n086Fz9pw5T(FYF#Mt&*U{zF_JBKpuFz%Qi^9On8k(T5KM z9+Em(%XKZ$wY7l1`^q?p-*$xSBSarL0$3omy^iZTqU-7aAAe;m*zY*1X|xY87JT$5 zV8;RC(J9Ax>==n1I|f)Kb?R}hj}v|TIAF_viFVovu1^qs;soG#Qm3Ef`XtdOPXb<$ z+IfoWQ$(LS1^CCW#YtSJxjs$w>C=EkQoGM^eTL{WX8@ZG6bts8)iinr8Vf#q7O>Ai z@o4Wk9y>>3=gtA{k=l2j>+?jPKM(lPAkp?;;Q9j57cKziOC7k#^+lpDUIc8AI(Uie zOGIC~1eoz}<0JvwWv(w1efctAh1B+XuIq`euLo=~*jRADaYfUZIoMe6l`DYX3>J@0 zxyoZ#N$l!Xz*ADEUgP>2(buj4y8k2EY1g^FPW1KbfODiyzrpnlqHo*)Y?9h}lk1yA z-@FOf;~Q}j*DbDZ5q;|xV2#x7+g#r!`u1(W)nB7%c>>t^f1;iClVEp_@cuAdS8>>1$u--)*KIoHpLe*PSA zgw(DVT)!at#S6fCsogKReo6Gpmw>)uV!@tQn#Lc884G^(3UJXdaZvAT9(zqH31%wI`Ee3w?w~v3;5gNokM>L!Mx$0;qrDCd^Ef} z#%5UX(-GYv6stz`foAyr55KW=9qA8OKSN_tMpCBoO*$#|=Z~?^cady3$vX9HggF~w&PEtn^-8nKT_hVpvMx27XtkKL z7Uc_OW^!B0I~hfhjD=*}dM47GiBvvqwoh&w`A$YrBoj$89{nYw%$X?jOGX(lsb1+z zDtD1=6v=w^tks;gnzL3Tt6phVxr=12B^cadx~$@=wdj5!-) z&c+y7^-8nKT_hVrvH?9CYtF`+v#~~2z0$057sx diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index 0f95d1344b2c..dfb8523c8bf4 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,3 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/q35/APIC.core-count2", -"tests/data/acpi/q35/DSDT.core-count2", From patchwork Mon Oct 23 09:46:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 1853609 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=Qf5eDrRw; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDVSk6XCxz23jn for ; Mon, 23 Oct 2023 20:36:38 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qurLZ-0006JL-4G; Mon, 23 Oct 2023 05:35:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLW-00068s-RU for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:38 -0400 Received: from mgamail.intel.com ([192.198.163.7]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLV-0005QU-7A for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:38 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698053737; x=1729589737; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8zSsK4SlR4Uv7Qd+gGqw0d5/oesTmjs5A3WGsggIjz0=; b=Qf5eDrRwr2Bdmmvpql/MG5qXpGFXnOXuqVuExyupG2T0Jbe1wW1qUQ84 OtMYJTNY7z5+8zelPtnXNfdHMp/YypkHaK3o85+DXtb5FNlmilVMTr+by Exql82NCVlrTrmhIDjlUO2y1Cu+2y/DhK6NjBkNvYuWLxRwxnyZ26tGhg n/ZbfR/Gl8S31jNtlAPYJM0gE1PTQf9t9ojwfnQifbdZreWAgc3A/0YaN PB4JyybI96K3E4s0YuB9tgP0JmmWmuDbRvBHRxqi4ocRK3ww8mnYusryc OyiuG7fNxbGyoBXolZnYnjn1Vw5+9OgYJ3XPzI2x3IZbWRRa2FSo8Yce3 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="8359668" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="8359668" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 02:35:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="707883313" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="707883313" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga003.jf.intel.com with ESMTP; 23 Oct 2023 02:35:32 -0700 From: Zhao Liu To: "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Eduardo Habkost , Yanan Wang Cc: Marcel Apfelbaum , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH v3 11/16] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 thread count test Date: Mon, 23 Oct 2023 17:46:30 +0800 Message-Id: <20231023094635.1588282-12-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> References: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.198.163.7; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Zhao Liu Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be added to test the thread count field of smbios type4 table. Signed-off-by: Zhao Liu Reviewed-by: Michael S. Tsirkin --- tests/data/acpi/q35/APIC.thread-count | 0 tests/data/acpi/q35/DSDT.thread-count | 0 tests/data/acpi/q35/FACP.thread-count | 0 tests/qtest/bios-tables-test-allowed-diff.h | 3 +++ 4 files changed, 3 insertions(+) create mode 100644 tests/data/acpi/q35/APIC.thread-count create mode 100644 tests/data/acpi/q35/DSDT.thread-count create mode 100644 tests/data/acpi/q35/FACP.thread-count diff --git a/tests/data/acpi/q35/APIC.thread-count b/tests/data/acpi/q35/APIC.thread-count new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/tests/data/acpi/q35/DSDT.thread-count b/tests/data/acpi/q35/DSDT.thread-count new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/tests/data/acpi/q35/FACP.thread-count b/tests/data/acpi/q35/FACP.thread-count new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8bf4..4d139d7f6b7e 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,4 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/q35/APIC.thread-count", +"tests/data/acpi/q35/DSDT.thread-count", +"tests/data/acpi/q35/FACP.thread-count", From patchwork Mon Oct 23 09:46:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 1853617 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=S09GylOg; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDVW93mkZz23kg for ; Mon, 23 Oct 2023 20:38:45 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qurLa-0006MR-8x; Mon, 23 Oct 2023 05:35:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLZ-0006JO-0Z for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:41 -0400 Received: from mgamail.intel.com ([192.198.163.7]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLW-0005P6-LK for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:40 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698053739; x=1729589739; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4BGoKnd1jrMIKcwElK4O/5OBKEiHI0ReCU0Rx3sh55Y=; b=S09GylOgNrYUMagUgh0gxko1WT3yVovPcxV0ci4t08pCSQHC19XXuNvr ZcGOd8N4Hg5RwKgQs5GxGRI3+atETxxAEISwR8ihP9EGGk9TbCQuzqs3s pVHoxa72hlXI47o9elansdo8gnaCXZgrxEBKLtolX7D5/rPawm+syGlaq sHUGZnFpCYWfiiuzlsrUTB02TV/adioF9R7SfGDl7GMha3MfKgE+zLb6Z WCajmYO9DUUIdqFcDGSeqNNCmmsdyMB+Ni8ZwbQFRbKkU0gdoqB0EK0hF x+rsm6+0IykOMhajVvKPpsN8jR2aL+Gsx7tmAZ+V0uL/ON4TaXG1XHduH Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="8359676" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="8359676" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 02:35:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="707883336" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="707883336" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga003.jf.intel.com with ESMTP; 23 Oct 2023 02:35:34 -0700 From: Zhao Liu To: "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Eduardo Habkost , Yanan Wang Cc: Marcel Apfelbaum , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH v3 12/16] tests: bios-tables-test: Add test for smbios type4 thread count Date: Mon, 23 Oct 2023 17:46:31 +0800 Message-Id: <20231023094635.1588282-13-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> References: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.198.163.7; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Zhao Liu This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in type4"). In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of threads in the socket is not more than 255, then smbios type4 table encodes threads per socket into the thread count field. So for the topology in this case, there're the following considerations: 1. threads per socket should be not more than 255 to ensure we could cover the thread count field. 2. The original bug was that threads per socket was miscalculated, so now we should configure as many topology levels as possible (multiple sockets & dies, no module since x86 hasn't supported it) to cover more general topology scenarios, to ensure that the threads per socket encoded in the thread count field is correct. 3. For the more general topology, we should also add "cpus" (presented threads for machine) and "maxcpus" (total threads for machine) to make sure that configuring unpluged CPUs in smp (cpus < maxcpus) does not affect the correctness of threads per socket for thread count field. Based on these considerations, select the topology as the follow: -smp cpus=15,maxcpus=54,sockets=2,dies=3,cores=3,threads=3 The expected thread count = threads per socket = threads (3) * cores (3) * dies (3) = 27. Suggested-by: Igor Mammedov Signed-off-by: Zhao Liu Reviewed-by: Michael S. Tsirkin --- Changes since v1: * Added description of the consideration for topology selection of this case in commit message. (Igor) --- tests/qtest/bios-tables-test.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index f3af20cf2c7f..395ed7f9ff73 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -95,6 +95,7 @@ typedef struct { uint16_t smbios_cpu_curr_speed; uint8_t smbios_core_count; uint16_t smbios_core_count2; + uint8_t smbios_thread_count; uint8_t *required_struct_types; int required_struct_types_len; int type4_count; @@ -640,6 +641,7 @@ static void smbios_cpu_test(test_data *data, uint32_t addr, SmbiosEntryPointType ep_type) { uint8_t core_count, expected_core_count = data->smbios_core_count; + uint8_t thread_count, expected_thread_count = data->smbios_thread_count; uint16_t speed, expected_speed[2]; uint16_t core_count2, expected_core_count2 = data->smbios_core_count2; int offset[2]; @@ -663,6 +665,13 @@ static void smbios_cpu_test(test_data *data, uint32_t addr, g_assert_cmpuint(core_count, ==, expected_core_count); } + thread_count = qtest_readb(data->qts, + addr + offsetof(struct smbios_type_4, thread_count)); + + if (expected_thread_count) { + g_assert_cmpuint(thread_count, ==, expected_thread_count); + } + if (ep_type == SMBIOS_ENTRY_POINT_TYPE_64) { core_count2 = qtest_readw(data->qts, addr + offsetof(struct smbios_type_4, core_count2)); @@ -1033,6 +1042,22 @@ static void test_acpi_q35_tcg_core_count2(void) free_test_data(&data); } +static void test_acpi_q35_tcg_thread_count(void) +{ + test_data data = { + .machine = MACHINE_Q35, + .variant = ".thread-count", + .required_struct_types = base_required_struct_types, + .required_struct_types_len = ARRAY_SIZE(base_required_struct_types), + .smbios_thread_count = 27, + }; + + test_acpi_one("-machine smbios-entry-point-type=64 " + "-smp cpus=15,maxcpus=54,sockets=2,dies=3,cores=3,threads=3", + &data); + free_test_data(&data); +} + static void test_acpi_q35_tcg_bridge(void) { test_data data = {}; @@ -2201,6 +2226,8 @@ int main(int argc, char *argv[]) test_acpi_q35_tcg_core_count); qtest_add_func("acpi/q35/core-count2", test_acpi_q35_tcg_core_count2); + qtest_add_func("acpi/q35/thread-count", + test_acpi_q35_tcg_thread_count); } if (qtest_has_device("virtio-iommu-pci")) { qtest_add_func("acpi/q35/viot", test_acpi_q35_viot); From patchwork Mon Oct 23 09:46:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 1853616 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=g87muBge; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDVW83Q0vz23jn for ; Mon, 23 Oct 2023 20:38:44 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qurLr-0006xv-W5; Mon, 23 Oct 2023 05:36:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLn-0006lC-Qz for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:56 -0400 Received: from mgamail.intel.com ([192.198.163.7]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLk-0005VZ-Qn for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:55 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698053753; x=1729589753; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/nGKjEx59S9NXDZki4edM86tdgrexQLckBOgnP33VMg=; b=g87muBgespCfKZhymKhk37bs+HIwC8ldn35kxVf2PxkU/y1VZ/Fj7YvX bHpLJacn7c3ee73GXsEsEUWw0AB3t63xz3o3/y6QdDGGPUXQmLv6bVNKr myKZ798ujLFStn3iJkGmtMULT9HJ+6qFRhxZ7vrrEjHRGpQUs8XBwWY9t p0cCJ7UrkCEDGJUpULg7YwyiG5O0zT4+EatfRwgSdXnveKoUN/HbCCYQU HF1VByKQJpiU2I5qc6LQ6xyHpOay8wkHXRopo/lirK/J8OUYTg/IvCTNb yyW/glBU6d7MPlJO1gNLkOriRZqKOtTB+oCgO6WnAujL77ttUfx0/e773 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="8359688" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="8359688" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 02:35:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="707883353" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="707883353" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga003.jf.intel.com with ESMTP; 23 Oct 2023 02:35:37 -0700 From: Zhao Liu To: "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Eduardo Habkost , Yanan Wang Cc: Marcel Apfelbaum , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH v3 13/16] tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count test Date: Mon, 23 Oct 2023 17:46:32 +0800 Message-Id: <20231023094635.1588282-14-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> References: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.198.163.7; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Zhao Liu Following the guidelines in tests/qtest/bios-tables-test.c, this is step 5 and 6. Changes in the tables: FACP: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-1NP791, Wed Aug 23 21:51:31 2023 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0002 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 1 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000484A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 1 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 ... APIC: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-2JP791, Wed Aug 23 21:51:31 2023 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000220 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 63 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 [snip] +[1D4h 0468 1] Subtable Type : 00 [Processor Local APIC] +[1D5h 0469 1] Length : 08 +[1D6h 0470 1] Processor ID : 35 +[1D7h 0471 1] Local Apic ID : 6A +[1D8h 0472 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[1DCh 0476 1] Subtable Type : 01 [I/O APIC] +[1DDh 0477 1] Length : 0C +[1DEh 0478 1] I/O Apic ID : 00 +[1DFh 0479 1] Reserved : 00 +[1E0h 0480 4] Address : FEC00000 +[1E4h 0484 4] Interrupt : 00000000 + +[1E8h 0488 1] Subtable Type : 02 [Interrupt Source Override] +[1E9h 0489 1] Length : 0A +[1EAh 0490 1] Bus : 00 +[1EBh 0491 1] Source : 00 +[1ECh 0492 4] Interrupt : 00000002 +[1F0h 0496 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[1F2h 0498 1] Subtable Type : 02 [Interrupt Source Override] +[1F3h 0499 1] Length : 0A +[1F4h 0500 1] Bus : 00 +[1F5h 0501 1] Source : 05 +[1F6h 0502 4] Interrupt : 00000005 +[1FAh 0506 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[1FCh 0508 1] Subtable Type : 02 [Interrupt Source Override] +[1FDh 0509 1] Length : 0A +[1FEh 0510 1] Bus : 00 +[1FFh 0511 1] Source : 09 +[200h 0512 4] Interrupt : 00000009 +[204h 0516 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[206h 0518 1] Subtable Type : 02 [Interrupt Source Override] +[207h 0519 1] Length : 0A +[208h 0520 1] Bus : 00 +[209h 0521 1] Source : 0A +[20Ah 0522 4] Interrupt : 0000000A +[20Eh 0526 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[210h 0528 1] Subtable Type : 02 [Interrupt Source Override] +[211h 0529 1] Length : 0A +[212h 0530 1] Bus : 00 +[213h 0531 1] Source : 0B +[214h 0532 4] Interrupt : 0000000B +[218h 0536 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[21Ah 0538 1] Subtable Type : 04 [Local APIC NMI] +[21Bh 0539 1] Length : 06 +[21Ch 0540 1] Processor ID : FF +[21Dh 0541 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[21Fh 0543 1] Interrupt Input LINT : 01 ... DSDT: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of /tmp/aml-00O791, Wed Aug 23 21:51:31 2023 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00003271 (12913) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0xAF + * OEM ID "BOCHS " + * OEM Table ID "BXPC " + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } [snip] + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + } [snip] + Processor (C035, 0x35, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x35)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x35, 0x6A, 0x01, 0x00, 0x00, 0x00 // ..5j.... + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x35) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x35, Arg0, Arg1, Arg2) + } + } ... Signed-off-by: Zhao Liu Reviewed-by: Michael S. Tsirkin --- tests/data/acpi/q35/APIC.thread-count | Bin 0 -> 544 bytes tests/data/acpi/q35/DSDT.thread-count | Bin 0 -> 12913 bytes tests/data/acpi/q35/FACP.thread-count | Bin 0 -> 244 bytes tests/qtest/bios-tables-test-allowed-diff.h | 3 --- 4 files changed, 3 deletions(-) diff --git a/tests/data/acpi/q35/APIC.thread-count b/tests/data/acpi/q35/APIC.thread-count index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..c27e87fcf1c04a2e75f9a20f2bc6a28f19aadf66 100644 GIT binary patch literal 544 zcmXxe*-pYh7(n4^X=@iyb^*5m0Ri{zURpKajdcxrrJx3VN*;wLL1%j6B=dhKlgVWI z@i3C65UELc8x0<0IEo{wmLY`DtrcRvNOXlj!$8x-l!ca!wu6p~OCGvDdRg>y800Zs z#7qg7%eYcWzTsx8n5$u4Vxf-329}ywZsBShD;=zMvDU-23taExMu?l2xOIi{8tVgW z3~~Dgn=!WTuzim^kJx#_?lbmAxch>8uekq)2k&?|#-k5B{=}0nJe}g%H=h4!jkKP# eg`TFbwhmpkt<321y#Mmm1A4)b;s}HheSP+5=BwpvPH|1Eq{unB-_)XMaV}|k}b+KDbGww1EeHRDtQ8g z&5VIK0|T}ONG1jfbVi+^OU*z5x=UBx)<8GyZgw4@t1i09HVEQXl>fQ+J-&1AlY!U^ z>YT@Oe&?J=^8I=5qsz_m_CFMauzp**@2oeor4Q>)7XK_E1ljaAwGnwFS})3_wYC)x zMXc7#xU}(5ie;{sOAptqf7$Q+y3_gemmO=TD|Ww4eZ9NW{rrp0uArc&yItERBXw`2 z-7K|RhZ{q6XCoJDuWytS#qaD`tnDZ(9BV(^D2vQyfBSyZiM;w)IOPxW$6L{({oxTi z)vEpP@*ihse(>uLJ}tifoB#RItB>sn0t)yW!{6mDJ#;?n*ylUPsjrR>tml+2pUWSQ ze03zBR>xBGOt(WvzDcMF^{sl&$>jy6Z#0Kz?U`SW3z48xPXGSx^z`&UlqpirL~1j0lTIF;xYmoh)7-Y= zuM>8x^)f|{gX0ggcqnIEFPfFRc&Yv?VMp*iwdmAiPNv{h?Z@$Xa`IZkQoVJ%zV zD1Vr3S*1mqrlr`>&u=svR!1Tk8d>F|ljTq`2ytSDl2>7nDsb~2@b zx;&rdzIQsIIBQfyo)Nkm(Lm3=8S7|#`QVj@;MXQoC$5tggz%+K4(&!GpWs))aQiD=N#1L9Mt9<)aQiD z=N!`J9Ma|-(&vQB=S*pHrnEUz`kZk2oWt6j!`hs~`kZk2oM~;&v^Hm2pA#;hb3~hS zM4NL&pA#;hGo#I!(dNwPbHe3wj%ss`YIBb2bHe3wj%jm_X>*S0bHe3wLdMiJOJ0@6 zwK>Q2IpOj-C$u>yv^gjAIpOj-CuL^Qy%J8!%#wStn^c*O?^0&jjh)gmr?ku|Jrgd^ zoYpd@wajTf6E4r3(K2VW%o#lsF3&utWuDVA&*_0RT`%S`VYe_myJ7jC$e z=_$#qR&!RXIjh%%t7^s|phYI2Yt0RmmSSqbMqyV#;h?N?!f?Ez5Kt8--$a(6EU!Nc zMOA1|K;e3$K|ockC!j2p1XP9g1Qag1@dQ-Gx*pX8)l*E$^v)OwC|q`2TvL*>ATyIVYsEU=D z5KtCM0;)n~CJ889Z%zoPij|oVP!>u8szPNZ2`F6e^@M<`SeXd{WuYXXDpY2YfWr0W zgn+78nF#@9p(LOxRA!QZ!u95afT~!T2?1rHB%mr(W|Dxy_2z_ts#uu`0cD{ipej^m zl7PbX=7fN%SeXd{WuYXXDpY2YfWr0Wgn+78nF#@9p(LOxRA!QZ!u95afT~!T2?1rH zB%mr(W|Dxy_2z_ts#uu`0cD{ipej^ml7PbX=7fN%SeXd{WuYXXDpY2YfWr0Wgn+78 znF#@9p(LOxRA!QZ!u95afT~!T2?1rHB%mr(W|Dxy_2z_ts#uu`0cD{ipej^ml7PbX z=7fN%SeXd{WuYXXDpY2YfWr0Wgn+78nF#@9p(LOxRA!QZ!u95afT~!T2?1rHB%mr( zW|Dxy_2z_ts#uu`0cD{ipej^ml7PbX=7fO4V*(0~3n*MJpm3RhvP=jl%OnA1nIxbr z69URIA)qXi1e9fxfU-;oD9eO^vP=?CmPrE2G9jQW69URINkCa92`I~ifWq@$T?i;V zykhcXl7Pa+%iy_`>782$C_L}nLO|hp=avK%u6J%pK;dE!WU37b6~~DqxmZ1+1?e|^ z^rx5^*?55U|M9?Q_KSUSVh^0y@yyD`1E(b-39NoiBPjF^M6y{}My#=J1$3@~c5H5QahtT!RI!rsA2%47HovMR7tc z)Ef_qnc;SMqbZ(~ZNHF5hG;{BBAkZw$J@e!jMz~^j4$Kjhr z0H=`YwXb1VC3k^ahwJvErLec*UT;*IUb{9f5@WZzbHjO;tg9w7TYW!q#Il^rL$r0fLQj3;iWV`)OknQ$A zNw(Yn6xnY7(`38-&yel*e~xUo|MO(K{m+u^_Me4aaQnYNw%h+4*>3+A$#(mnC)@3R zfo!+`OJuwKUnbk_f01mr|0`s>{a+>9?f)9tZvWTGcKg3Uw%h+rvfcid$aeeB!CrRz z&y(%;Um)A!YN zeSW(35bibwp4q&2(#h1K^qG3MLY9dF;Y@yJZOmypTd}u{5p%XGAEZO4U9s1-9)DX& zA3e6Z;&IpNbj8lMwZuOib*!)V>|28?bzLki&?MuL2 zu}7DiJrro=&mJzoLO)M;&pyw!0q1^mJMotDeD>QVz{kn!9-MJ*x^~DsN}*58gE-A+ zcGvp+4lYhP5*I-?74gQ7ozUAGm)}}(dpK^#1oq8nHI^B~eeLZy4I}msp0qx%M39=7 z3pFhji=bYrWy#cd+ZBhL#W0q{tP`eyjZdnP^gE!{Opg-^Nlv22u|xRE==EcVe9|)R zB$_0sbdMB{n4~Z#g?-WrwALhHjnN}Tq9!TANfDp4O3P4VIxH7@q-dW>igHraC*8uv zsY!yU_egy)lhnsaeLm?nHd0LzzQp%P{c;J8w}kh~+5Mc<@00G}4Puh;vxpukW}7|5 zI4S0n-jm;Q^moAkBMqcX(f}t7_@p8&`i(PgGm<@Ql59@0eNu_G4h&M9k>Y8S6z8P4 zPjc|}&?F@oDUmTr2~JA*q%t;YO;VDPlA|Um$w^6{RKdorNg8CN!7-CG$Vr1fsfvwU zlZ5ZDy?4RTgh?9Wq@f-upQF{AamKN}>yc8ECMm^9DW8<5MVdjv(ym7uo-#?poHXo{ z3bZ~mNLbbNNNM@ABmQYgb5hzTEz{D>AYnn*BaK`zdm7=S5uda|t1^RxwOo&snKMZl zPRjVCRa%f4BrM~4q|tekG|EY%KIs;%#S9Wwa6Qu4f=L?Vq%og#o0ee)35&NLY5bB& z8t0^OpL7Qs%O+`pktP;R(gY_>_@wu+(QJ|?8ENv0Nt)!ONuN~2om-PM#Yj_EP0|!6 zP5Gn}Hlj_^G$T#_z$8s`(zH)D&(?3QkIdjSOMdW%ak+ANm-wi zzYru{V5AG{Cg}nvUGPbTxgcqdk>)l`(i|tv`K0BGLDEG=x_H+lUF4*TK51n>NSbG) z`MOD(=cIX`w7L)^Eilr;1CzACNee#d)}(I>rkB}lr$NLSuBNmn@OicczD4U(=h($x=5(p65n>XS;> zf~0GVbnS;G=^7_p^GVM2An7_IUH?0ibe)r~`=s)XAn67p-RPL48=Q2*Csl3+NjDkk z=8j3a$w@bTQgtavT4JQ7U6ZuLNlQJ_vb&tq)>8Pva!)yPk4;jJlX5;OpAYtwXQcc` zCMnNJd7o4$1W5%(D*VVK6*#Hjla`l*q-920-Zx3hoV4tdR#t+f6-HV)Fi9(%wBnOi zSA(QgMp}Jhl2$os6{O5GHbSwf+pgpa!ri{5O;OsTN!3QxE~)%=uiO&88@K=ci=+st zCB-R~x7MsTi8l!=hT~R3u7dxFr{5%ceiAviIF z!kWNl`jtm0-&}5|`y#Yk0ehvLjz#Q{jZF!7tMm+wk@{=@WoRAVtbX9An;*#smD)q> zq7*3F=r|QkMQIB?RhfPyf1_QSqF1qX7;ols?O3~5ZeW_L&D?%F1(ZhPIb+~e`R7NxEKRAT3cS19{w<0F&(KV|hI>N%+?Xh@_zjGn^s?OK$ zKkQ`BbPo8!z`($~*~#D8BUr&HBEVSz2pEB4AU24G0Y(N+hD|^Y6El!tgNU*~X%LSC z$X0-fGcm9T0LA|E|L2FOWMD92VqjR>!otAF!NBm72Obk1 YBHITON2VDSAnpK(F*YFF1LDH~0O^Si0RR91 literal 0 HcmV?d00001 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index 4d139d7f6b7e..dfb8523c8bf4 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,4 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/q35/APIC.thread-count", -"tests/data/acpi/q35/DSDT.thread-count", -"tests/data/acpi/q35/FACP.thread-count", From patchwork Mon Oct 23 09:46:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 1853615 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=b3rOlKx7; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDVW83dgjz23jq for ; Mon, 23 Oct 2023 20:38:44 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qurLs-0006y0-1V; Mon, 23 Oct 2023 05:36:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLo-0006lh-R2 for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:56 -0400 Received: from mgamail.intel.com ([192.198.163.7]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLn-0005WP-7h for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:35:56 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698053755; x=1729589755; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DBpNZQjwV3r0cYakq12XmqZ0tZ94v+zrAeZNPNbQmCI=; b=b3rOlKx71mgaWHWFTWlNC/4kpt+Hzm7UbLodZ5tO24i3wiJPJDg/dEts 9DnloiBGCJ02qrKLjtXERGMFcSuOPDqpqTPX5e8C9szUnO5VwL8NbUH5E AaQlorhjoGzbc0njaWLsNUEV41hKzVDf/5x3lRShEq9NHf6WDFokGpv/1 AZRK1qXLxWCYTXUQHb98UX3s21rVSO1L+5M2PHHJoD/pPQ3cpF9YF9d3Z 5yHzUZevlaQq9lwRMd0u+UzOOlmGjNUMYoN4DmPpcs5BlCS90M3n7Xmsz 8mLWsMlqjamTE2vyA5GpFdqvSAYlZZ4ACz4iCh06iKaEqrh67kEbZTFfN A==; X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="8359696" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="8359696" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 02:35:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="707883366" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="707883366" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga003.jf.intel.com with ESMTP; 23 Oct 2023 02:35:41 -0700 From: Zhao Liu To: "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Eduardo Habkost , Yanan Wang Cc: Marcel Apfelbaum , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH v3 14/16] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 thread count2 test Date: Mon, 23 Oct 2023 17:46:33 +0800 Message-Id: <20231023094635.1588282-15-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> References: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.198.163.7; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Zhao Liu Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be added to test the thread count2 field of smbios type4 table. Signed-off-by: Zhao Liu Reviewed-by: Michael S. Tsirkin --- tests/data/acpi/q35/APIC.thread-count2 | 0 tests/data/acpi/q35/DSDT.thread-count2 | 0 tests/data/acpi/q35/FACP.thread-count2 | 0 tests/qtest/bios-tables-test-allowed-diff.h | 3 +++ 4 files changed, 3 insertions(+) create mode 100644 tests/data/acpi/q35/APIC.thread-count2 create mode 100644 tests/data/acpi/q35/DSDT.thread-count2 create mode 100644 tests/data/acpi/q35/FACP.thread-count2 diff --git a/tests/data/acpi/q35/APIC.thread-count2 b/tests/data/acpi/q35/APIC.thread-count2 new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/tests/data/acpi/q35/DSDT.thread-count2 b/tests/data/acpi/q35/DSDT.thread-count2 new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/tests/data/acpi/q35/FACP.thread-count2 b/tests/data/acpi/q35/FACP.thread-count2 new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8bf4..d17d80e21ab9 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,4 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/q35/APIC.thread-count2", +"tests/data/acpi/q35/DSDT.thread-count2", +"tests/data/acpi/q35/FACP.thread-count2", From patchwork Mon Oct 23 09:46:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 1853608 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=EkJL8nsA; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDVSh0FlFz23jn for ; Mon, 23 Oct 2023 20:36:36 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qurLx-000781-1Y; Mon, 23 Oct 2023 05:36:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLs-0006z0-9w for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:36:00 -0400 Received: from mgamail.intel.com ([192.198.163.7]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLq-0005XQ-D5 for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:36:00 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698053758; x=1729589758; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lFTHrf9r7t3llLILAkJNgbgd2feR0sJ/dRqpO4Pmcr8=; b=EkJL8nsAvzzTe7eIIWjhLo302KQsEoubPWj2Y2CB9aK+C/lclKK40XDw 8/DcM9qEjt7Xw4NM1fgNDWEPCB6R56JNn9cvWV+xu/9KNEBMErI4GOIof MYAskAOKxJDbFhxHkWTEFbde65O0F3l865zIkz2TAKRbjsRXeUb8fDnzB w7D9Mjcn+NwnwBWnAVvpPtRTysCEOO8F4bi5fY5fI6vk7c8qP9HZ9+VH9 p5i797+VfMIpQKWxx+KsdwBNnVNjSqdOObCIW9Eg6aWD6XjjhQhXxmuPj pTurJD5xV45YztxkjCAufI/fq/86V478clnCPKJUYUD8fdahD9R2P+moM A==; X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="8359711" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="8359711" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 02:35:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="707883372" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="707883372" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga003.jf.intel.com with ESMTP; 23 Oct 2023 02:35:43 -0700 From: Zhao Liu To: "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Eduardo Habkost , Yanan Wang Cc: Marcel Apfelbaum , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH v3 15/16] tests: bios-tables-test: Add test for smbios type4 thread count2 Date: Mon, 23 Oct 2023 17:46:34 +0800 Message-Id: <20231023094635.1588282-16-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> References: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.198.163.7; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Zhao Liu This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in type4"). In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of threads in the socket is more than 255, then smbios type4 table encodes threads per socket into the thread count2 field. So for the topology in this case, there're the following considerations: 1. threads per socket should be more than 255 to ensure we could cover the thread count2 field. 2. The original bug was that threads per socket was miscalculated, so now we should configure as many topology levels as possible (multiple dies, no module since x86 hasn't supported it) to cover more general topology scenarios, to ensure that the threads per socket encoded in the thread count2 field is correct. 3. For the more general topology, we should also add "cpus" (presented threads for machine) and "maxcpus" (total threads for machine) to make sure that configuring unpluged CPUs in smp (cpus < maxcpus) does not affect the correctness of threads per socket for thread count2 field. Note we don't consider the topology with multiple sockets since this topology would create too many vCPUs (more than 255 threads per socket with at least 2 sockets, which may cause the failure "Number of hotpluggable cpus requested (*) exceeds the maximum cpus supported by KVM (*) socket_accept failed: Resource temporarily unavailable"), and the calculation of threads per socket has already been covered by "thread count" test case. Based on these considerations, select the topology as the follow: -smp cpus=210,maxcpus=260,dies=2,cores=65,threads=2 The expected thread count2 = threads per socket = threads (2) * cores (65) * dies (2) = 260. Suggested-by: Igor Mammedov Signed-off-by: Zhao Liu --- Changes since v2: * Reduced the vCPU number by deleting the multiple sockets in "-smp" to fix the failure: "Number of hotpluggable cpus requested (520) exceeds the maximum cpus supported by KVM (288) socket_accept failed: Resource temporarily unavailable". (Michael) Changes since v1: * Dropped the extra variable: uint64_t thread_count2_addr. (Igor) * Added description of the consideration for topology selection of this case in commit message. (Igor) --- tests/qtest/bios-tables-test.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 395ed7f9ff73..71af5cf69fc5 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -96,6 +96,7 @@ typedef struct { uint8_t smbios_core_count; uint16_t smbios_core_count2; uint8_t smbios_thread_count; + uint16_t smbios_thread_count2; uint8_t *required_struct_types; int required_struct_types_len; int type4_count; @@ -644,6 +645,7 @@ static void smbios_cpu_test(test_data *data, uint32_t addr, uint8_t thread_count, expected_thread_count = data->smbios_thread_count; uint16_t speed, expected_speed[2]; uint16_t core_count2, expected_core_count2 = data->smbios_core_count2; + uint16_t thread_count2, expected_thread_count2 = data->smbios_thread_count2; int offset[2]; int i; @@ -680,6 +682,15 @@ static void smbios_cpu_test(test_data *data, uint32_t addr, if (expected_core_count == 0xFF && expected_core_count2) { g_assert_cmpuint(core_count2, ==, expected_core_count2); } + + thread_count2 = qtest_readw(data->qts, + addr + offsetof(struct smbios_type_4, + thread_count2)); + + /* Thread Count has reached its limit, checking Thread Count 2 */ + if (expected_thread_count == 0xFF && expected_thread_count2) { + g_assert_cmpuint(thread_count2, ==, expected_thread_count2); + } } } @@ -1050,6 +1061,7 @@ static void test_acpi_q35_tcg_thread_count(void) .required_struct_types = base_required_struct_types, .required_struct_types_len = ARRAY_SIZE(base_required_struct_types), .smbios_thread_count = 27, + .smbios_thread_count2 = 27, }; test_acpi_one("-machine smbios-entry-point-type=64 " @@ -1058,6 +1070,23 @@ static void test_acpi_q35_tcg_thread_count(void) free_test_data(&data); } +static void test_acpi_q35_tcg_thread_count2(void) +{ + test_data data = { + .machine = MACHINE_Q35, + .variant = ".thread-count2", + .required_struct_types = base_required_struct_types, + .required_struct_types_len = ARRAY_SIZE(base_required_struct_types), + .smbios_thread_count = 0xFF, + .smbios_thread_count2 = 260, + }; + + test_acpi_one("-machine smbios-entry-point-type=64 " + "-smp cpus=210,maxcpus=260,dies=2,cores=65,threads=2", + &data); + free_test_data(&data); +} + static void test_acpi_q35_tcg_bridge(void) { test_data data = {}; @@ -2228,6 +2257,8 @@ int main(int argc, char *argv[]) test_acpi_q35_tcg_core_count2); qtest_add_func("acpi/q35/thread-count", test_acpi_q35_tcg_thread_count); + qtest_add_func("acpi/q35/thread-count2", + test_acpi_q35_tcg_thread_count2); } if (qtest_has_device("virtio-iommu-pci")) { qtest_add_func("acpi/q35/viot", test_acpi_q35_viot); From patchwork Mon Oct 23 09:46:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 1853612 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=aYQfQFs3; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDVT21l8bz23jq for ; Mon, 23 Oct 2023 20:36:54 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qurM4-0007kB-Mi; Mon, 23 Oct 2023 05:36:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurM2-0007YJ-9i for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:36:10 -0400 Received: from mgamail.intel.com ([192.198.163.7]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qurLy-0005VZ-5n for qemu-devel@nongnu.org; Mon, 23 Oct 2023 05:36:09 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698053766; x=1729589766; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aBuL0BuijXl9jyu2ljEksmLwgpXnUY19FR5QR44TviQ=; b=aYQfQFs31kGghqDhYL6UHkDzRZJoFZ6XhO1s94ipqSHwZ14G80tOr9tl wNPAReQDZX+AR2OysK3iQswFbCkRQGAu9yxEFwcLTVJviG61jJ96v9IQ+ YAIvO1QRm7FhZ38shDYL41XoYK5i1vWV9wy7xlgLinPfeAyfRM7bjIHfG RBuvhxQQpxWE8bjOIRPqFNMTd1VqeWyWO/PV7p71+Z5KOGoYz3L1He9G6 +N+WbwvT5+8rJOoPt9c9WepMph2nE7vAjIAtfpX6YeuBDW6mkyWn4GvJz 8x32xbzo62hrWBgvq+e5kp90m9VIBtQJI3uwFv36yqZuG8kIPRS6OmRiJ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="8359719" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="8359719" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 02:35:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="707883382" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="707883382" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga003.jf.intel.com with ESMTP; 23 Oct 2023 02:35:46 -0700 From: Zhao Liu To: "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Eduardo Habkost , Yanan Wang Cc: Marcel Apfelbaum , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH v3 16/16] tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count2 test Date: Mon, 23 Oct 2023 17:46:35 +0800 Message-Id: <20231023094635.1588282-17-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> References: <20231023094635.1588282-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.198.163.7; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Zhao Liu Following the guidelines in tests/qtest/bios-tables-test.c, this is step 5 and 6. Changes in the tables: FACP: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-CNE3C2, Mon Oct 23 15:25:01 2023 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0002 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 1 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000484A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 1 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 ... APIC: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-WKE3C2, Mon Oct 23 15:25:01 2023 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000CA6 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 2C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 [snip] +[434h 1076 1] Subtable Type : 00 [Processor Local APIC] +[435h 1077 1] Length : 08 +[436h 1078 1] Processor ID : 81 +[437h 1079 1] Local Apic ID : 81 +[438h 1080 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[43Ch 1084 1] Subtable Type : 09 [Processor Local x2APIC] +[43Dh 1085 1] Length : 10 +[43Eh 1086 2] Reserved : 0000 +[440h 1088 4] Processor x2Apic ID : 00000100 +[444h 1092 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[448h 1096 4] Processor UID : 00000082 [snip] +[C4Ch 3148 1] Subtable Type : 09 [Processor Local x2APIC] +[C4Dh 3149 1] Length : 10 +[C4Eh 3150 2] Reserved : 0000 +[C50h 3152 4] Processor x2Apic ID : 00000181 +[C54h 3156 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 +[C58h 3160 4] Processor UID : 00000103 + +[C5Ch 3164 1] Subtable Type : 01 [I/O APIC] +[C5Dh 3165 1] Length : 0C +[C5Eh 3166 1] I/O Apic ID : 00 +[C5Fh 3167 1] Reserved : 00 +[C60h 3168 4] Address : FEC00000 +[C64h 3172 4] Interrupt : 00000000 + +[C68h 3176 1] Subtable Type : 02 [Interrupt Source Override] +[C69h 3177 1] Length : 0A +[C6Ah 3178 1] Bus : 00 +[C6Bh 3179 1] Source : 00 +[C6Ch 3180 4] Interrupt : 00000002 +[C70h 3184 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 [snip] +[C90h 3216 1] Subtable Type : 02 [Interrupt Source Override] +[C91h 3217 1] Length : 0A +[C92h 3218 1] Bus : 00 +[C93h 3219 1] Source : 0B +[C94h 3220 4] Interrupt : 0000000B +[C98h 3224 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[C9Ah 3226 1] Subtable Type : 0A [Local x2APIC NMI] +[C9Bh 3227 1] Length : 0C +[C9Ch 3228 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[C9Eh 3230 4] Processor UID : FFFFFFFF +[CA2h 3234 1] Interrupt Input LINT : 01 +[CA3h 3235 3] Reserved : 000000 ... DSDT: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of /tmp/aml-CDE3C2, Mon Oct 23 15:25:01 2023 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x000083EA (33770) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x01 + * OEM ID "BOCHS " + * OEM Table ID "BXPC " + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } [snip] + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } [snip] + Processor (C081, 0x81, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x81)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x81, 0x81, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x81) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x81, Arg0, Arg1, Arg2) + } + } ... Signed-off-by: Zhao Liu --- Changes since v2: * Rebuilt the binaries to match the changes for the change in "thread count2" test case. --- tests/data/acpi/q35/APIC.thread-count2 | Bin 0 -> 3238 bytes tests/data/acpi/q35/DSDT.thread-count2 | Bin 0 -> 33770 bytes tests/data/acpi/q35/FACP.thread-count2 | Bin 0 -> 244 bytes tests/qtest/bios-tables-test-allowed-diff.h | 3 --- 4 files changed, 3 deletions(-) diff --git a/tests/data/acpi/q35/APIC.thread-count2 b/tests/data/acpi/q35/APIC.thread-count2 index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..ac200ab7aa6e2fc4b6995ba0dfc1a77ae32e0412 100644 GIT binary patch literal 3238 zcmXxmWmuJI9E9-!M9(>ZVz+{diQP>If(43!4Ju%FCv513Zg;2K-R*X_Zg+Qg=sv^D za)I~zqdtJwf5Zy^48jY&4n3|NNCMT;YDQf-tYJ&!9YO30>q1vdC+PJaWq>0+JsoJcW z+Pt~iqJ`SBrP`{M+Pbycrj6RRt=g`g+P=N2p9>=C>2ik-YR8Uhr%q}{hT6Ha+NF!y zwX52#o7%m*+M|b>nW^^dsrKrn_U^6r>7(}TtM==s_V2F_7@!Uus16#W4j!xy8KMpy zsty~b4j-|Fsg4?@jvlRMWvSWOYEF)ttN$mFF=OPsJT*UG9XnPnC{POv)p6t0 z@#EDA6V!%^G#>T6Ntzb^UsE!v=NZMs?FBb@OI*%NBL(R(0Dpb^CU8#}0MpPIcEV zwYplZsbQn3;h*rp=cDX6`)Hd7f*(J|=AodEwRte;-8K&gy~pMOp^vk9Na*8j9u)cn zn}>xy(dL1n_u4!(^gf#hhd#;X;h|5qd4T9sY#t)|RGSBhKF#J~qEEMZpy)Gf9xD1w zn+Jw84 zY#u`TQajDQ%ucs2w|OALE3UA4DCsM09!z?_onc>P^MLZ>SKBoX9^e%$6@&`;QT_LFwL{glli;pabXb5Q7KYz_DfPo)u4KeVetw9EUvNg=W&$b2{_{G*x1HalDY~VLr!wvjyYrug&Yz;Z^ zr>#K;{<1afz~8n89{9)B&;$S48hqfet>Fib*!lw?ApG3<`_&%;fp)cjAKZC_*i)31D_HTLsR$^jsE`>3!k9(B_-89#llw~2`~JH{{h;7;sF2v literal 0 HcmV?d00001 diff --git a/tests/data/acpi/q35/DSDT.thread-count2 b/tests/data/acpi/q35/DSDT.thread-count2 index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..3a0cb8c581c8cc630a2ec21712b7f8b75fcad1c8 100644 GIT binary patch literal 33770 zcmb822Y6J)*N5+>5jGnLA#{X@Vpq}=tR%ae0wjbafEqLjMJbk5Kt)6;iiq8ay+p;{ zdspmTvG?A4S1f<|&hOsYopa8;KF=qQhTm*v-uKL=9QI~58*7cVeYMhYLZO;T(fZcH znmwDNh4d%nI1V!Y&TGh+?zAt9)zo!_a?&zF?aOoAOmAwk3wDUrOsNZCX~?M+4Og50&hB(bcRQC_T-(>JvX!z%iZ@C_w+xb+kLlpTOQt%=)^6TM7*1T zDqc6gU_xd**4micQ_(%oN%Tt(Ih{R2&+rP^Q2ErSt>s5Ho<8WS#vzYH8`pLA^jbSN zoVKnr5njH!({bpA;obAXy%PDEX-=-wN%z75j?9d&n}+uYP#6fG)t zX!k9x{YHj|A3w-(BDl-(=cY}YHa+M?CvUNnH?d$R+m%Xp_T_mP zMCtY^h4dy?*uJbaKAt{QPe#HS^s&MqT2mAsPw%K{YHSJRZ19$05UpvN(pcEs5Zkk` zJybI>I>9Lz-5iaNPix--qfMIpZdH=Sl~XF*Nx zX7~P#W&Ni+lySX7+>l8#f=6Z?4YbJx+-@Q{9y`#7e5hoty5iOjeNYU}bV@y0?<1x+`gjl}Ss6yE0iphPyI3HN#t(ES`pZ zpP6ExneNKu)J$(>vUnQueP)S$X1ObqQ?ukgX~_54OYF0k*k>=fPa5)lW{Z7hi+yIx zebSKcv$xo1Z?Vtba-THh`wWYHhQ&U^a-THh`^*vh%n|#{k^7_}-)BVZGa~jGk^7_} z-)FAaXRg?1uG}XL`9AxIefAOi>?8L{L%z?xVxN7*KKsgj(va^nPwX>K>@!d9lZJes z{lq@|iGB8y`=lY?XTI2HzSw8J+$RnBKKqM(_80r?FZW49zRv=&&jPW}0=Z8b@_h~v z`y3$lIY91{hJ2p`#Xbj$eGZiSq#@rYwK4B|mit|4kl5!SxlbDMeGV4;94z)ZSniXC ze4j(ymDT1u;ShIajrnFb#9JA)L#&LMxkJUupVXuB0JfIb5t9 zE>;egD{07AZYEZ4CRT1HSJIHL9O14^evcpFu1tQ9AK|S`e&ePgRwg^iNZ}kQoFk=^ zhMqH<8fZ0ZpmnVcq;{KWh%$*y1Em3Jy+Jw+l2U4*-aPk{DCA&Ovc3>Wy{V}NO2g#V zsDXNOlMR$jMFaJwrWz;>shVU1_2!xpoJ37_Osq`aV`!i>q>9|R)IhztW@Ps0u0#X% zrY47cpVUA-thaIisrD1ZP)Ihzt?n-K)Y$_V4H`QH<21>)^$CDbUH`iTB4U|nq1NEl5 zE73q{nA|5dP;aigk{T$RiU#UUbyuQ+(lEJCYM|a+cO^AYHWdxjo9eDa1EpbdpVUCT zx$a78plm7{s5jMJi3Uo;G*B8Q_el-Zo9nKm2Fj+QfqGNjm1v+eOzx8! zs5jSLNez@uMFaJwx+~E@X_(w6HBfJ^yOJ6xn~DbNO?6kIfzmL!PimmvTz4fkP&O3} z)SK$AL<6N^a-Y;dy}9m6YM^W?8mKqbU5N%t!{k1xfqHY@mDE7lR5Va;s=E>ml!nQD zQUmqox+|%HvZ-jG-c)xb8Ym5u`=kcy&2?8&17%auK)tE%N;FU!Cih7V)SK(Bqz1~S zqJer--IZvdG)(T38Yqoe1EmpfpfuzSl!mN9AahizNH3AqvU-{4U|U7`xXt9hRORD4U~p-4PVp0alj-q)Pwyq+WpkW$;oj@QIR#}6lcO!YsqMBD_3IPPIU&pG?OsY)?5x3U;Y@nl zkXSM&+}A-OP)kw!iiy3b&sQg}#6=#oZjiwp&a@i?9g{pXR%Yz zx1+VK+F6GZnp-AU7xe3hHMBZQk;BW}Tl(UH24+NC-0`4})|S@LnmMKh=yAKT*C>1F zKiF%Sy~efIP<`B9QxI&gXEo_GuJrML(Z`LxR_inWgT9vOYh8V<(%1fr zzSijLv_9)U=x{l$>wEnNeLd6HyZU;ium2Z)J?S&>?MUnMJbm(; z2mRB4zTCZwlk&ELEcZ*E{=(O_!RasKa6gHoe=qoO-fe+6-`8cn#L+(@d^qp6K%DRE ztiQz3zbt$>@3ugk@9U;O;^?0nKAd-3AkO!7FhJty-ylAmcUvIN_jx@~;^-eHKAd-3 zAkO!BI!NN^Un@SGcbmlJHD-I4|Kr*9&GEM6r(cM^<>8`#`?C7xwnm5k<-Osb9EUDl z=V9D`YP=~{*xVB9C@iROJ5K_)bS7|9*O8s!yw0A;>D`@9cPCwsUFY=lIla5fIkPL` zeE4hTI%9OjzLb`6<(A1EfaByS$ij{M+rn^5Hpo+XI&3=lDP>1(} zmCS;MN1|=Dd!_Y+yXQEoqO{w&h#|z{xji}EbHZuJC0)}psF!n*V_xoq9QSfx)IS*6)IS8-)ISv2)ISW_)IS{A)V~?Bsec5rsedH0 zslSkNiK%~cWK;hrWK;hZ$fo`+kxl)hkxl(uA)ETQMmF_tgKX;G7TMIl9kQu^dt_7p z4#=kd9g$7_J0Y9;#~_>fizt_x`iqfG{Uykz{!(O9e;Kl=zZ}`rUx94uuS7QWS0S7F z$0D2hcSbh#?}BXV-xb-^zZhC}{ z^>{$-S_O#RD|P5mp7P5mp8P5s9roBEGK zHubMUHuWEmZ0cW)Z0bJ&+0?%V+0=g`vZ?$?M z{|sbPe>bwJ|4d|4|5{{I|5?bU{OUXZ)PDi8ssBP`Q~yQC zrv8hOP5nKTt4;lvAe;IxMK<+chHUCzhivM<9NE-=1+uCCN@P?2Rmi6PtC3Cp*C3nv zuSGWXUx#e!zaH7te*?0q|3+j}|4o!@O#L?_oBD4-Huc|%Z0f%a+0=hKvZ?VFK`)c-iLss9ONQ~#65rv9gpP5nVFT})c-!Rss97YaZ~??$fo{}kWKv`Bb)j^K{oY&ifrot4B6EGIkKt$3uIIO zm&m66uaHgsUn86Pzd<(je~WDD{|?#I|2?v){|Cyorv4w1P5nP1oBDr7Hue94Z0i3N z+0_3VvZ?=fWK;h}WK;hi$fo{3kxl)7A)EUDMmF{T582fJ53;F$6Ef8w>7GMB23Zv? z#=rkD2)P5=0S0OAfVO}^x;rSHTTq`x2aKwFw{J0hOa^~Mghx6!A*64nM zz+;_6xG$Xy^1Wx`gms+-jhT4-^WQ`vjUqxIzo33#v^Cn4{V&_djyA=o<)>{*I5QKW zS(n!4ch3qXoLPxbXTs^av?+30cV}qr%$y9mu`@AKOWiH&8|m>|&!DyXR(b?C^YWhF z-Cf~LB)U8i^!}bLefJ$6A|__8MwMO8qAsfIlFFWP-!%6@Bt6cX8BS05?izY0ty?q` zNA%(u-WfdrXE-zQ*l;EZ+KYoX=VMVli)IAh(T%;MlUmy%|8hqMf4=zmbmt}J2HZD^ zaGJgqQ|IX$>240Ju6<<{J(4WKl>i4P!00nOdmTQ%>9KNSbz8rjaJEA~tLkDYU9nCr4TapLIUVMad{KyDLN2Brm=gLaH5|FN0$h4d zanjOUP9((%r_uGjWIf?DODd&fUz$XhR8pjLI>G2}HCa(Oos-fnsf;d+XcAozPLVP) zG%16VGAyYaKQmCfqieeYDdHY><-3b;QpA#C z^iy?B%4MY7TwPNxC*@jFoPNr#NqrcpPajR{!%2NCsg{1~u1R#UG4)x{x34Dk<)pqT zQgIP3wX1uaF2<)wd3l1?VG^rma^|PcBTufIax&)sh<>zZs zJ}2c{QYo&ZD-vCOPm%if*QEZO)ZdcIa0y+J=)!x7R8XKv1)Nl1N#(eDu1IvvJw+NY zK$8Y=(f~`Uz=d-~qRZ_m(!hb5G?0@9T2dvhnJW@qX-|;`4br4RoHWRis^}DeCJkn! z!GkqvFeeSRq_K1=K$C_r(vTsVG=!6eSW-0|v(u!Zj5KtpCJp7Jp_Wubrv@}>7$XfE zrb)v%X_zHN=@fw`4QHg`!!>C*Ck?lx7@aE6q|F#Nu^u(Nn0?|7F%f27M!$&C6#UICvC|{TW+aITXNEt zmQ+64Pa4fgqepAfXige!Nflf9Nn0_}R$FP(R-CkzB~@qB-cQ<| zk+$DnleXui?JX&~gP*hmBkiz*ChfpUJ6KX|M?YytM%r;lP1=!@cC@7UPJYr(jI`5E znzR!q?PN){WBjBsj5KD9CXL~wF)321c{nE?OVP8-Qk}D?NRx^LksV0?jQmG}CmHA0!j8s;pNoAZ= zW=ZAceo{Fjm6vN$IVY7{QbmQIRKZ9U6`EARNfnk{v}2%SmG`sd{HWX=g^-d1p=9nUi+5q?%p)q+J+kmt8bz z7f#y6lA^o%NxL%AuDfc|uAH>1CB=60lXhdI-FDNY-8gACON#IAC+*HiyYH?^yK~a+ zmQ=fkpR@-f?Xia@?ZHWVq)25&S|4@=A>#% zDyi|4=m=MeR8yl#I9Zvx{#0X0rBOeLPH&}1QTJKI{Cg%2Nv23qODc=`Npx^4MT*6A zO*rqEBE>AJJnkpaS)UXs9@iusT}+YUmQ+#eC(&`O6seYu>d=EWc7+C~5L2XDORB8% zljx*Yid0vpNjOlLBGp+^RlT1?hqO|p`g%>m*}xR3-jc>P_(=_n)X<1 zr16Y2e!M1)=cMtLR5QU(n!rdCCTP+GPMTmz(TRT2L`Ir8QIjTe(nL#&HTp?(nk{vY zH#TZgBPTUlQoPAeYGS0OCQWMMq$W$Mo#ZD?Vx&ovG-(niO-hlK zq-oPMX&NU@v!tp${iHn^Y0o`1X-`ht(~`#SC-i7IwwuHq}V=w(msr|&pw*84=3$o zN%4LCqv=+LANPU=XJDvCP&q)tZa?9`-APU^Iz;x0d_ zi;=pzG^vY|x-6+=hMzQpk!H-$q#2wv!;(s8`bjexY358#n#oBsEvamlpEQe+X3f&1 zS)4S>lFDcMNwXPg_H0d>%}KK@sbW7rX+K8VZ$C}ikCXPZq{{vMr2QFb|NS*-e@@!p zlB(wTNpl!!&Kyme!%1^2Y3y7-X)YtpovTT6IccsXRnPO2<}uQ|d73njljd1c&3r#; zJ|oSauSxScX}%>z5Ac%?V59@+m$Jxz`yRka2Ut?~ZCN1Ek1(sB{&`(;(NDCKg(n3yJ zXi4RZ{G>&Uv}lngE#jm_mQ-<=pL7@_9d?)|9mYwASyJWUe$wHLbok+#bT}s+Zb?-~ z_(?}F(h)~!(h;0=ge8q#>?bW|q{WLhX)z})wxsGK{iGuq>Bu8B=}1mG(voVH_(@9` zX~_~zTEa<7EGc@FpL7%>9d(o@9mPpUSyF7NpR|;bmM+z#rJS_XlHy1ENk=o%(MN02 z(VTR&CDk6|Cmq8`#~hh+w49Tc zgS28?7M zz_3ynRtiJN7*;C7N^V$b4Rq~1z;LWE94ibs)P+49s|?3-!?D&t*VF?H#|gu6!hpkG zFdU~0$8p1P)tbwiu2N+HkhLeQ>ht*&>Ss6~|hLf#IY=DZ^>paGEvH&qM%p)~~ehl_;aB4NNG zLKrSmhKso2B5Mfl4;Kr=#lnEYg)m&K3>S05#VJE|aDV6#h8|(Sp+gvYl%ac3B%^baG5e( z#toNQLvVjsCk*R^0f!ptKWCjXtmB4t))3quE*FN&g#m{hVYplwF6V~Jts%HSTprJT+0pDT0?MuxK0?Z69yd0gyA}6xQ-jHvxeaQaJ?{GFAO-W3B&cua6LC%ZwJRl4>L<_?M%J2X;JYWsM{oz4jcu*K{xE6*7mEl2dcray%2KR^c z!mwT#aOf6>^~$iG8`fJxaDRA67#QT;QsKiFgz>__x@R%^* zurCacDZ^vj@R&6O_lL)Y;c;QWAz&CDSBA&A;c;sS?hj80!xO>~H-;ya;R$Yd!Wx46 z!;`}Bq%hPP!;{MJBsV;14Z;24DPed@7;u;v_tI0!@Dw*ZWevgo;b~!bS{QK17>1{n z;c0Go+8ToU!!yG0j4m|=Kc8J_2c=dB^QKfE9eF9-t;H^cCPGQ7YI zFQg2y;Qp{d7&Zt44n4!LK^Zo1!v<>z?hh{t!;8Xz!_Y9is0=T1!;97s+#g;NhL?l^ zhooV6Nf}<^hL@}%xIers3@-}<4o}1IvNF8P4KG_maDRA37+w*E7Grot8D8OrSF9np zKfEdouL=VWTVoHeD#NSX@TxTg_lMVn;Wc5vA#504Q-;^L;WcXr?hmgE!|TE@#TZ^! zhS#~_b!!Oj4{r#=8^VA?+t|Y!%J2p^ykQN&{ozevcvBc~m>Y&SmElcpc+(n!`@>tp z@Rl&(kT(o(DZ^Xb@Rl_M_lLKI;ca2S;cpn;R))8^;caUO?ho$>!#l!&L*X#IqYUqG z!#max+#lW*hIfSlhs9xdR~g>rhIg$YxIern4DSg84w1v~o-(}04ewb)aDRAT7~U5K z94?39ePwu`8{SVD;=%pl17Y|;7;xwuh7XkC18(@h8iM=7hr;loFyJsc3?C}PhurX? zH3avEkA&ePVdyl5kCfpfZurO=g8ReA!tk*$bQ#0P%J4Bad~6ND{oxZ~_(T|RsGa_E zK2e5GxZx9P2<{J`3d5(ufWz)Ee5wqea>J+A5ZoU=6Nb-(0f*pW_)Hl-}bxIcU$3||Pte#Y>HGJL@eUsywMfA~@uz7&T2jp0jW_>vpG zw1(jR@RcxpB@8%ZPyabzDZ^LX@RcQ;d>aqR)(*+;cIIM?hoGx!#Bc! zL-{a#qYU40!#CCt+#kLbhHr%dhxK9jRvEtKhHtGQxIcU+4BrU@4)MeAoicpK4c}Qq zaDVt-7`_(<9PWqVdu8~Z8@^8&YJ>a355n++FyPQX3_mEt58UvBH3avEABEvZVZf6C zVE9oPe&mK9ts%HS{3HxN2?L%a0K-qp@Dn%uWDUXn;b&p^Ss3u-0T_N(hM&3NXKM)V z55EY*FT#K)6~OR|GW@~~zgR3@7569A2tfZMq$8{7O;nn%CM0eHd;e)fA~Wf z{tyN{nE{4Bl;IC<_`@24`@^5Y@TV}~Ne(dlsSJN|!=Kg=+#miDhQEXXPkw;mFJ<_P z8~(C};QsKpF#IhHcv1ume=Eb^-0-(G1owyk3B&({0Z*2I;eX2TKW_M+H3avEe}v&5 zVZf6pVE9KF{^5pytRc8RY!Ze|!hk1Nz_3XfHgUry*AUCXuPzQceM-O9n10i0>eso_ zP&n|k3pntGN=g1cO{~gG{b~dnSxaD#px>7)EFo#ZQ!-$|GYPnbRxwM6Spxe6{UT;z zNt2dk#)4-Pa0{(smNaGw>=pDIo`oe{T9z9No>9Opw2E2MVJR3!uRueurqdBGDsjx~ z=HS(6@C%po8V7hUPvgF~ywJwT#z-ieZVyG$ar^J| z?v0VuIG0|9om$uNgB-_uKVFn>)219ur9Wwo`yQ&*{gX{E5Rc;y_;Zzb&-zW99>k|I z{aL^Jn(ZykyA1%mx_q`bOufaJUc_fbG=uhOJ^`DXn&}t$S9s4|$;IvLm4N8Aj@qij zIo_)exvvCNm{ph+$^&G4Mst00i}zV9A#^7NysD6&wLY>w5*kdeVzlja(zlj&_>K>>_U$`(bEbu~Y4|sQE&j9B-ULzY)0vYgNU0nR%Ib?V`N+ zu<7{C-+7Hg@lkAFk<(gK)REm$9c!W8Y}Z;;Mi1FKDf` zlSkrJks4Yir-eJik-TVzD`{W8^O$sKFca?$;l%>!g$*ay;7t^7V%ZM8Ce-9OaxLD} z;Z1#Z`--v&H8CoNPN&mr`lY9Pd+O_b6b6R})P*{oPWtk!3(az7(ch!e+>h#(jgzLN zR`u;KR%M4XM>+0?tz=?zoA+IT*csl3oxWypuNgyLIJYizMEViw+1aC(x#W`Qq{h^m zOqxxv9Tl)B4X$`mvGaehF-gM! literal 0 HcmV?d00001 diff --git a/tests/data/acpi/q35/FACP.thread-count2 b/tests/data/acpi/q35/FACP.thread-count2 index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..31fa5dd19c213034eef4eeefa6a04e61dadd8a2a 100644 GIT binary patch literal 244 zcmZ>BbPo8!z`($~*~#D8BUr&HBEVSz2pEB4AU24G0Y(N+hD|^Y6El!tgNU*~X%LSC z$X0-fGcm9T0LA|E|L2FOWMD92VqjR>!otAF!NBm72Obk1 YBHITON2VDSAnpK(F*YFF1LDH~0O^Si0RR91 literal 0 HcmV?d00001 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index d17d80e21ab9..dfb8523c8bf4 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,4 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/q35/APIC.thread-count2", -"tests/data/acpi/q35/DSDT.thread-count2", -"tests/data/acpi/q35/FACP.thread-count2",