From patchwork Fri Sep 29 16:08:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John David Anglin X-Patchwork-Id: 1841413 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RxwJl0Zjzz1ypT for ; Sat, 30 Sep 2023 02:09:10 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BD03238323E3 for ; Fri, 29 Sep 2023 16:09:08 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from dellerweb.de (unknown [IPv6:2a02:c207:3003:236::1]) by sourceware.org (Postfix) with ESMTPS id 747E6385840D for ; Fri, 29 Sep 2023 16:08:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 747E6385840D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=parisc-linux.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=parisc-linux.org Received: from mx3210.localdomain (unknown [142.126.114.79]) by dellerweb.de (Postfix) with ESMTPSA id 1BA6A160005D; Fri, 29 Sep 2023 18:08:53 +0200 (CEST) Received: by mx3210.localdomain (Postfix, from userid 1000) id 54D7B22012C; Fri, 29 Sep 2023 16:08:51 +0000 (UTC) Date: Fri, 29 Sep 2023 16:08:51 +0000 From: John David Anglin To: GCC Patches Subject: [committed] hppa: Fix memory barrier patterns for pre PA8800 processors Message-ID: MIME-Version: 1.0 Content-Disposition: inline X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Since 2005, it was assumed in the Linux kernel that all PA 2.0 processors supported the ldcw cacheable hint and that natural alignment could be used for ldcw,co. However, I recently fired up an old A500 machine with PA8600 processors and found that 16-byte alignment was needed for ldcw,co on it. As far as I can tell, only PA8800 and PA8900 processors support the cacheable hint. This change revises the memory barrier patterns. We alway use ldcw,co when comp[iling for PA 2.0 but we disable the -mcoherent-ldcw option by default. As a result, the 16-byte aligned patterns are now the default. This is safer but slightly less efficient. Dave --- Fix memory barrier patterns for pre PA8800 processors 2023-09-29 John David Anglin * config/pa/pa.md (memory_barrier): Revise comment. (memory_barrier_64, memory_barrier_32): Use ldcw,co on PA 2.0. * config/pa/pa.opt (coherent-ldcw): Change default to disabled. diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index f603591447d..4f85991e6bd 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -10739,10 +10739,10 @@ add,l %2,%3,%3\;bv,n %%r0(%3)" ;; generating PA 1.x code even though all PA 1.x systems are strongly ordered. ;; When barriers are needed, we use a strongly ordered ldcw instruction as -;; the barrier. Most PA 2.0 targets are cache coherent. In that case, we -;; can use the coherent cache control hint and avoid aligning the ldcw -;; address. In spite of its description, it is not clear that the sync -;; instruction works as a barrier. +;; the barrier. All PA 2.0 targets accept the "co" cache control hint but +;; only PA8800 and PA8900 processors implement the cacheable hint. In +;; that case, we can avoid aligning the ldcw address. In spite of its +;; description, it is not clear that the sync instruction works as a barrier. (define_expand "memory_barrier" [(parallel @@ -10772,7 +10772,7 @@ add,l %2,%3,%3\;bv,n %%r0(%3)" (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) (clobber (match_operand 1 "pmode_register_operand" "=&r"))] "TARGET_64BIT" - "ldo 15(%%sp),%1\n\tdepd %%r0,63,3,%1\n\tldcw 0(%1),%1" + "ldo 15(%%sp),%1\n\tdepd %%r0,63,3,%1\n\tldcw,co 0(%1),%1" [(set_attr "type" "binary") (set_attr "length" "12")]) @@ -10781,6 +10781,6 @@ add,l %2,%3,%3\;bv,n %%r0(%3)" (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) (clobber (match_operand 1 "pmode_register_operand" "=&r"))] "" - "ldo 15(%%sp),%1\n\t{dep|depw} %%r0,31,3,%1\n\tldcw 0(%1),%1" + "ldo 15(%%sp),%1\n\t{dep|depw} %%r0,31,3,%1\n\t{ldcw|ldcw,co} 0(%1),%1" [(set_attr "type" "binary") (set_attr "length" "12")]) diff --git a/gcc/config/pa/pa.opt b/gcc/config/pa/pa.opt index dd358f2f26a..573edcea338 100644 --- a/gcc/config/pa/pa.opt +++ b/gcc/config/pa/pa.opt @@ -50,7 +50,7 @@ Target Mask(CALLER_COPIES) Caller copies function arguments passed by hidden reference. mcoherent-ldcw -Target Var(TARGET_COHERENT_LDCW) Init(1) +Target Var(TARGET_COHERENT_LDCW) Init(0) Use ldcw/ldcd coherent cache-control hint. mdisable-fpregs