From patchwork Tue Sep 26 19:49:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1839928 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=SALLpOS3; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Rw9NS2G3zz1ypD for ; Wed, 27 Sep 2023 05:51:20 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qlE4M-0003pu-1v; Tue, 26 Sep 2023 15:50:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qlE4K-0003pW-LV for qemu-devel@nongnu.org; Tue, 26 Sep 2023 15:50:04 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qlE4I-0001Ip-TP for qemu-devel@nongnu.org; Tue, 26 Sep 2023 15:50:04 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1c724577e1fso14645ad.0 for ; Tue, 26 Sep 2023 12:50:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695757801; x=1696362601; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uJTj/yG05+kNxL5qN2Z68Ih6ZRkTJzsbo+tX9aImP4Q=; b=SALLpOS3aCNOpKq52a5B2TPRCFIk7SNmZy/KG52tv1lVYqSA2tBL1IhoHPpL2lHyys mgzjmJPDOHkh9Tex+xFsSsA9OsdD5UdY9+yNu6NZbRmxBSdLBBiwiPHC6d/EDyzSTx6u Y9t2AB2WRoYnouews96EGtNlWL8OOY4OIGe/9YwHfEJ/ZBzZOSRAJ4RQzn/jfdtEZyve vrGK9aYfaHQoqz94svSIfuuRPBQ79iEfo+XxxxDkWZzaIqXzJfDufWDjXbMPVqU9yy7G YQFHzPRSgSfcMfokuzsQjssgHmRhf6VlHxFL6y75d7dXcIoO1bpqAy0xh5MQjxo7eU5X 4Yzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695757801; x=1696362601; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uJTj/yG05+kNxL5qN2Z68Ih6ZRkTJzsbo+tX9aImP4Q=; b=onEF1XUUka9wAHuibRKIZMkLWIAfYqU12Z1PYSCSgkOZF1LaEVypLik8MgF+YzD3Tx QhHQmyMSn4EXldDBfpwGMTS0XVr7uY1I7vflG5xnnYSnxEkquIQC4yh7hZZhsHR0DF4w MGW5E8am8McBdN8HIJyaZ/uiBOUs4IlTJL9KXDxliBhHX4jKqRHPFiSqyPt/xWtDrUyu elfjSDyIKceMjikJPw6f3vrBOl4dr0zuQ0tXXtKVk81/kvaJkyVmCAzfkWXOhhzANImI r7asyQypPO/mlykOlmekb5QO78dkBMouFe9c25HNoihq9vwbpT36rjcvojY5v1RTZyIi t7wA== X-Gm-Message-State: AOJu0YwoWQHZHt4Z9cMG6po1Pzs5IQ8Z7UJivliqbILOca9hbt2ltaKS 2kMTm+1Nfuv6czmxS0ubZo34r98b3U3EfRTN7tA= X-Google-Smtp-Source: AGHT+IFzvAAydcNlqALCblWijRPuPjEyYaJ93BTyHW1tJFMx6r5iowFi9SHz6io+sysr2eJENYwRiw== X-Received: by 2002:a17:902:a988:b0:1c5:d8a3:8781 with SMTP id bh8-20020a170902a98800b001c5d8a38781mr10768899plb.55.1695757801054; Tue, 26 Sep 2023 12:50:01 -0700 (PDT) Received: from grind.. ([177.94.42.59]) by smtp.gmail.com with ESMTPSA id l6-20020a170902f68600b001c41e1e9ca7sm11386010plg.215.2023.09.26.12.49.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 12:50:00 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 1/6] target/riscv/cpu.c: add zicntr extension flag Date: Tue, 26 Sep 2023 16:49:45 -0300 Message-ID: <20230926194951.183767-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230926194951.183767-1-dbarboza@ventanamicro.com> References: <20230926194951.183767-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org zicntr is the Base Counters and Timers extension described in chapter 12 of the unprivileged spec. It describes support for RDCYCLE, RDTIME and RDINSTRET. QEMU already implements it way before it was a discrete extension. zicntr is part of the RVA22 profile, so let's add it to QEMU to make the future profile implementation flag complete. Given than it represents an already existing feature, default it to 'true'. Change the realize() time validation to disable it in case its dependency (icsr) isn't present. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 7 +++++++ target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 521bb88538..8783a415b1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -79,6 +79,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), + ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_icntr), ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl), @@ -1265,6 +1266,12 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false), MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false), + /* + * Always default true - we'll disable it during + * realize() if needed. + */ + MULTI_EXT_CFG_BOOL("zicntr", ext_icntr, true), + MULTI_EXT_CFG_BOOL("zba", ext_zba, true), MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true), MULTI_EXT_CFG_BOOL("zbc", ext_zbc, true), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 0e6a0f245c..671b8c7cb8 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -62,6 +62,7 @@ struct RISCVCPUConfig { bool ext_zksh; bool ext_zkt; bool ext_ifencei; + bool ext_icntr; bool ext_icsr; bool ext_icbom; bool ext_icboz; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index a90ee63b06..ce0fde0f5d 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -542,6 +542,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true); } + if (cpu->cfg.ext_icntr && !cpu->cfg.ext_icsr) { + cpu->cfg.ext_icntr = false; + } + /* * Disable isa extensions based on priv spec after we * validated and set everything we need. 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([177.94.42.59]) by smtp.gmail.com with ESMTPSA id l6-20020a170902f68600b001c41e1e9ca7sm11386010plg.215.2023.09.26.12.50.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 12:50:03 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 2/6] target/riscv/cpu.c: add zihpm extension flag Date: Tue, 26 Sep 2023 16:49:46 -0300 Message-ID: <20230926194951.183767-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230926194951.183767-1-dbarboza@ventanamicro.com> References: <20230926194951.183767-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org zihpm is the Hardware Performance Counters extension described in chapter 12 of the unprivileged spec. It describes support for 29 unprivileged performance counters, hpmcounter3-hpmcounter21. As with zicntr, QEMU already implements zihpm before it was even an extension. zihpm is also part of the RVA22 profile, so add it to QEMU to complement the future future profile implementation. Default it to 'true' since it was always present in the code. Change the realize() time validation to disable it in case 'icsr' isn't present and if there's no hardware counters (cpu->cfg.pmu_num is zero). Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 4 +++- target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 4 ++++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8783a415b1..b3befccf89 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -84,6 +84,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl), ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), + ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_ihpm), ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa), @@ -1267,10 +1268,11 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false), /* - * Always default true - we'll disable it during + * Always default true - we'll disable them during * realize() if needed. */ MULTI_EXT_CFG_BOOL("zicntr", ext_icntr, true), + MULTI_EXT_CFG_BOOL("zihpm", ext_ihpm, true), MULTI_EXT_CFG_BOOL("zba", ext_zba, true), MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 671b8c7cb8..cf228546da 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -66,6 +66,7 @@ struct RISCVCPUConfig { bool ext_icsr; bool ext_icbom; bool ext_icboz; + bool ext_ihpm; bool ext_zicond; bool ext_zihintntl; bool ext_zihintpause; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ce0fde0f5d..11e34782b9 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -546,6 +546,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) cpu->cfg.ext_icntr = false; } + if (cpu->cfg.ext_ihpm && (!cpu->cfg.ext_icsr || cpu->cfg.pmu_num == 0)) { + cpu->cfg.ext_ihpm = false; + } + /* * Disable isa extensions based on priv spec after we * validated and set everything we need. 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([177.94.42.59]) by smtp.gmail.com with ESMTPSA id l6-20020a170902f68600b001c41e1e9ca7sm11386010plg.215.2023.09.26.12.50.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 12:50:06 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 3/6] target/riscv: add rva22u64 profile definition Date: Tue, 26 Sep 2023 16:49:47 -0300 Message-ID: <20230926194951.183767-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230926194951.183767-1-dbarboza@ventanamicro.com> References: <20230926194951.183767-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The rva22U64 profile, described in: https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva22-profiles Contains a set of CPU extensions aimed for 64-bit userspace applications. Enabling this set to be enabled via a single user flag makes it convenient to enable a predictable set of features for the CPU, giving users more predicability when running/testing their workloads. QEMU implements all possible extensions of this profile. The exception is Zicbop (Cache-Block Prefetch Operations) that is not available since QEMU RISC-V does not implement a cache model. For this same reason all the so called 'synthetic extensions' described in the profile that are cache related are ignored (Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa, Zicclsm). An abstraction called RISCVCPUProfile is created to store the profile. 'ext_offsets' contains mandatory extensions that QEMU supports. Same thing with the 'misa_ext' mask. Optional extensions must be enabled manually in the command line if desired. The design here is to use the common target/riscv/cpu.c file to store the profile declaration and export it to the accelerator files. Each accelerator is then responsible to expose it (or not) to users and how to enable the extensions. Next patches will implement the profile for TCG and KVM. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 16 ++++++++++++++++ target/riscv/cpu.h | 10 ++++++++++ 2 files changed, 26 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b3befccf89..c83807f179 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1376,6 +1376,22 @@ Property riscv_cpu_options[] = { DEFINE_PROP_END_OF_LIST(), }; +/* Optional extensions left out: RVV, zfh, zkn, zks */ +const RISCVCPUProfile RVA22U64 = { + .name = "rva22u64", + .misa_ext = RVM | RVA | RVF | RVD | RVC, + .ext_offsets = { + CPU_CFG_OFFSET(ext_icsr), CPU_CFG_OFFSET(ext_zihintpause), + CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb), + CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin), + CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_icntr), + CPU_CFG_OFFSET(ext_ihpm), CPU_CFG_OFFSET(ext_icbom), + CPU_CFG_OFFSET(ext_icboz), + + RISCV_PROFILE_EXT_LIST_END + } +}; + static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3f11e69223..615946b919 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -66,6 +66,16 @@ const char *riscv_get_misa_ext_description(uint32_t bit); #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) +typedef struct riscv_cpu_profile { + const char *name; + uint32_t misa_ext; + const int32_t ext_offsets[]; +} RISCVCPUProfile; + +#define RISCV_PROFILE_EXT_LIST_END -1 + +extern const RISCVCPUProfile RVA22U64; + /* Privileged specification version */ enum { PRIV_VERSION_1_10_0 = 0, From patchwork Tue Sep 26 19:49:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1839927 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=ojvBEWwd; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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([177.94.42.59]) by smtp.gmail.com with ESMTPSA id l6-20020a170902f68600b001c41e1e9ca7sm11386010plg.215.2023.09.26.12.50.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 12:50:09 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 4/6] target/riscv/tcg: implement rva22u64 profile Date: Tue, 26 Sep 2023 16:49:48 -0300 Message-ID: <20230926194951.183767-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230926194951.183767-1-dbarboza@ventanamicro.com> References: <20230926194951.183767-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The TCG emulation implements all the extensions described in the RVA22U64 profile, both mandatory and optional. The mandatory extensions will be enabled via the profile flag. We'll leave the optional extensions to be enabled by hand. Given that this is the first profile we're implementing in TCG we'll need some wiring first. 'cpu_set_profile', our set() callback for the profile user flag that we'll expose, will do the heavy lifting. We'll assign misa_ext and misa_ext_mask based on the profile .misa_ext, and enable all extensions from .ext_offsets[]. We'll also update the user choice hash 'multi_ext_user_opts' for each extension. The idea is to reflect that setting a profile is the same as setting all extensions of the profile in the command line. This will prevent us from mishandling those by accident during realize() time, in particular in validate_set_extensions(), when we might enable/disable extensions based on certain criterias. After cpu_set_profile() is figured out then it's a matter of exposing the user flag for the profile using the profile name (in this case, 'rva22u64') during riscv_cpu_add_user_properties(). We will expose the profile option for vendor CPUs in the next patch since it requires special handling. Expose it to generic CPUs only for now. Here's an example with the 'rv64' CPU: $ qemu-system-riscv64 -M virt -cpu rv64,rva22u64=true (...) # cat /proc/cpuinfo processor : 0 hart : 0 isa : rv64imafdch_zicbom_zicboz_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zawrs_zfa_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_sstc_svadu Signed-off-by: Daniel Henrique Barboza --- target/riscv/tcg/tcg-cpu.c | 55 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 11e34782b9..03435521c9 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -740,6 +740,57 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) } } +static void cpu_set_profile(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + const RISCVCPUProfile *profile = opaque; + RISCVCPU *cpu = RISCV_CPU(obj); + CPURISCVState *env = &cpu->env; + int i = 0; + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + /* We won't disable extensions if the user disables the profile */ + if (!value) { + return; + } + + env->misa_ext |= profile->misa_ext; + env->misa_ext_mask |= profile->misa_ext; + + for (i = 0;; i++) { + int ext_offset = profile->ext_offsets[i]; + + if (ext_offset == RISCV_PROFILE_EXT_LIST_END) { + break; + } + + isa_ext_update_enabled(cpu, ext_offset, true); + g_hash_table_insert(multi_ext_user_opts, + GUINT_TO_POINTER(ext_offset), + (gpointer)true); + } +} + +static void cpu_get_profile(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value; + + visit_type_bool(v, name, &value, errp); +} + +static void riscv_cpu_add_profile_prop(Object *cpu_obj, + const RISCVCPUProfile *profile) +{ + object_property_add(cpu_obj, profile->name, "bool", + cpu_get_profile, cpu_set_profile, + NULL, (void *)profile); +} + static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -834,6 +885,10 @@ static void riscv_cpu_add_user_properties(Object *obj) riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); + if (object_dynamic_cast(obj, TYPE_RISCV_DYNAMIC_CPU) != NULL) { + riscv_cpu_add_profile_prop(obj, &RVA22U64); + } + for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { qdev_property_add_static(DEVICE(obj), prop); } From patchwork Tue Sep 26 19:49:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1839929 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=KDd+PHwJ; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; 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([177.94.42.59]) by smtp.gmail.com with ESMTPSA id l6-20020a170902f68600b001c41e1e9ca7sm11386010plg.215.2023.09.26.12.50.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 12:50:11 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 5/6] target/riscv/tcg-cpu.c: enable profile support for vendor CPUs Date: Tue, 26 Sep 2023 16:49:49 -0300 Message-ID: <20230926194951.183767-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230926194951.183767-1-dbarboza@ventanamicro.com> References: <20230926194951.183767-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Vendor CPUs can implement any profile they want as long as all required extensions are being set in their respective cpu_init(). We do not enable extensions for vendor CPUs and that will still be true with profile support. The idea then is to enable the profile option for vendor CPUs and let users try to enable it. In case the vendor CPU do not implement all mandatory extensions of the profile, error out. Proceed as usual otherwise. Here's an example of what happens if we try to enable the rva22u64 profile with the veyron-v1 CPU: ./qemu-system-riscv64 -M virt -cpu veyron-v1,rva22u64=true qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.rva22u64=true: Setting profile 'rva22u64' failed: CPU veyron-v1 does not support extension 'Zihintpause' Signed-off-by: Daniel Henrique Barboza --- target/riscv/tcg/tcg-cpu.c | 43 ++++++++++++++++++++++++++++++++++---- 1 file changed, 39 insertions(+), 4 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 03435521c9..c8f688292e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -99,6 +99,31 @@ static const struct TCGCPUOps riscv_tcg_ops = { #endif /* !CONFIG_USER_ONLY */ }; +static const char *cpu_get_multi_ext_cfg_name(uint32_t ext_offset) +{ + const RISCVCPUMultiExtConfig *prop; + + for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { + if (prop->offset == ext_offset) { + return prop->name; + } + } + + for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) { + if (prop->offset == ext_offset) { + return prop->name; + } + } + + for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) { + if (prop->offset == ext_offset) { + return prop->name; + } + } + + return NULL; +} + static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) { const RISCVIsaExtData *edata; @@ -747,7 +772,7 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name, RISCVCPU *cpu = RISCV_CPU(obj); CPURISCVState *env = &cpu->env; int i = 0; - bool value; + bool value, generic_cpu; if (!visit_type_bool(v, name, &value, errp)) { return; @@ -758,16 +783,28 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name, return; } + generic_cpu = object_dynamic_cast(obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; + env->misa_ext |= profile->misa_ext; env->misa_ext_mask |= profile->misa_ext; for (i = 0;; i++) { int ext_offset = profile->ext_offsets[i]; + bool prev_val = isa_ext_is_enabled(cpu, ext_offset); if (ext_offset == RISCV_PROFILE_EXT_LIST_END) { break; } + if (!prev_val && !generic_cpu) { + const char *ext_name = cpu_get_multi_ext_cfg_name(ext_offset); + const char *cpu_name = riscv_cpu_get_name(cpu); + + error_setg(errp, "Setting profile '%s' failed: CPU %s does not " + "support extension '%s'", name, cpu_name, ext_name); + return; + } + isa_ext_update_enabled(cpu, ext_offset, true); g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), @@ -885,9 +922,7 @@ static void riscv_cpu_add_user_properties(Object *obj) riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); - if (object_dynamic_cast(obj, TYPE_RISCV_DYNAMIC_CPU) != NULL) { - riscv_cpu_add_profile_prop(obj, &RVA22U64); - } + riscv_cpu_add_profile_prop(obj, &RVA22U64); for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { qdev_property_add_static(DEVICE(obj), prop); From patchwork Tue Sep 26 19:49:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1839926 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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([177.94.42.59]) by smtp.gmail.com with ESMTPSA id l6-20020a170902f68600b001c41e1e9ca7sm11386010plg.215.2023.09.26.12.50.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 12:50:14 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 6/6] target/riscv/kvm: add 'rva22u64' flag as unavailable Date: Tue, 26 Sep 2023 16:49:50 -0300 Message-ID: <20230926194951.183767-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230926194951.183767-1-dbarboza@ventanamicro.com> References: <20230926194951.183767-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org KVM does not have the means to support enabling the rva22u64 profile. The main reasons are: - we're missing support for some mandatory rva22u64 extensions in the KVM module; - we can't make promises about enabling a profile since it all depends on host support in the end. We'll revisit this decision in the future if needed. For now mark the 'rva22u64' profile as unavailable when running a KVM CPU: $ qemu-system-riscv64 -machine virt,accel=kvm -cpu rv64,rva22u64=true qemu-system-riscv64: can't apply global rv64-riscv-cpu.rva22u64=true: 'rva22u64' is not available with KVM Signed-off-by: Daniel Henrique Barboza --- target/riscv/kvm/kvm-cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index c6615cb807..258e360422 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -358,7 +358,7 @@ static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, } if (value) { - error_setg(errp, "extension %s is not available with KVM", + error_setg(errp, "'%s' is not available with KVM", propname); } } @@ -438,6 +438,9 @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); + + /* We don't have the needed KVM support for this profile */ + riscv_cpu_add_kvm_unavail_prop(cpu_obj, RVA22U64.name); } static int kvm_riscv_get_regs_core(CPUState *cs)