From patchwork Tue Sep 26 18:31:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1839891 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=YLxrDnOw; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Rw7dW47vfz1ynX for ; Wed, 27 Sep 2023 04:32:30 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qlCqC-0002tA-7f; Tue, 26 Sep 2023 14:31:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qlCqA-0002sU-Q3 for qemu-devel@nongnu.org; Tue, 26 Sep 2023 14:31:22 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qlCq9-0003uv-8a for qemu-devel@nongnu.org; Tue, 26 Sep 2023 14:31:22 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1c5bf7871dcso72817205ad.1 for ; Tue, 26 Sep 2023 11:31:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695753079; x=1696357879; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wuGegwgck8ZEFasbqFPHbzSlisDssAI2uj1gevUmTVY=; b=YLxrDnOw79RLz06wjukSF+k1p1dt1wOE9DP1AGnbYS/3vGfS4zDZYgIrgsrvtjZ/l4 85Qf2e0V83TJ3VQH+L4JdphyAm0Gna0YIHpH2QCySXQ+rnih83EJTzdi3u1S2i+P5y2R E+BUpl1oBAg4mZSKpF+ZLBE7JVliSqwu/w35V6EemLcPfvdsJhifuSUAMrG6tGGua4NR x6RvySVyc1lopV7aRXlvVZ2wiWLKaeLRoxz0ADxs6bdowGV54SIs9pjmptI4ziU7e4Zm kFXEFGXuXkw5uYiPx/V2hKIohK7S8Nr3iG5nsIK0ntMsxIQpZkgN8HpMfF/eP8OPsolz oiSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695753079; x=1696357879; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wuGegwgck8ZEFasbqFPHbzSlisDssAI2uj1gevUmTVY=; b=YdeGotR/R1bWRILxGGXxaS7H5N4UrarFTufbXY+s3g6ahd4PqFyrA8eQxUYtSjW/7t pWmAs85yKXslyP++TP3aOB+Le3rlswrJbZUWWE8j8Ft8i6oMp3wlX2T0YnvLTmqDSML6 RD1zO6xzTlUu8TKF3O0t938DagV8jN+VggMmkjBNosAy4t2bUhe0JpDnq6kcp0Z+YiGU NO5RcsmRkJJ4rmp3DmCBfQ8jYu3pbNj2efL+G9ss1cwK8YnjSR06gQ/I5cL2oiZasFs4 s8ThhTbDPjMlYj/yMOw5XjG0XVsAfmCGZbfT1TkYx/OcgMKctGQL7E/7UTEq5SBvCtAw EElw== X-Gm-Message-State: AOJu0YxS/FRrUlYdl8w4LMMJAJ5mE1KuxLnYKP3e+QhjEaGqldHDkuoU D7Po9dJjLv3fD9l3GtBOVRhPGVeBRz2eGLzBfSI= X-Google-Smtp-Source: AGHT+IH82I/4KYW3kBx42+4k8dhUK04YjL0wAylNQAAac4ZTymBrYqkqe4PfQtTDLiyJfbEEbNjdtQ== X-Received: by 2002:a17:902:da88:b0:1c6:777:712c with SMTP id j8-20020a170902da8800b001c60777712cmr6872406plx.51.1695753078860; Tue, 26 Sep 2023 11:31:18 -0700 (PDT) Received: from grind.. ([177.94.42.59]) by smtp.gmail.com with ESMTPSA id u6-20020a170902b28600b001c61acd5bd2sm4715800plr.112.2023.09.26.11.31.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 11:31:18 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 1/2] target/riscv: add riscv_cpu_get_name() Date: Tue, 26 Sep 2023 15:31:08 -0300 Message-ID: <20230926183109.165878-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230926183109.165878-1-dbarboza@ventanamicro.com> References: <20230926183109.165878-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We'll introduce generic errors that will output a CPU type name via its RISCVCPU pointer. Create a helper for that. Use the helper in tcg_cpu_realizefn() instead of hardcoding the 'host' CPU name. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 11 +++++++++++ target/riscv/cpu.h | 1 + target/riscv/tcg/tcg-cpu.c | 4 +++- 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index eeeb08a35a..521bb88538 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -643,6 +643,17 @@ static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) return oc; } +char *riscv_cpu_get_name(RISCVCPU *cpu) +{ + RISCVCPUClass *rcc = RISCV_CPU_GET_CLASS(cpu); + const char *typename = object_class_get_name(OBJECT_CLASS(rcc)); + + g_assert(g_str_has_suffix(typename, RISCV_CPU_TYPE_SUFFIX)); + + return g_strndup(typename, + strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX)); +} + static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) { RISCVCPU *cpu = RISCV_CPU(cs); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 219fe2e9b5..3f11e69223 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -730,6 +730,7 @@ typedef struct isa_ext_data { int ext_enable_offset; } RISCVIsaExtData; extern const RISCVIsaExtData isa_edata_arr[]; +char *riscv_cpu_get_name(RISCVCPU *cpu); void riscv_add_satp_mode_properties(Object *obj); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 8c052d6fcd..f31aa9bcc4 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -563,7 +563,9 @@ static bool tcg_cpu_realizefn(CPUState *cs, Error **errp) Error *local_err = NULL; if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { - error_setg(errp, "'host' CPU is not compatible with TCG acceleration"); + g_autofree char *name = riscv_cpu_get_name(cpu); + error_setg(errp, "'%s' CPU is not compatible with TCG acceleration", + name); return false; } From patchwork Tue Sep 26 18:31:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1839893 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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([177.94.42.59]) by smtp.gmail.com with ESMTPSA id u6-20020a170902b28600b001c61acd5bd2sm4715800plr.112.2023.09.26.11.31.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 11:31:21 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 2/2] target/riscv/tcg-cpu.c: add extension properties for all cpus Date: Tue, 26 Sep 2023 15:31:09 -0300 Message-ID: <20230926183109.165878-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230926183109.165878-1-dbarboza@ventanamicro.com> References: <20230926183109.165878-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org At this moment we do not expose extension properties for vendor CPUs because that would allow users to change them via command line. The drawback is that if we were to add an API that shows all CPU properties, e.g. qmp-query-cpu-model-expansion, we won't be able to show extensions state of vendor CPUs. We have the required machinery to create extension properties for vendor CPUs while not allowing users to enable extensions. Disabling existing extensions is allowed since it can be useful for debugging. Change the set() callback cpu_set_multi_ext_cfg() to allow enabling extensions only for generic CPUs. In cpu_add_multi_ext_prop() let's not set the default values for the properties if we're not dealing with generic CPUs, otherwise the values set in cpu_init() of vendor CPUs will be overwritten. And finally, in tcg_cpu_instance_init(), add cpu user properties for all CPUs. For the veyron-v1 CPU, we're now able to disable existing extensions like smstateen: $ ./build/qemu-system-riscv64 --nographic -M virt \ -cpu veyron-v1,smstateen=false But setting extensions that the CPU didn't set during cpu_init(), like V, is not allowed: $ ./build/qemu-system-riscv64 --nographic -M virt \ -cpu veyron-v1,v=true qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.v=true: 'veyron-v1' CPU does not allow enabling extensions Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 64 +++++++++++++++++++++++++++++--------- 1 file changed, 50 insertions(+), 14 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f31aa9bcc4..a90ee63b06 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -549,6 +549,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) riscv_cpu_disable_priv_spec_isa_exts(cpu); } +static bool riscv_cpu_is_generic(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; +} + /* * We'll get here via the following path: * @@ -632,13 +637,27 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, target_ulong misa_bit = misa_ext_cfg->misa_bit; RISCVCPU *cpu = RISCV_CPU(obj); CPURISCVState *env = &cpu->env; - bool value; + bool generic_cpu = riscv_cpu_is_generic(obj); + bool prev_val, value; if (!visit_type_bool(v, name, &value, errp)) { return; } + prev_val = env->misa_ext & misa_bit; + + if (value == prev_val) { + return; + } + if (value) { + if (!generic_cpu) { + g_autofree char *cpuname = riscv_cpu_get_name(cpu); + error_setg(errp, "'%s' CPU does not allow enabling extensions", + cpuname); + return; + } + env->misa_ext |= misa_bit; env->misa_ext_mask |= misa_bit; } else { @@ -688,6 +707,7 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { */ static void riscv_cpu_add_misa_properties(Object *cpu_obj) { + bool use_def_vals = riscv_cpu_is_generic(cpu_obj); int i; for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { @@ -706,7 +726,9 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) cpu_set_misa_ext_cfg, NULL, (void *)misa_cfg); object_property_set_description(cpu_obj, name, desc); - object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL); + if (use_def_vals) { + object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL); + } } } @@ -714,17 +736,32 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; - bool value; + RISCVCPU *cpu = RISCV_CPU(obj); + bool generic_cpu = riscv_cpu_is_generic(obj); + bool prev_val, value; if (!visit_type_bool(v, name, &value, errp)) { return; } - isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value); - g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(multi_ext_cfg->offset), (gpointer)value); + + prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset); + + if (value == prev_val) { + return; + } + + if (value && !generic_cpu) { + g_autofree char *cpuname = riscv_cpu_get_name(cpu); + error_setg(errp, "'%s' CPU does not allow enabling extensions", + cpuname); + return; + } + + isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); } static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name, @@ -739,11 +776,17 @@ static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name, static void cpu_add_multi_ext_prop(Object *cpu_obj, const RISCVCPUMultiExtConfig *multi_cfg) { + bool generic_cpu = riscv_cpu_is_generic(cpu_obj); + object_property_add(cpu_obj, multi_cfg->name, "bool", cpu_get_multi_ext_cfg, cpu_set_multi_ext_cfg, NULL, (void *)multi_cfg); + if (!generic_cpu) { + return; + } + /* * Set def val directly instead of using * object_property_set_bool() to save the set() @@ -828,20 +871,13 @@ static bool riscv_cpu_has_max_extensions(Object *cpu_obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; } -static bool riscv_cpu_has_user_properties(Object *cpu_obj) -{ - return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; -} - static void tcg_cpu_instance_init(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); Object *obj = OBJECT(cpu); - if (riscv_cpu_has_user_properties(obj)) { - multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); - riscv_cpu_add_user_properties(obj); - } + multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); + riscv_cpu_add_user_properties(obj); if (riscv_cpu_has_max_extensions(obj)) { riscv_init_max_cpu_extensions(obj);