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Thu, 14 Sep 2023 19:46:00 -0700 From: To: , , , , , , CC: , , , , , , , Subject: [PATCH v1 1/4] vfio: new command line params for device memory NUMA nodes Date: Thu, 14 Sep 2023 19:45:56 -0700 Message-ID: <20230915024559.6565-2-ankita@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230915024559.6565-1-ankita@nvidia.com> References: <20230915024559.6565-1-ankita@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FC:EE_|IA0PR12MB7698:EE_ X-MS-Office365-Filtering-Correlation-Id: f4d2a141-cac7-4e47-bef2-08dbb595e74b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 09zunvNbk9AF92eWojs46+9ZWNDpRCXuIOyuJixuvCqsLXNpgVN+mwlbp65TCcN8WzZlpMaK4HJTvp1T53I5iyT5BPlzWmouZaSnj63XpZJCBqi5dkqtNVLSlE9PDEKbATuJujb9rl5aRRFZktOupPNjpP4exaiAwbygN/71BG4uEKIJANIuhnpBQE97mpCkqYgHHX3oOfAi0cgCZjBWRf3AFbzuXt6nuZ43sx0HSA+h0dr8RIujdmty43KFyPeRwLS0r1pRyeinGpKJi5c/slVq11ZhvcEBIkxWX8SVOJPuFY0oCM2RJ5vo+BW+D1zwccCbet0LId1Nwf56oBv2TQdag/lO1l+BNZ1Ry6PNa2wb5Azu2dTdTfTB1uF79SptKukG+1CYJRM21mhfuSLwxsv7DOEQ9WuvasK2k4WRyUKCD6U2EfYqua+Yo53E9I/0aiiQWSe3sXo/yMRV1jeStFknjpSE1jeiM6DheBHXZ1iK6x2C5rdCZwmgaT+MnZylQGWLgElPbExioj0701htnlQGje8dGEZHIknu/hABGqxU3aBj+jHEbcxiHQVvxABjq/oWqbXLNhH8F4wbyTuQgBT9rOSdwXMlJ5eRhEiRhWUK8KKPBEJPaaWvNy+WaqPc/bL5XIB9fqbFsFfFPfx52MtHs6DhwgXx21fatIg6wViKAZ7cFZ2JwZFK+3OOuNzVQHsF3YcYBCmRUavhvtF9qPW19y3wTWpdOUMh7wwwrUDOk1Gk9SXpzC8K/j1OkZc6 X-Forefront-Antispam-Report: CIP:216.228.118.233; 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envelope-from=ankita@nvidia.com; helo=NAM02-SN1-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Ankit Agrawal The CPU cache coherent device memory can be added as a set of NUMA nodes distinct from the system memory nodes. The Qemu currently do not provide a mechanism to support node creation for a vfio-pci device. Introduce new command line parameters to allow host admin provide the desired starting NUMA node id (pxm-ns) and the number of such nodes (pxm-nc) associated with the device. In this implementation, a numerically consecutive nodes from pxm-ns to pxm-ns + pxm-nc is created. Also validate the requested range of nodes to check for conflict with other nodes and to ensure that the id do not cross QEMU limit. Since the QEMU's SRAT and DST builder code needs the proximity domain (PXM) id range, expose PXM start and count as device object properties. The device driver module communicates support for such feature through sysfs. Check the presence of the feature to activate the code. E.g. the following argument adds 8 PXM nodes starting from id 0x10. -device vfio-pci-nohotplug,host=,pxm-ns=0x10,pxm-nc=8 Signed-off-by: Ankit Agrawal --- hw/vfio/pci.c | 144 ++++++++++++++++++++++++++++++++++++ hw/vfio/pci.h | 2 + include/hw/pci/pci_device.h | 3 + 3 files changed, 149 insertions(+) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index a205c6b113..cc0c516161 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -42,6 +42,8 @@ #include "qapi/error.h" #include "migration/blocker.h" #include "migration/qemu-file.h" +#include "qapi/visitor.h" +#include "include/hw/boards.h" #define TYPE_VFIO_PCI_NOHOTPLUG "vfio-pci-nohotplug" @@ -2955,6 +2957,22 @@ static void vfio_register_req_notifier(VFIOPCIDevice *vdev) } } +static void vfio_pci_get_dev_mem_pxm_start(Object *obj, Visitor *v, + const char *name, + void *opaque, Error **errp) +{ + uint64_t pxm_start = (uintptr_t) opaque; + visit_type_uint64(v, name, &pxm_start, errp); +} + +static void vfio_pci_get_dev_mem_pxm_count(Object *obj, Visitor *v, + const char *name, + void *opaque, Error **errp) +{ + uint64_t pxm_count = (uintptr_t) opaque; + visit_type_uint64(v, name, &pxm_count, errp); +} + static void vfio_unregister_req_notifier(VFIOPCIDevice *vdev) { Error *err = NULL; @@ -2974,6 +2992,125 @@ static void vfio_unregister_req_notifier(VFIOPCIDevice *vdev) vdev->req_enabled = false; } +static int validate_dev_numa(uint32_t dev_node_start, uint32_t num_nodes) +{ + MachineState *ms = MACHINE(qdev_get_machine()); + unsigned int i; + + if (num_nodes >= MAX_NODES) { + return -EINVAL; + } + + for (i = 0; i < num_nodes; i++) { + if (ms->numa_state->nodes[dev_node_start + i].present) { + return -EBUSY; + } + } + + return 0; +} + +static int mark_dev_node_present(uint32_t dev_node_start, uint32_t num_nodes) +{ + MachineState *ms = MACHINE(qdev_get_machine()); + unsigned int i; + + for (i = 0; i < num_nodes; i++) { + ms->numa_state->nodes[dev_node_start + i].present = true; + } + + return 0; +} + + +static bool vfio_pci_read_cohmem_support_sysfs(VFIODevice *vdev) +{ + gchar *contents = NULL; + gsize length; + char *path; + bool ret = false; + uint32_t supported; + + path = g_strdup_printf("%s/coherent_mem", vdev->sysfsdev); + if (g_file_get_contents(path, &contents, &length, NULL) && length > 0) { + if ((sscanf(contents, "%u", &supported) == 1) && supported) { + ret = true; + } + } + + if (length) { + g_free(contents); + } + g_free(path); + + return ret; +} + +static int vfio_pci_dev_mem_probe(VFIOPCIDevice *vPciDev, + Error **errp) +{ + Object *obj = NULL; + VFIODevice *vdev = &vPciDev->vbasedev; + MachineState *ms = MACHINE(qdev_get_machine()); + int ret = 0; + uint32_t dev_node_start = vPciDev->dev_node_start; + uint32_t dev_node_count = vPciDev->dev_nodes; + + if (!vdev->sysfsdev || !vfio_pci_read_cohmem_support_sysfs(vdev)) { + ret = -ENODEV; + goto done; + } + + if (vdev->type == VFIO_DEVICE_TYPE_PCI) { + obj = vfio_pci_get_object(vdev); + } + + /* Since this device creates new NUMA node, hotplug is not supported. */ + if (!obj || DEVICE_CLASS(object_get_class(obj))->hotpluggable) { + ret = -EINVAL; + goto done; + } + + /* + * This device has memory that is coherently accessible from the CPU. + * The memory can be represented seperate memory-only NUMA nodes. + */ + vPciDev->pdev.has_coherent_memory = true; + + /* + * The device can create several NUMA nodes with consecutive IDs + * from dev_node_start to dev_node_start + dev_node_count. + * Verify + * - whether any node ID is occupied in the desired range. + * - Node ID is not crossing MAX_NODE. + */ + ret = validate_dev_numa(dev_node_start, dev_node_count); + if (ret) { + goto done; + } + + /* Reserve the node by marking as present */ + mark_dev_node_present(dev_node_start, dev_node_count); + + /* + * To have multiple unique nodes in the VM, a series of PXM nodes are + * required to be added to VM's SRAT. Send the information about the + * starting node ID and the node count to the ACPI builder code. + */ + object_property_add(OBJECT(vPciDev), "dev_mem_pxm_start", "uint64", + vfio_pci_get_dev_mem_pxm_start, NULL, NULL, + (void *) (uintptr_t) dev_node_start); + + object_property_add(OBJECT(vPciDev), "dev_mem_pxm_count", "uint64", + vfio_pci_get_dev_mem_pxm_count, NULL, NULL, + (void *) (uintptr_t) dev_node_count); + + ms->numa_state->num_nodes += dev_node_count; + +done: + return ret; +} + static void vfio_realize(PCIDevice *pdev, Error **errp) { VFIOPCIDevice *vdev = VFIO_PCI(pdev); @@ -3291,6 +3428,11 @@ static void vfio_realize(PCIDevice *pdev, Error **errp) } } + ret = vfio_pci_dev_mem_probe(vdev, errp); + if (ret && ret != -ENODEV) { + error_report("Failed to setup device memory with error %d", ret); + } + vfio_register_err_notifier(vdev); vfio_register_req_notifier(vdev); vfio_setup_resetfn_quirk(vdev); @@ -3454,6 +3596,8 @@ static Property vfio_pci_dev_properties[] = { DEFINE_PROP_UINT32("x-pci-sub-device-id", VFIOPCIDevice, sub_device_id, PCI_ANY_ID), DEFINE_PROP_UINT32("x-igd-gms", VFIOPCIDevice, igd_gms, 0), + DEFINE_PROP_UINT32("pxm-ns", VFIOPCIDevice, dev_node_start, 0), + DEFINE_PROP_UINT32("pxm-nc", VFIOPCIDevice, dev_nodes, 0), DEFINE_PROP_UNSIGNED_NODEFAULT("x-nv-gpudirect-clique", VFIOPCIDevice, nv_gpudirect_clique, qdev_prop_nv_gpudirect_clique, uint8_t), diff --git a/hw/vfio/pci.h b/hw/vfio/pci.h index a2771b9ff3..eef5ddfd06 100644 --- a/hw/vfio/pci.h +++ b/hw/vfio/pci.h @@ -158,6 +158,8 @@ struct VFIOPCIDevice { uint32_t display_yres; int32_t bootindex; uint32_t igd_gms; + uint32_t dev_node_start; + uint32_t dev_nodes; OffAutoPCIBAR msix_relo; uint8_t pm_cap; uint8_t nv_gpudirect_clique; diff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h index d3dd0f64b2..aacd2279ae 100644 --- a/include/hw/pci/pci_device.h +++ b/include/hw/pci/pci_device.h @@ -157,6 +157,9 @@ struct PCIDevice { MSIVectorReleaseNotifier msix_vector_release_notifier; MSIVectorPollNotifier msix_vector_poll_notifier; + /* GPU coherent memory */ + bool has_coherent_memory; + /* ID of standby device in net_failover pair */ char *failover_pair_id; uint32_t acpi_index; From patchwork Fri Sep 15 02:45:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Agrawal X-Patchwork-Id: 1834618 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=oB9XzG/R; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2023 02:46:09.7858 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c162bee1-2648-41ef-f2e3-08dbb595eaf4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6943 Received-SPF: softfail client-ip=2a01:111:f400:7e8b::623; envelope-from=ankita@nvidia.com; helo=NAM04-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Ankit Agrawal It may be desirable for some deployments to have QEMU automatically pick a range and create the NUMA nodes. So the admin need not care about passing any additional params. Another advantage is that the feature is not dependent on newer libvirt that support the new parameters pxm-ns and pxm-nc. Assign default values to pxm-ns (first available node) and pxm-nc (8). This makes the new params optional and the feature will work on older libvirt. Signed-off-by: Ankit Agrawal --- hw/vfio/pci.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index cc0c516161..0bba161172 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -3053,8 +3053,10 @@ static int vfio_pci_dev_mem_probe(VFIOPCIDevice *vPciDev, VFIODevice *vdev = &vPciDev->vbasedev; MachineState *ms = MACHINE(qdev_get_machine()); int ret = 0; - uint32_t dev_node_start = vPciDev->dev_node_start; - uint32_t dev_node_count = vPciDev->dev_nodes; + uint32_t dev_node_start = vPciDev->dev_node_start ? + vPciDev->dev_node_start : + ms->numa_state->num_nodes; + uint32_t dev_node_count = vPciDev->dev_nodes ? vPciDev->dev_nodes : 8; if (!vdev->sysfsdev || !vfio_pci_read_cohmem_support_sysfs(vdev)) { ret = -ENODEV; From patchwork Fri Sep 15 02:45:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Agrawal X-Patchwork-Id: 1834614 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2023 02:46:05.1357 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9236e475-72c7-43d6-79cd-08dbb595e823 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FD.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7830 Received-SPF: softfail client-ip=2a01:111:f400:7e89::610; envelope-from=ankita@nvidia.com; helo=NAM10-MW2-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Ankit Agrawal During bootup, Linux kernel parse the ACPI SRAT to determine the PXM ids. This allows for the creation of NUMA nodes for each unique id. Insert a series of the unique PXM ids in the VM SRAT ACPI table. The range of nodes can be determined from the "dev_mem_pxm_start" and "dev_mem_pxm_count" object properties associated with the device. These nodes as made MEM_AFFINITY_HOTPLUGGABLE. This allows the kernel to create memory-less NUMA nodes on bootup to which a subrange (or entire range) of device memory can be added/removed. Signed-off-by: Ankit Agrawal --- hw/arm/virt-acpi-build.c | 54 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 6b674231c2..6d1e3b6b8a 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -46,6 +46,7 @@ #include "hw/acpi/hmat.h" #include "hw/pci/pcie_host.h" #include "hw/pci/pci.h" +#include "hw/vfio/pci.h" #include "hw/pci/pci_bus.h" #include "hw/pci-host/gpex.h" #include "hw/arm/virt.h" @@ -515,6 +516,57 @@ build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) acpi_table_end(linker, &table); } +static int devmem_device_list(Object *obj, void *opaque) +{ + GSList **list = opaque; + + if (object_dynamic_cast(obj, TYPE_VFIO_PCI)) { + *list = g_slist_append(*list, DEVICE(obj)); + } + + object_child_foreach(obj, devmem_device_list, opaque); + return 0; +} + +static GSList *devmem_get_device_list(void) +{ + GSList *list = NULL; + + object_child_foreach(qdev_get_machine(), devmem_device_list, &list); + return list; +} + +static void build_srat_devmem(GArray *table_data) +{ + GSList *device_list, *list = devmem_get_device_list(); + + for (device_list = list; device_list; device_list = device_list->next) { + DeviceState *dev = device_list->data; + Object *obj = OBJECT(dev); + VFIOPCIDevice *pcidev + = ((VFIOPCIDevice *)object_dynamic_cast(OBJECT(obj), + TYPE_VFIO_PCI)); + + if (pcidev->pdev.has_coherent_memory) { + uint64_t start_node = object_property_get_uint(obj, + "dev_mem_pxm_start", &error_abort); + uint64_t node_count = object_property_get_uint(obj, + "dev_mem_pxm_count", &error_abort); + uint64_t node_index; + + /* + * Add the node_count PXM domains starting from start_node as + * hot pluggable. The VM kernel parse the PXM domains and + * creates NUMA nodes. + */ + for (node_index = 0; node_index < node_count; node_index++) + build_srat_memory(table_data, 0, 0, start_node + node_index, + MEM_AFFINITY_ENABLED | MEM_AFFINITY_HOTPLUGGABLE); + } + } + g_slist_free(list); +} + /* * ACPI spec, Revision 5.1 * 5.2.16 System Resource Affinity Table (SRAT) @@ -569,6 +621,8 @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); } + build_srat_devmem(table_data); + acpi_table_end(linker, &table); } From patchwork Fri Sep 15 02:45:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Agrawal X-Patchwork-Id: 1834615 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=Cx6lR1eI; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2023 02:46:11.9108 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b5b2ac45-3420-486b-32a1-08dbb595ec39 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6793 Received-SPF: softfail client-ip=2a01:111:f400:7e8a::608; envelope-from=ankita@nvidia.com; helo=NAM10-BN7-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Ankit Agrawal To add the memory in the guest as NUMA nodes, it needs the PXM node index and the total count of nodes associated with the memory. The range of proximity domains are communicated to the VM as part of the guest ACPI using the nvidia,gpu-mem-pxm-start and nvidia,gpu-mem-pxm-count DSD properties. These value respectively represent the staring proximity domain id and the count. Kernel modules can then fetch this information and determine the numa node id using pxm_to_node(). Signed-off-by: Ankit Agrawal --- hw/pci-host/gpex-acpi.c | 69 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index 7c7316bc96..0548feace1 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -49,6 +49,72 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq) } } +static void acpi_dsdt_add_cohmem_device(Aml *dev, int32_t devfn, + uint64_t dev_mem_pxm_start, + uint64_t dev_mem_pxm_count) +{ + Aml *memdev = aml_device("CMD%X", PCI_SLOT(devfn)); + Aml *pkg = aml_package(2); + Aml *pkg1 = aml_package(2); + Aml *pkg2 = aml_package(2); + Aml *dev_pkg = aml_package(2); + Aml *UUID; + + aml_append(memdev, aml_name_decl("_ADR", aml_int(PCI_SLOT(devfn) << 16))); + + aml_append(pkg1, aml_string("dev-mem-pxm-start")); + aml_append(pkg1, aml_int(dev_mem_pxm_start)); + + aml_append(pkg2, aml_string("dev-mem-pxm-count")); + aml_append(pkg2, aml_int(dev_mem_pxm_count)); + + aml_append(pkg, pkg1); + aml_append(pkg, pkg2); + + UUID = aml_touuid("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301"); + aml_append(dev_pkg, UUID); + aml_append(dev_pkg, pkg); + + aml_append(memdev, aml_name_decl("_DSD", dev_pkg)); + aml_append(dev, memdev); +} + +static void find_mem_device(PCIBus *bus, PCIDevice *pdev, + void *opaque) +{ + Aml *dev = (Aml *)opaque; + + if (bus == NULL) { + return; + } + + if (pdev->has_coherent_memory) { + Object *po = OBJECT(pdev); + + if (po == NULL) { + return; + } + + uint64_t pxm_start + = object_property_get_uint(po, "dev_mem_pxm_start", NULL); + uint64_t pxm_count + = object_property_get_uint(po, "dev_mem_pxm_count", NULL); + + acpi_dsdt_add_cohmem_device(dev, pdev->devfn, pxm_start, pxm_count); + } +} + +static void acpi_dsdt_find_and_add_cohmem_device(PCIBus *bus, Aml *dev) +{ + if (bus == NULL) { + return; + } + + pci_for_each_device_reverse(bus, pci_bus_num(bus), + find_mem_device, dev); + +} + static void acpi_dsdt_add_pci_osc(Aml *dev) { Aml *method, *UUID, *ifctx, *ifctx1, *elsectx, *buf; @@ -207,7 +273,10 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) acpi_dsdt_add_pci_route_table(dev, cfg->irq); + acpi_dsdt_find_and_add_cohmem_device(cfg->bus, dev); + method = aml_method("_CBA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(cfg->ecam.base))); aml_append(dev, method);