From patchwork Mon Sep 4 14:00:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 1829620 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 header.s=mimecast20190719 header.b=EBwgOxMK; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RfVgd2JGhz1yh1 for ; Tue, 5 Sep 2023 00:02:04 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qdA8l-0006x1-Fa; Mon, 04 Sep 2023 10:01:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qdA8N-0006tM-V3 for qemu-devel@nongnu.org; Mon, 04 Sep 2023 10:01:01 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qdA8I-00088Q-HK for qemu-devel@nongnu.org; Mon, 04 Sep 2023 10:00:53 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1693836049; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UGcJ34kwy0LVOQwYnN3F2+fzebsswC9QQNw9e5u8JW0=; b=EBwgOxMKc1WBuJk0FXfWyICWeWLiIG2EwFrDURY6dGoHcvWV0UBW+SkehJ36rAoQ3xrUik 7x81JJIUnxptlZOs3f23H7L+Ui67ZrbSMl6lSkUNrUQ/kjNreXI7gnQpZHBf4mH27u3EQA i0uiIrQV0OKAktk3pCCV2B9U3R7MlqU= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-507-D0Dp-ilFMquqnW2r3BkzYw-1; Mon, 04 Sep 2023 10:00:46 -0400 X-MC-Unique: D0Dp-ilFMquqnW2r3BkzYw-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 97DEE8008A4; Mon, 4 Sep 2023 14:00:45 +0000 (UTC) Received: from thuth.com (unknown [10.39.193.108]) by smtp.corp.redhat.com (Postfix) with ESMTP id 3EA451121314; Mon, 4 Sep 2023 14:00:44 +0000 (UTC) From: Thomas Huth To: Peter Maydell Cc: qemu-s390x@nongnu.org, qemu-devel@nongnu.org, Richard Henderson , Ilya Leoshkevich , David Hildenbrand Subject: [risu PATCH 1/4] s390x: Add basic s390x support to the C code Date: Mon, 4 Sep 2023 16:00:37 +0200 Message-Id: <20230904140040.33153-2-thuth@redhat.com> In-Reply-To: <20230904140040.33153-1-thuth@redhat.com> References: <20230904140040.33153-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org With these changes, it is now possible to compile the "risu" binary for s390x hosts. Signed-off-by: Thomas Huth Acked-by: Ilya Leoshkevich --- risu_reginfo_s390x.c | 142 +++++++++++++++++++++++++++++++++++++++++++ risu_reginfo_s390x.h | 23 +++++++ risu_s390x.c | 48 +++++++++++++++ test_s390x.S | 32 ++++++++++ 4 files changed, 245 insertions(+) create mode 100644 risu_reginfo_s390x.c create mode 100644 risu_reginfo_s390x.h create mode 100644 risu_s390x.c create mode 100644 test_s390x.S diff --git a/risu_reginfo_s390x.c b/risu_reginfo_s390x.c new file mode 100644 index 0000000..9e118a2 --- /dev/null +++ b/risu_reginfo_s390x.c @@ -0,0 +1,142 @@ +/****************************************************************************** + * Copyright 2023 Red Hat Inc. + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * Thomas Huth - initial implementation + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include "risu.h" +#include "risu_reginfo_s390x.h" + + +const struct option * const arch_long_opts; +const char * const arch_extra_help; + +void process_arch_opt(int opt, const char *arg) +{ + abort(); +} + +void arch_init(void) +{ +} + +int reginfo_size(struct reginfo *ri) +{ + return sizeof(*ri); +} + +/* reginfo_init: initialize with a ucontext */ +void reginfo_init(struct reginfo *ri, ucontext_t *uc) +{ + int i; + + memset(ri, 0, sizeof(*ri)); + + ri->faulting_insn = *((uint32_t *) uc->uc_mcontext.psw.addr); + ri->psw_mask = uc->uc_mcontext.psw.mask; + ri->psw_addr = uc->uc_mcontext.psw.addr - image_start_address; + + for (i = 0; i < 16; i++) { + ri->gregs[i] = uc->uc_mcontext.gregs[i]; + } + + memcpy(&ri->fpregs, &uc->uc_mcontext.fpregs, sizeof(fpregset_t)); +} + +/* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */ +int reginfo_is_eq(struct reginfo *m, struct reginfo *a) +{ + int i; + + if (m->psw_mask != a->psw_mask || m->psw_addr != a->psw_addr) { + return 0; + } + + /* Skip return address register and stack register for comparison */ + for (i = 0; i < 14; i++) { + if (m->gregs[i] != a->gregs[i]) { + return 0; + } + } + + if (memcmp(&m->fpregs, &a->fpregs, sizeof(fpregset_t))) { + return 0; + } + + return 1; +} + +/* reginfo_dump: print state to a stream, returns nonzero on success */ +int reginfo_dump(struct reginfo *ri, FILE * f) +{ + int i; + + fprintf(f, " faulting insn 0x%x\n", ri->faulting_insn); + fprintf(f, " PSW mask 0x%" PRIx64 "\n\n", ri->psw_mask); + fprintf(f, " PSW addr offs 0x%" PRIx64 "\n\n", ri->psw_addr); + + for (i = 0; i < 16/2; i++) { + fprintf(f, "\tr%d: %16lx\tr%02d: %16lx\n", i, ri->gregs[i], + i + 8, ri->gregs[i + 8]); + } + fprintf(f, "\n"); + + for (i = 0; i < 16/2; i++) { + fprintf(f, "\tf%d: %16lx\tf%02d: %16lx\n", + i, *(uint64_t *)&ri->fpregs.fprs[i], + i + 8, *(uint64_t *)&ri->fpregs.fprs[i + 8]); + } + fprintf(f, "\tFPC: %8x\n\n", ri->fpregs.fpc); + + return !ferror(f); +} + +int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f) +{ + int i; + + if (m->psw_mask != a->psw_mask) { + fprintf(f, "Mismatch: PSW mask master: [%016lx] - PSW mask apprentice: [%016lx]\n", + m->psw_mask, a->psw_mask); + } + + if (m->psw_addr != a->psw_addr) { + fprintf(f, "Mismatch: PSW addr offset master: [%016lx] - PSW addr offset apprentice: [%016lx]\n", + m->psw_addr, a->psw_addr); + } + + /* Skip return address register and stack register for comparison */ + for (i = 0; i < 14; i++) { + if (m->gregs[i] != a->gregs[i]) { + fprintf(f, "Mismatch: r%d master: [%016lx] - r%d apprentice: [%016lx]\n", + i, m->gregs[i], i, a->gregs[i]); + } + } + + for (i = 0; i < 16; i++) { + if (*(uint64_t *)&m->fpregs.fprs[i] != *(uint64_t *)&a->fpregs.fprs[i]) { + fprintf(f, "Mismatch: f%d master: [%016lx] - f%d apprentice: [%016lx]\n", + i, *(uint64_t *)&m->fpregs.fprs[i], + i, *(uint64_t *)&a->fpregs.fprs[i]); + } + } + + if (m->fpregs.fpc != a->fpregs.fpc) { + fprintf(f, "Mismatch: FPC master: [%08x] - FPC apprentice: [%08x]\n", + m->fpregs.fpc, a->fpregs.fpc); + } + + return !ferror(f); +} diff --git a/risu_reginfo_s390x.h b/risu_reginfo_s390x.h new file mode 100644 index 0000000..b55a11d --- /dev/null +++ b/risu_reginfo_s390x.h @@ -0,0 +1,23 @@ +/****************************************************************************** + * Copyright 2023 Red Hat Inc. + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * Thomas Huth - initial implementation + *****************************************************************************/ + +#ifndef RISU_REGINFO_S390X_H +#define RISU_REGINFO_S390X_H + +struct reginfo { + uint32_t faulting_insn; + uint64_t psw_mask; + uint64_t psw_addr; + gregset_t gregs; + fpregset_t fpregs; +}; + +#endif /* RISU_REGINFO_S390X_H */ diff --git a/risu_s390x.c b/risu_s390x.c new file mode 100644 index 0000000..4a83869 --- /dev/null +++ b/risu_s390x.c @@ -0,0 +1,48 @@ +/****************************************************************************** + * Copyright 2023 Red Hat Inc. + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * Thomas Huth - initial implementation + *****************************************************************************/ + +#include + +#include "risu.h" + +void advance_pc(void *vuc) +{ + /* + * Note: The PSW address already points to the next instruction + * after we get a SIGILL, so we must not advance it here! + */ + // ucontext_t *uc = (ucontext_t *) vuc; + // uc->uc_mcontext.psw.addr += 4; +} + +void set_ucontext_paramreg(void *vuc, uint64_t value) +{ + ucontext_t *uc = vuc; + uc->uc_mcontext.gregs[0] = value; +} + +uint64_t get_reginfo_paramreg(struct reginfo *ri) +{ + return ri->gregs[0]; +} + +RisuOp get_risuop(struct reginfo *ri) +{ + uint32_t insn = ri->faulting_insn; + uint32_t op = insn & 0xff; + uint32_t key = insn & ~0xff; + return (key != 0x835a0f00) ? OP_SIGILL : op; +} + +uintptr_t get_pc(struct reginfo *ri) +{ + return ri->psw_addr; +} diff --git a/test_s390x.S b/test_s390x.S new file mode 100644 index 0000000..b67594f --- /dev/null +++ b/test_s390x.S @@ -0,0 +1,32 @@ +/***************************************************************************** + * Copyright 2023 Red Hat Inc. + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * Thomas Huth - initial implementation + *****************************************************************************/ + + /* Initialise the general purpose registers */ + lgfi %r0, 0 + lgfi %r1, 0x1111111 + lgfi %r2, 0x2222222 + lgfi %r3, 0x3333333 + lgfi %r4, 0x4444444 + lgfi %r5, 0x5555555 + lgfi %r6, 0x6666666 + lgfi %r7, 0x7777777 + lgfi %r8, 0x8888888 + lgfi %r9, 0x9999999 + lgfi %r10, 0xaaaaaaa + lgfi %r11, 0xbbbbbbb + lgfi %r12, 0xccccccc + lgfi %r13, 0xddddddd + lgfi %r14, 0xeeeeeee + + /* do compare */ + .int 0x835a0f00 + /* exit test */ + .int 0x835a0f01 From patchwork Mon Sep 4 14:00:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 1829623 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Mon, 04 Sep 2023 10:00:48 -0400 X-MC-Unique: 4cCWOVKrPLG1p2NE9tIMOw-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 865AA3C025CB; Mon, 4 Sep 2023 14:00:47 +0000 (UTC) Received: from thuth.com (unknown [10.39.193.108]) by smtp.corp.redhat.com (Postfix) with ESMTP id F3DB11121314; Mon, 4 Sep 2023 14:00:45 +0000 (UTC) From: Thomas Huth To: Peter Maydell Cc: qemu-s390x@nongnu.org, qemu-devel@nongnu.org, Richard Henderson , Ilya Leoshkevich , David Hildenbrand Subject: [risu PATCH 2/4] s390x: Add simple s390x.risu file Date: Mon, 4 Sep 2023 16:00:38 +0200 Message-Id: <20230904140040.33153-3-thuth@redhat.com> In-Reply-To: <20230904140040.33153-1-thuth@redhat.com> References: <20230904140040.33153-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This only adds a limited set of s390x instructions for initial testing. More instructions will be added later. Signed-off-by: Thomas Huth Acked-by: Ilya Leoshkevich --- s390x.risu | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 s390x.risu diff --git a/s390x.risu b/s390x.risu new file mode 100644 index 0000000..3ad7015 --- /dev/null +++ b/s390x.risu @@ -0,0 +1,48 @@ +############################################################################### +# Copyright 2023 Red Hat Inc. +# All rights reserved. This program and the accompanying materials +# are made available under the terms of the Eclipse Public License v1.0 +# which accompanies this distribution, and is available at +# http://www.eclipse.org/legal/epl-v10.html +# +# Contributors: +# Thomas Huth - initial implementation +############################################################################### + +.mode s390x + +# format:RR Add (register + register, 32 bit) +AR Z 00011010 r1:4 r2:4 + +# format:RRE Add (register + register, 64 bit) +AGR Z 10111001 00001000 00000000 r1:4 r2:4 + +# format:RRE Add (register + register, 32 bit to 64 bit) +AGFR Z 10111001 00011000 00000000 r1:4 r2:4 + +# format:RRF-a Add (three registers, 32 bit) +ARK STFLE45 10111001 11111000 r3:4 0000 r1:4 r2:4 + +# format:RRF-a Add (three registers, 64 bit) +AGRK STFLE45 10111001 11101000 r3:4 0000 r1:4 r2:4 + + +# format:RRE Add Halfword Immediate (32 bit) +AHI Z 10100111 r1:4 1010 i2:16 + +# format:RI Add Halfword Immediate (64 bit) +AGHI Z 10100111 r1:4 1011 i2:16 + + +# format:RR Add Logical (32 bit) +ALR Z 00011110 r1:4 r2:4 + +# format:RRE Add Logical (64 bit) +ALGR Z 10111001 00001010 00000000 r1:4 r2:4 + +# format:RRE Add Logical (32 bit to 64 bit) +ALGFR Z 10111001 00011010 00000000 r1:4 r2:4 + + +# format:RRF-c Population Count +POPCNT STFLE45 10111001 11100001 m3:4 0000 r1:4 r2:4 From patchwork Mon Sep 4 14:00:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 1829622 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 header.s=mimecast20190719 header.b=aGGiqKIq; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RfVj33fzrz1yh1 for ; Tue, 5 Sep 2023 00:03:19 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qdA8v-00074G-JC; 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Mon, 04 Sep 2023 10:00:50 -0400 X-MC-Unique: nB9UkFmSPQGbZCFc-CMZhA-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 93B09939EC3; Mon, 4 Sep 2023 14:00:49 +0000 (UTC) Received: from thuth.com (unknown [10.39.193.108]) by smtp.corp.redhat.com (Postfix) with ESMTP id 0B7EA1121314; Mon, 4 Sep 2023 14:00:47 +0000 (UTC) From: Thomas Huth To: Peter Maydell Cc: qemu-s390x@nongnu.org, qemu-devel@nongnu.org, Richard Henderson , Ilya Leoshkevich , David Hildenbrand Subject: [risu PATCH 3/4] s390x: Add basic risugen perl module for s390x Date: Mon, 4 Sep 2023 16:00:39 +0200 Message-Id: <20230904140040.33153-4-thuth@redhat.com> In-Reply-To: <20230904140040.33153-1-thuth@redhat.com> References: <20230904140040.33153-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This implements support for simple 16-bit and 32-bit instructions. Support for 48-bit instructions and support for load/store memory instructions is not implemented yet. Signed-off-by: Thomas Huth --- risugen_s390x.pm | 194 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 194 insertions(+) create mode 100644 risugen_s390x.pm diff --git a/risugen_s390x.pm b/risugen_s390x.pm new file mode 100644 index 0000000..c58d3c1 --- /dev/null +++ b/risugen_s390x.pm @@ -0,0 +1,194 @@ +#!/usr/bin/perl -w +############################################################################### +# Copyright 2023 Red Hat Inc. +# All rights reserved. This program and the accompanying materials +# are made available under the terms of the Eclipse Public License v1.0 +# which accompanies this distribution, and is available at +# http://www.eclipse.org/legal/epl-v10.html +# +# Contributors: +# Thomas Huth - initial implementation (based on risugen_ppc64.pm etc.) +############################################################################### + +# risugen -- generate a test binary file for use with risu +# See 'risugen --help' for usage information. +package risugen_s390x; + +use strict; +use warnings; + +use risugen_common; + +require Exporter; + +our @ISA = qw(Exporter); +our @EXPORT = qw(write_test_code); + +my $periodic_reg_random = 1; + +# Maximum alignment restriction permitted for a memory op. +my $MAXALIGN = 64; + +sub write_mov_ri($$$) +{ + my ($r, $imm_h, $imm_l) = @_; + + # LGFI + insn16(0xc0 << 8 | $r << 4 | 0x1); + insn32($imm_l); + # IIHF r,imm_high + insn16(0xc0 << 8 | $r << 4 | 0x8); + insn32($imm_h); +} + +sub write_mov_fp($$) +{ + my ($r, $imm) = @_; + + write_mov_ri(0, ~$imm, $imm); + # LDGR + insn32(0xb3c1 << 16 | $r << 4); +} + +sub write_random_regdata() +{ + # Floating point registers + for (my $i = 0; $i < 16; $i++) { + write_mov_fp($i, rand(0xffffffff)); + } + + # Load FPC (via r0) + write_mov_ri(0, 0, (rand(0xffffffff) & 0xfcfcff77)); + insn32(0xb3840000); + + # general purpose registers (except return addr in r14 and the stack in r15) + for (my $i = 0; $i < 14; $i++) { + write_mov_ri($i, rand(0xffffffff), rand(0xffffffff)); + } +} + +my $OP_COMPARE = 0; # compare registers +my $OP_TESTEND = 1; # end of test, stop + +sub write_random_register_data() +{ + write_random_regdata(); + write_risuop($OP_COMPARE); +} + +sub gen_one_insn($$) +{ + # Given an instruction-details array, generate an instruction + my $constraintfailures = 0; + + INSN: while(1) { + my ($forcecond, $rec) = @_; + my $insn = int(rand(0xffffffff)); + my $insnname = $rec->{name}; + my $insnwidth = $rec->{width}; + my $fixedbits = $rec->{fixedbits}; + my $fixedbitmask = $rec->{fixedbitmask}; + my $constraint = $rec->{blocks}{"constraints"}; + my $memblock = $rec->{blocks}{"memory"}; + + $insn &= ~$fixedbitmask; + $insn |= $fixedbits; + + for my $tuple (@{ $rec->{fields} }) { + my ($var, $pos, $mask) = @$tuple; + my $val = ($insn >> $pos) & $mask; + # Check constraints here: Do not allow to use or modify + # the return address (r14) or stack pointer (r15) + next INSN if ($var =~ /^r/ && (($val == 14) || ($val == 15))); + } + + if (defined $constraint) { + # user-specified constraint: evaluate in an environment + # with variables set corresponding to the variable fields. + my $v = eval_with_fields($insnname, $insn, $rec, "constraints", $constraint); + if (!$v) { + $constraintfailures++; + if ($constraintfailures > 10000) { + print "10000 consecutive constraint failures for $insnname constraints string:\n$constraint\n"; + exit (1); + } + next INSN; + } + } + + # OK, we got a good one + $constraintfailures = 0; + + my $basereg; + + if (defined $memblock) { + die "memblock handling has not been implemented yet." + } + + if ($insnwidth == 16) { + insn16(($insn >> 16) & 0xffff); + } else { + insn32($insn); + } + + return; + } +} + +sub write_risuop($) +{ + my ($op) = @_; + insn32(0x835a0f00 | $op); +} + +sub write_test_code($) +{ + my ($params) = @_; + + my $condprob = $params->{ 'condprob' }; + my $numinsns = $params->{ 'numinsns' }; + my $outfile = $params->{ 'outfile' }; + + my %insn_details = %{ $params->{ 'details' } }; + my @keys = @{ $params->{ 'keys' } }; + + set_endian(1); + + open_bin($outfile); + + # convert from probability that insn will be conditional to + # probability of forcing insn to unconditional + $condprob = 1 - $condprob; + + # TODO better random number generator? + srand(0); + + print "Generating code using patterns: @keys...\n"; + progress_start(78, $numinsns); + + if (grep { defined($insn_details{$_}->{blocks}->{"memory"}) } @keys) { + write_memblock_setup(); + } + + # memblock setup doesn't clean its registers, so this must come afterwards. + write_random_register_data(); + + for my $i (1..$numinsns) { + my $insn_enc = $keys[int rand (@keys)]; + #dump_insn_details($insn_enc, $insn_details{$insn_enc}); + my $forcecond = (rand() < $condprob) ? 1 : 0; + gen_one_insn($forcecond, $insn_details{$insn_enc}); + write_risuop($OP_COMPARE); + # Rewrite the registers periodically. This avoids the tendency + # for the VFP registers to decay to NaNs and zeroes. + if ($periodic_reg_random && ($i % 100) == 0) { + write_random_register_data(); + } + progress_update($i); + } + write_risuop($OP_TESTEND); + progress_end(); + close_bin(); +} + +1; From patchwork Mon Sep 4 14:00:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 1829621 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 header.s=mimecast20190719 header.b=U7WxnrUI; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RfVhc4SZGz1yh1 for ; Tue, 5 Sep 2023 00:02:56 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qdA8r-00072O-7B; Mon, 04 Sep 2023 10:01:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qdA8Q-0006to-DK for qemu-devel@nongnu.org; Mon, 04 Sep 2023 10:01:03 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qdA8N-00089E-Nl for qemu-devel@nongnu.org; Mon, 04 Sep 2023 10:00:57 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1693836053; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Zfoc5byNma2/tAzL7Or4qEYp+n+T2JV1qukJ2JhJ+EQ=; b=U7WxnrUI5pAxxjbCuYU5zjxuIkeQgXMUlGBpRWyliI2obGCYByA+Mz4IFamqfhf2fk688y Ol/r6pBN1PyFZ+1yW404SWI2Yte6Ygfw2FqL9rarRNp4C1htEraBCI2ql/2gZSt8fOXO/F PC1+VVF7HToGa4Ad9Wa5B43LOyLYspI= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-479-5GoUcvEAM9CButvFY7mP_g-1; Mon, 04 Sep 2023 10:00:52 -0400 X-MC-Unique: 5GoUcvEAM9CButvFY7mP_g-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 845378015AA; Mon, 4 Sep 2023 14:00:51 +0000 (UTC) Received: from thuth.com (unknown [10.39.193.108]) by smtp.corp.redhat.com (Postfix) with ESMTP id D950F1121314; Mon, 4 Sep 2023 14:00:49 +0000 (UTC) From: Thomas Huth To: Peter Maydell Cc: qemu-s390x@nongnu.org, qemu-devel@nongnu.org, Richard Henderson , Ilya Leoshkevich , David Hildenbrand Subject: [risu PATCH 4/4] s390x: Update the configure script for s390x support Date: Mon, 4 Sep 2023 16:00:40 +0200 Message-Id: <20230904140040.33153-5-thuth@redhat.com> In-Reply-To: <20230904140040.33153-1-thuth@redhat.com> References: <20230904140040.33153-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Auto-detect s390x hosts and add s390x information to the help text. Signed-off-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé --- configure | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configure b/configure index ca2d7db..2f7c580 100755 --- a/configure +++ b/configure @@ -58,6 +58,8 @@ guess_arch() { ARCH="m68k" elif check_define __powerpc64__ ; then ARCH="ppc64" + elif check_define __s390x__ ; then + ARCH="s390x" else echo "This cpu is not supported by risu. Try -h. " >&2 exit 1 @@ -139,7 +141,7 @@ Some influential environment variables: prefixed with the given string. ARCH force target architecture instead of trying to detect it. - Valid values=[arm|aarch64|ppc64|ppc64le|m68k] + Valid values=[arm|aarch64|m68k|ppc64|ppc64le|s390x] CC C compiler command CFLAGS C compiler flags