From patchwork Fri Aug 18 10:34:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1822954 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=qiyJDYcF; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RS3jR6Dclz1yfn for ; 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Fri, 18 Aug 2023 03:34:36 -0700 (PDT) Received: from localhost.localdomain ([92.88.170.41]) by smtp.gmail.com with ESMTPSA id r11-20020a5d4e4b000000b00317b063590fsm2330351wrt.55.2023.08.18.03.34.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 18 Aug 2023 03:34:36 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Huacai Chen , Song Gao , Xiaojuan Yang , Jiajie Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 1/4] target/loongarch: Log I/O write accesses to CSR registers Date: Fri, 18 Aug 2023 12:34:22 +0200 Message-ID: <20230818103425.16271-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230818103425.16271-1-philmd@linaro.org> References: <20230818103425.16271-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Various CSR registers have Read/Write fields. We might want to see guest trying to change such registers. Signed-off-by: Philippe Mathieu-Daudé --- target/loongarch/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index ad93ecac92..7107968699 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -544,6 +544,8 @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp) static void loongarch_qemu_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { + qemu_log_mask(LOG_UNIMP, "[%s]: Unimplemented reg 0x%" HWADDR_PRIx "\n", + __func__, addr); } static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) From patchwork Fri Aug 18 10:34:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1822963 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; 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Fri, 18 Aug 2023 03:34:42 -0700 (PDT) Received: from localhost.localdomain ([92.88.170.41]) by smtp.gmail.com with ESMTPSA id l11-20020a1c790b000000b003fbca942499sm5762728wme.14.2023.08.18.03.34.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 18 Aug 2023 03:34:41 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Huacai Chen , Song Gao , Xiaojuan Yang , Jiajie Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 2/4] target/loongarch: Remove duplicated disas_set_info assignment Date: Fri, 18 Aug 2023 12:34:23 +0200 Message-ID: <20230818103425.16271-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230818103425.16271-1-philmd@linaro.org> References: <20230818103425.16271-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Commit 228021f05e ("target/loongarch: Add core definition") sets disas_set_info to loongarch_cpu_disas_set_info. Probably due to a failed git-rebase, commit ca61e75071 ("target/loongarch: Add gdb support") also sets it to the same value. Remove the duplication. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/loongarch/cpu.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 7107968699..dc617be36f 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -723,7 +723,6 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data) cc->disas_set_info = loongarch_cpu_disas_set_info; cc->gdb_read_register = loongarch_cpu_gdb_read_register; cc->gdb_write_register = loongarch_cpu_gdb_write_register; - cc->disas_set_info = loongarch_cpu_disas_set_info; cc->gdb_num_core_regs = 35; cc->gdb_core_xml_file = "loongarch-base64.xml"; cc->gdb_stop_before_watchpoint = true; From patchwork Fri Aug 18 10:34:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1822947 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Fri, 18 Aug 2023 03:34:48 -0700 (PDT) Received: from localhost.localdomain ([92.88.170.41]) by smtp.gmail.com with ESMTPSA id l3-20020a1ced03000000b003fe1a96845bsm5816099wmh.2.2023.08.18.03.34.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 18 Aug 2023 03:34:47 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Huacai Chen , Song Gao , Xiaojuan Yang , Jiajie Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 3/4] target/loongarch: Rename 64-bit specific functions Date: Fri, 18 Aug 2023 12:34:24 +0200 Message-ID: <20230818103425.16271-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230818103425.16271-1-philmd@linaro.org> References: <20230818103425.16271-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org These functions are specific to loongarch64 cores. Rename including the '64' suffix in preparation of supporting loongarch32 cores. Signed-off-by: Philippe Mathieu-Daudé --- target/loongarch/cpu.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index dc617be36f..19572e37ad 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -76,7 +76,7 @@ void G_NORETURN do_raise_exception(CPULoongArchState *env, cpu_loop_exit_restore(cs, pc); } -static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) +static void loongarch64_cpu_set_pc(CPUState *cs, vaddr value) { LoongArchCPU *cpu = LOONGARCH_CPU(cs); CPULoongArchState *env = &cpu->env; @@ -84,7 +84,7 @@ static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) env->pc = value; } -static vaddr loongarch_cpu_get_pc(CPUState *cs) +static vaddr loongarch64_cpu_get_pc(CPUState *cs) { LoongArchCPU *cpu = LOONGARCH_CPU(cs); CPULoongArchState *env = &cpu->env; @@ -356,7 +356,7 @@ static bool loongarch_cpu_has_work(CPUState *cs) #endif } -static void loongarch_la464_initfn(Object *obj) +static void loongarch64_la464_initfn(Object *obj) { LoongArchCPU *cpu = LOONGARCH_CPU(obj); CPULoongArchState *env = &cpu->env; @@ -694,7 +694,7 @@ static const struct SysemuCPUOps loongarch_sysemu_ops = { }; #endif -static gchar *loongarch_gdb_arch_name(CPUState *cs) +static gchar *loongarch64_gdb_arch_name(CPUState *cs) { return g_strdup("loongarch64"); } @@ -714,8 +714,8 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data) cc->class_by_name = loongarch_cpu_class_by_name; cc->has_work = loongarch_cpu_has_work; cc->dump_state = loongarch_cpu_dump_state; - cc->set_pc = loongarch_cpu_set_pc; - cc->get_pc = loongarch_cpu_get_pc; + cc->set_pc = loongarch64_cpu_set_pc; + cc->get_pc = loongarch64_cpu_get_pc; #ifndef CONFIG_USER_ONLY dc->vmsd = &vmstate_loongarch_cpu; cc->sysemu_ops = &loongarch_sysemu_ops; @@ -726,14 +726,14 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data) cc->gdb_num_core_regs = 35; cc->gdb_core_xml_file = "loongarch-base64.xml"; cc->gdb_stop_before_watchpoint = true; - cc->gdb_arch_name = loongarch_gdb_arch_name; + cc->gdb_arch_name = loongarch64_gdb_arch_name; #ifdef CONFIG_TCG cc->tcg_ops = &loongarch_tcg_ops; #endif } -#define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \ +#define DEFINE_LOONGARCH64_CPU_TYPE(model, initfn) \ { \ .parent = TYPE_LOONGARCH_CPU, \ .instance_init = initfn, \ @@ -751,7 +751,7 @@ static const TypeInfo loongarch_cpu_type_infos[] = { .class_size = sizeof(LoongArchCPUClass), .class_init = loongarch_cpu_class_init, }, - DEFINE_LOONGARCH_CPU_TYPE("la464", loongarch_la464_initfn), + DEFINE_LOONGARCH64_CPU_TYPE("la464", loongarch64_la464_initfn), }; DEFINE_TYPES(loongarch_cpu_type_infos) From patchwork Fri Aug 18 10:34:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1822949 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=nHCqP+Xv; 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Fri, 18 Aug 2023 03:34:53 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Huacai Chen , Song Gao , Xiaojuan Yang , Jiajie Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 4/4] target/loongarch: Extract 64-bit specifics to loongarch64_cpu_class_init Date: Fri, 18 Aug 2023 12:34:25 +0200 Message-ID: <20230818103425.16271-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230818103425.16271-1-philmd@linaro.org> References: <20230818103425.16271-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Extract loongarch64 specific code from loongarch_cpu_class_init() to a new loongarch64_cpu_class_init(). Adapt DEFINE_LOONGARCH64_CPU_TYPE() macro. Signed-off-by: Philippe Mathieu-Daudé --- target/loongarch/cpu.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 19572e37ad..6bd5ca93fd 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -694,11 +694,6 @@ static const struct SysemuCPUOps loongarch_sysemu_ops = { }; #endif -static gchar *loongarch64_gdb_arch_name(CPUState *cs) -{ - return g_strdup("loongarch64"); -} - static void loongarch_cpu_class_init(ObjectClass *c, void *data) { LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c); @@ -714,8 +709,6 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data) cc->class_by_name = loongarch_cpu_class_by_name; cc->has_work = loongarch_cpu_has_work; cc->dump_state = loongarch_cpu_dump_state; - cc->set_pc = loongarch64_cpu_set_pc; - cc->get_pc = loongarch64_cpu_get_pc; #ifndef CONFIG_USER_ONLY dc->vmsd = &vmstate_loongarch_cpu; cc->sysemu_ops = &loongarch_sysemu_ops; @@ -723,21 +716,35 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data) cc->disas_set_info = loongarch_cpu_disas_set_info; cc->gdb_read_register = loongarch_cpu_gdb_read_register; cc->gdb_write_register = loongarch_cpu_gdb_write_register; - cc->gdb_num_core_regs = 35; - cc->gdb_core_xml_file = "loongarch-base64.xml"; cc->gdb_stop_before_watchpoint = true; - cc->gdb_arch_name = loongarch64_gdb_arch_name; #ifdef CONFIG_TCG cc->tcg_ops = &loongarch_tcg_ops; #endif } +static gchar *loongarch64_gdb_arch_name(CPUState *cs) +{ + return g_strdup("loongarch64"); +} + +static void loongarch64_cpu_class_init(ObjectClass *c, void *data) +{ + CPUClass *cc = CPU_CLASS(c); + + cc->set_pc = loongarch64_cpu_set_pc; + cc->get_pc = loongarch64_cpu_get_pc; + cc->gdb_num_core_regs = 35; + cc->gdb_core_xml_file = "loongarch-base64.xml"; + cc->gdb_arch_name = loongarch64_gdb_arch_name; +} + #define DEFINE_LOONGARCH64_CPU_TYPE(model, initfn) \ { \ .parent = TYPE_LOONGARCH_CPU, \ - .instance_init = initfn, \ .name = LOONGARCH_CPU_TYPE_NAME(model), \ + .instance_init = initfn, \ + .class_init = loongarch64_cpu_class_init, \ } static const TypeInfo loongarch_cpu_type_infos[] = {