From patchwork Tue Aug 15 20:15:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1821551 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=j9LwFMts; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RQMxL4bFbz1yfb for ; Wed, 16 Aug 2023 06:16:54 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qW0Sc-0001U1-Jq; Tue, 15 Aug 2023 16:16:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qW0Sb-0001Sr-4v for qemu-devel@nongnu.org; Tue, 15 Aug 2023 16:16:13 -0400 Received: from mail-oa1-x32.google.com ([2001:4860:4864:20::32]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qW0SY-0004v8-QF for qemu-devel@nongnu.org; Tue, 15 Aug 2023 16:16:12 -0400 Received: by mail-oa1-x32.google.com with SMTP id 586e51a60fabf-1c4c5375329so2362222fac.2 for ; Tue, 15 Aug 2023 13:16:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1692130569; x=1692735369; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LCch6fM7rUgQScUqXb+DtD/viZ/OLl4eViDfh6qTFO8=; b=j9LwFMtsi6WH7Ga73ugfrKgtABA0Gymig1uj4IbdD4RIyI4i7DSthNoBroglFFWgAY Rvxr56sG/GysFfEvLKsA5mqWgWqAghgNZSJsVmFdas3gATNyaTgRhqRrD2yp3AZvw16t QrfS/3DLXV0BhFGykI+E1Obq+ivsHNXz4vIAlyofsNk6BV+osGCgBHXbKkpG6qrgxJCB XdTSGxMfmJ2z5gTDfjpG6hSHDtN5a88SxHcf5IxtBsUGEWHrVffklR5uqh2LPPuycrsv mXejcE2OYxrO5ZG+qiSzBQBYPl7WE/Tk+6MSpPR2RKy12g4vnFpEylIKQv4BLA4TsRRX R2Rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692130569; x=1692735369; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LCch6fM7rUgQScUqXb+DtD/viZ/OLl4eViDfh6qTFO8=; b=EJ0aYWH7Y2YGwEu9Tb8eShbNplLOdRljuZQ7LoBdpEBf/ciqWjbN4hvZBUXRfqa5Wh Yo1tMjJNO2B0NX+MrKE8EvkPWJBwDrFD2f9WSSLvCSzDvQJc92jyM8+M2kqJ6LyQAmeH r03EH19SvHAXM4IQQEs7FSA3l/fvsF2YFFqBE8bQT2EaGiZBhl6QfMCWv78OW3ttsTvX zmETdBbOvxVFC2YqZs0f+UL0BTHlVPLbKAennRuj/N0xcYrkiMN3bhp8UVUuXYkdjxSM /QEobAexr5fLapOBIt+8z8le/mCJ9deRq/6MCPBEgNU4+S9KAxSy6h5IEe4TVAJKVqaw SPVw== X-Gm-Message-State: AOJu0YygWLZ7LdA2pBsS6IGHFlcsOSzQ70OvNJeiq9d7dkooiJgSL8Pm qMNzpbB2sUBxKrqcGtgHkVulLG3DS152XopONK0= X-Google-Smtp-Source: AGHT+IHnXNJaK4sVw6Mt2yVXR8ww41dZr11W8Rsse9tdJyMD4BHOJga7+uiIwBa+e1IKe0Do86zrmg== X-Received: by 2002:a05:6870:455:b0:1bf:8a8:dfa with SMTP id i21-20020a056870045500b001bf08a80dfamr14418578oak.11.1692130568779; Tue, 15 Aug 2023 13:16:08 -0700 (PDT) Received: from grind.. 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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id o14-20020a056870e80e00b001bb5b2a958csm6658203oan.23.2023.08.15.13.16.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 13:16:08 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v7 01/12] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] Date: Tue, 15 Aug 2023 17:15:48 -0300 Message-ID: <20230815201559.398643-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815201559.398643-1-dbarboza@ventanamicro.com> References: <20230815201559.398643-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::32; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We'll add a new CPU type that will enable a considerable amount of extensions. To make it easier for us we'll do a few cleanups in our existing riscv_cpu_extensions[] array. Start by splitting all CPU non-boolean options from it. Create a new riscv_cpu_options[] array for them. Add all these properties in riscv_cpu_add_user_properties() as it is already being done today. 'mmu' and 'pmp' aren't really extensions in the usual way we think about RISC-V extensions. These are closer to CPU features/options, so move both to riscv_cpu_options[] too. In the near future we'll need to match all extensions with all entries in isa_edata_arr[], and so it happens that both 'mmu' and 'pmp' do not have a riscv,isa string (thus, no priv spec version restriction). This further emphasizes the point that these are more a CPU option than an extension. No functional changes made. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 33 +++++++++++++++++++++++---------- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6b93b04453..9a3afc0482 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1752,7 +1752,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) static Property riscv_cpu_extensions[] = { /* Defaults for standard extensions */ - DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), @@ -1764,15 +1763,8 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false), - DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), - DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), - DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), - DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), - DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), - DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), - DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false), DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), @@ -1803,9 +1795,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true), - DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true), - DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), @@ -1849,6 +1839,21 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_END_OF_LIST(), }; +static Property riscv_cpu_options[] = { + DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), + + DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), + DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + + DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), + DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), + + DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), + DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), + + DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), + DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), +}; #ifndef CONFIG_USER_ONLY static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, @@ -1917,6 +1922,14 @@ static void riscv_cpu_add_user_properties(Object *obj) #endif qdev_property_add_static(dev, prop); } + + for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) { + /* Check if KVM created the property already */ + if (object_property_find(obj, riscv_cpu_options[i].name)) { + continue; + } + qdev_property_add_static(dev, &riscv_cpu_options[i]); + } } static Property riscv_cpu_properties[] = { From patchwork Tue Aug 15 20:15:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1821552 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=cuPKye4f; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RQMxg5rTmz1yf2 for ; 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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id o14-20020a056870e80e00b001bb5b2a958csm6658203oan.23.2023.08.15.13.16.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 13:16:11 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v7 02/12] target/riscv/cpu.c: skip 'bool' check when filtering KVM props Date: Tue, 15 Aug 2023 17:15:49 -0300 Message-ID: <20230815201559.398643-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815201559.398643-1-dbarboza@ventanamicro.com> References: <20230815201559.398643-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org After the introduction of riscv_cpu_options[] all properties in riscv_cpu_extensions[] are booleans. This check is now obsolete. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9a3afc0482..f10d40733a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1907,17 +1907,11 @@ static void riscv_cpu_add_user_properties(Object *obj) * Set the default to disabled for every extension * unknown to KVM and error out if the user attempts * to enable any of them. - * - * We're giving a pass for non-bool properties since they're - * not related to the availability of extensions and can be - * safely ignored as is. */ - if (prop->info == &qdev_prop_bool) { - object_property_add(obj, prop->name, "bool", - NULL, cpu_set_cfg_unavailable, - NULL, (void *)prop->name); - continue; - } + object_property_add(obj, prop->name, "bool", + NULL, cpu_set_cfg_unavailable, + NULL, (void *)prop->name); + continue; } #endif qdev_property_add_static(dev, prop); From patchwork Tue Aug 15 20:15:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1821550 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=VAzR02I3; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RQMxL4Xbmz1yf2 for ; Wed, 16 Aug 2023 06:16:54 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qW0Sk-0001Vy-WE; Tue, 15 Aug 2023 16:16:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qW0Sg-0001VQ-Ly for qemu-devel@nongnu.org; Tue, 15 Aug 2023 16:16:18 -0400 Received: from mail-oa1-x2c.google.com ([2001:4860:4864:20::2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qW0Se-0004wD-Cn for qemu-devel@nongnu.org; Tue, 15 Aug 2023 16:16:18 -0400 Received: by mail-oa1-x2c.google.com with SMTP id 586e51a60fabf-1c4d5cc56e2so1438436fac.2 for ; Tue, 15 Aug 2023 13:16:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1692130575; x=1692735375; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HKxo5YuCZUjw8nEJxLWI8Q+BuLO4vaQHkEhOsQ8xDE0=; b=VAzR02I3NBbep1Q28FGCvlllnQJFuqESNZ6a906ZDzD4aFbUiTqy3OAjKNq78aQ7tK hUVRnt4EEUV+emLryOG1WsXHIL9/o8pXvePj/CyGcSwR0SK9UdHLDl+z9yWiQl1BnhdN s4hU6nqXzNqybCmkGgfLBipHkEHpK4BtFN+oKUb1sl+t1jsKJmkiK3DO0DIa1k3FYRkP AFDoUiGUi+ClCvP3ORmulHuxvAiTOdAOGl45yJKxXHpErARI2IXme9YGqbqp6IDkYUzJ /9HcSDxgyyHGfoeXQkAn+SU/H/pd1Ar6mzIFKTgOZ4pRHMsKYq5ym2UnLzqsAE6fuWhd jqIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692130575; x=1692735375; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HKxo5YuCZUjw8nEJxLWI8Q+BuLO4vaQHkEhOsQ8xDE0=; b=Uj8Y9p9tb4vW9YbHshhVq1Z0/+3GecF7o4ojAFVgSlhLsqd8th/B5TLDBY9hnlLukK bT5Dd4cAbrqVJJfYD+7FdDIBOA4R9/VyTAVK+rDSgH7iFlnCurhNLuoosRjxubZt9P8O MIuzipCc/V3PoGls5JcYkUMkpGKPjvcxpD4Me95x1waHb4+9As67ca+FpiHnxlNYZogp Bx3kIgYQDIBi/Pjd961eEDeVwL0wVge08UijrYB/7bLe76ZneB7lQt7i34SLNwtl/Jfc lcH+RI1MtxmUQsWZpWO6Eft88qbcYaSWgiWQu2n8P7dIVn7stY+bN4OBEUMoPubipLBR o5FA== X-Gm-Message-State: AOJu0YzHbOGI8La/H3eMAePMjocws/QHXClSzrfuIGwjCEluo8zEss19 Ek57/CZyQ3m3e7sIO/TEX9Lh7Z4ophCi6tpXgGc= X-Google-Smtp-Source: AGHT+IHqFH38w1cU6oIJEH7fRENGJ3jnmsQhR4dPcL2WFWGnMQaWzhHvwerzV7qlz4D4FOecYxDCbw== X-Received: by 2002:a05:6870:41d1:b0:1bb:a468:9e6c with SMTP id z17-20020a05687041d100b001bba4689e6cmr12131982oac.23.1692130574990; Tue, 15 Aug 2023 13:16:14 -0700 (PDT) Received: from grind.. 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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id o14-20020a056870e80e00b001bb5b2a958csm6658203oan.23.2023.08.15.13.16.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 13:16:14 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v7 03/12] target/riscv/cpu.c: split kvm prop handling to its own helper Date: Tue, 15 Aug 2023 17:15:50 -0300 Message-ID: <20230815201559.398643-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815201559.398643-1-dbarboza@ventanamicro.com> References: <20230815201559.398643-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Future patches will split the existing Property arrays even further, and the existing code in riscv_cpu_add_user_properties() will start to scale bad with it because it's dealing with KVM constraints mixed in with TCG constraints. We're going to pay a high price to share a couple of common lines of code between the two. Create a new riscv_cpu_add_kvm_properties() that will be forked from riscv_cpu_add_user_properties() if we're running KVM. The helper includes all properties that a KVM CPU will add. The rest of riscv_cpu_add_user_properties() body will then be relieved from having to deal with KVM constraints. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 65 ++++++++++++++++++++++++++++++---------------- 1 file changed, 42 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f10d40733a..7f0852a14e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1874,6 +1874,46 @@ static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, } #endif +#ifndef CONFIG_USER_ONLY +static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) +{ + /* Check if KVM created the property already */ + if (object_property_find(obj, prop_name)) { + return; + } + + /* + * Set the default to disabled for every extension + * unknown to KVM and error out if the user attempts + * to enable any of them. + */ + object_property_add(obj, prop_name, "bool", + NULL, cpu_set_cfg_unavailable, + NULL, (void *)prop_name); +} + +static void riscv_cpu_add_kvm_properties(Object *obj) +{ + Property *prop; + DeviceState *dev = DEVICE(obj); + + kvm_riscv_init_user_properties(obj); + riscv_cpu_add_misa_properties(obj); + + for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { + riscv_cpu_add_kvm_unavail_prop(obj, prop->name); + } + + for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) { + /* Check if KVM created the property already */ + if (object_property_find(obj, riscv_cpu_options[i].name)) { + continue; + } + qdev_property_add_static(dev, &riscv_cpu_options[i]); + } +} +#endif + /* * Add CPU properties with user-facing flags. * @@ -1889,39 +1929,18 @@ static void riscv_cpu_add_user_properties(Object *obj) riscv_add_satp_mode_properties(obj); if (kvm_enabled()) { - kvm_riscv_init_user_properties(obj); + riscv_cpu_add_kvm_properties(obj); + return; } #endif riscv_cpu_add_misa_properties(obj); for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { -#ifndef CONFIG_USER_ONLY - if (kvm_enabled()) { - /* Check if KVM created the property already */ - if (object_property_find(obj, prop->name)) { - continue; - } - - /* - * Set the default to disabled for every extension - * unknown to KVM and error out if the user attempts - * to enable any of them. - */ - object_property_add(obj, prop->name, "bool", - NULL, cpu_set_cfg_unavailable, - NULL, (void *)prop->name); - continue; - } -#endif qdev_property_add_static(dev, prop); } for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) { - /* Check if KVM created the property already */ - if (object_property_find(obj, riscv_cpu_options[i].name)) { - continue; - } qdev_property_add_static(dev, &riscv_cpu_options[i]); } } From patchwork Tue Aug 15 20:15:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1821559 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id o14-20020a056870e80e00b001bb5b2a958csm6658203oan.23.2023.08.15.13.16.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 13:16:17 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v7 04/12] target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[] Date: Tue, 15 Aug 2023 17:15:51 -0300 Message-ID: <20230815201559.398643-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815201559.398643-1-dbarboza@ventanamicro.com> References: <20230815201559.398643-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32e; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add DEFINE_PROP_END_OF_LIST() and eliminate the ARRAY_SIZE() usage when iterating in the riscv_cpu_options[] array, making it similar to what we already do when working with riscv_cpu_extensions[]. We also have a more sophisticated motivation behind this change. In the future we might need to export riscv_cpu_options[] to other files, and ARRAY_LIST() doesn't work properly in that case because the array size isn't exposed to the header file. Here's a future sight of what we would deal with: ./target/riscv/kvm.c:1057:5: error: nested extern declaration of 'riscv_cpu_add_misa_properties' [-Werror=nested-externs] n file included from ../target/riscv/kvm.c:19: home/danielhb/work/qemu/include/qemu/osdep.h:473:31: error: invalid application of 'sizeof' to incomplete type 'const RISCVCPUMultiExtConfig[]' 473 | #define ARRAY_SIZE(x) ((sizeof(x) / sizeof((x)[0])) + \ | ^ ./target/riscv/kvm.c:1047:29: note: in expansion of macro 'ARRAY_SIZE' 1047 | for (int i = 0; i < ARRAY_SIZE(_array); i++) { \ | ^~~~~~~~~~ ./target/riscv/kvm.c:1059:5: note: in expansion of macro 'ADD_UNAVAIL_KVM_PROP_ARRAY' 1059 | ADD_UNAVAIL_KVM_PROP_ARRAY(obj, riscv_cpu_extensions); | ^~~~~~~~~~~~~~~~~~~~~~~~~~ home/danielhb/work/qemu/include/qemu/osdep.h:473:31: error: invalid application of 'sizeof' to incomplete type 'const RISCVCPUMultiExtConfig[]' 473 | #define ARRAY_SIZE(x) ((sizeof(x) / sizeof((x)[0])) + \ | ^ ./target/riscv/kvm.c:1047:29: note: in expansion of macro 'ARRAY_SIZE' 1047 | for (int i = 0; i < ARRAY_SIZE(_array); i++) { \ Homogenize the present and change the future by using DEFINE_PROP_END_OF_LIST() in riscv_cpu_options[]. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7f0852a14e..854c56b6d0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1853,6 +1853,8 @@ static Property riscv_cpu_options[] = { DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), + + DEFINE_PROP_END_OF_LIST(), }; #ifndef CONFIG_USER_ONLY @@ -1904,12 +1906,12 @@ static void riscv_cpu_add_kvm_properties(Object *obj) riscv_cpu_add_kvm_unavail_prop(obj, prop->name); } - for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) { + for (prop = riscv_cpu_options; prop && prop->name; prop++) { /* Check if KVM created the property already */ - if (object_property_find(obj, riscv_cpu_options[i].name)) { + if (object_property_find(obj, prop->name)) { continue; } - qdev_property_add_static(dev, &riscv_cpu_options[i]); + qdev_property_add_static(dev, prop); } } #endif @@ -1940,8 +1942,8 @@ static void riscv_cpu_add_user_properties(Object *obj) qdev_property_add_static(dev, prop); } - for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) { - qdev_property_add_static(dev, &riscv_cpu_options[i]); + for (prop = riscv_cpu_options; prop && prop->name; prop++) { + qdev_property_add_static(dev, prop); } } From patchwork Tue Aug 15 20:15:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1821556 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=HO2KPJ2/; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RQMyl50fnz1yf2 for ; Wed, 16 Aug 2023 06:18:07 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qW0So-0001Xj-Ot; Tue, 15 Aug 2023 16:16:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qW0Sn-0001XO-An for qemu-devel@nongnu.org; Tue, 15 Aug 2023 16:16:25 -0400 Received: from mail-ot1-x32e.google.com ([2607:f8b0:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qW0Sk-0004xV-U2 for qemu-devel@nongnu.org; Tue, 15 Aug 2023 16:16:25 -0400 Received: by mail-ot1-x32e.google.com with SMTP id 46e09a7af769-6bd0a0a675dso4891769a34.2 for ; Tue, 15 Aug 2023 13:16:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1692130581; x=1692735381; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=U6Gqq8xsXFn/VlblXeiMzNhXqLfn/OYfOtsv/+5rfiY=; b=HO2KPJ2/2qkyjUmrDo1pVBoC5XdAxlzANX41RmQWnSIo995vcbxQTjmv0MXpbeplOv SVRZUOP+vzb1/wESWtQnshCjqFSCdi7KM1Ae4x1K5VV0yRARivh0hPccnjojjzrP7RjZ tIY08reNseLSEkw1dBL3us8hJ/1a64z5RN8PvCf5cGRLd9KnzZCUY5k1p0whE1ibvcS8 XWwOW968cZOMY7I0PtDSbARn03kk3jmj4KMwXiheZm5iXtotsgi5qqm8p2rIiKsM+jjK 4BE+n4u05aOm0/+PfpQ7oUv18g2pKtkrb7RuDDoeN1xihG3sXtOgcedT3FnwpuYAM0PC h4Eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692130581; x=1692735381; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U6Gqq8xsXFn/VlblXeiMzNhXqLfn/OYfOtsv/+5rfiY=; b=c5FgykAq0OgOnWTLhS75hUwQPdVsM+piGQKNHVi2uV6TqVbEAY0gr1yBtF/krr0HqS SVEYcNYUjPthx6w56LmmT7YGMH5QVQ7k9thc6WIJSK6CHoqheXXhS5hyEwPFTgOqBa+S 8DQyHTIyUKBPHtgKlijPYZ1fCWI7RIclBei5+yBy2nPlqEsxiGb+8NAP091XCnifpCKB 9TRaDBz78y/kMyWzALz2CLZMGBdmbtbdcEdTvGl8Nr8RQv8zHNseUHu/P217OUW6M8Zy yg6yrS4jyIP4nE06cK7jdjjcCdGkt4ttvKDY+EVCEGghVgOeUvVUOGY15iqCcPUD0xks BpxQ== X-Gm-Message-State: AOJu0Ywhx9QuMfb71EopmaSLVM7jvspPz5huHXfmDpZ+N6tQUIX7RUMy i2OAVITEhKKRPg7DkdVn7A5DT7v6L/Sm3IMUGSQ= X-Google-Smtp-Source: AGHT+IHF29wNEwMMnVYslHYyxGK2YsoDYsi2NdAKFvGFv2+5+ntMhgYprHYKK0GyL9p0TQ+gQZS18A== X-Received: by 2002:a05:6870:5814:b0:1ba:989b:ca65 with SMTP id r20-20020a056870581400b001ba989bca65mr15182555oap.19.1692130581394; Tue, 15 Aug 2023 13:16:21 -0700 (PDT) Received: from grind.. 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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id o14-20020a056870e80e00b001bb5b2a958csm6658203oan.23.2023.08.15.13.16.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 13:16:21 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v7 05/12] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[] Date: Tue, 15 Aug 2023 17:15:52 -0300 Message-ID: <20230815201559.398643-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815201559.398643-1-dbarboza@ventanamicro.com> References: <20230815201559.398643-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32e; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Our goal is to make riscv_cpu_extensions[] hold only ratified, non-vendor extensions. Create a new riscv_cpu_vendor_exts[] array for them, changing riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties() accordingly. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 39 +++++++++++++++++++++++++-------------- 1 file changed, 25 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 854c56b6d0..3cd025b678 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1807,20 +1807,6 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false), DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false), - /* Vendor-specific custom extensions */ - DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), - DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), - DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), - DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), - DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), - DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), - DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), - DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), - DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), - DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), - DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), - DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), - /* These are experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), @@ -1839,6 +1825,23 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_END_OF_LIST(), }; +static Property riscv_cpu_vendor_exts[] = { + DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), + DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), + DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), + DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), + DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), + DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), + DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), + DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), + DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), + DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), + DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), + DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), + + DEFINE_PROP_END_OF_LIST(), +}; + static Property riscv_cpu_options[] = { DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), @@ -1906,6 +1909,10 @@ static void riscv_cpu_add_kvm_properties(Object *obj) riscv_cpu_add_kvm_unavail_prop(obj, prop->name); } + for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) { + riscv_cpu_add_kvm_unavail_prop(obj, prop->name); + } + for (prop = riscv_cpu_options; prop && prop->name; prop++) { /* Check if KVM created the property already */ if (object_property_find(obj, prop->name)) { @@ -1945,6 +1952,10 @@ static void riscv_cpu_add_user_properties(Object *obj) for (prop = riscv_cpu_options; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); } + + for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) { + qdev_property_add_static(dev, prop); + } } static Property riscv_cpu_properties[] = { From patchwork Tue Aug 15 20:15:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1821555 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id o14-20020a056870e80e00b001bb5b2a958csm6658203oan.23.2023.08.15.13.16.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 13:16:23 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v7 06/12] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[] Date: Tue, 15 Aug 2023 17:15:53 -0300 Message-ID: <20230815201559.398643-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815201559.398643-1-dbarboza@ventanamicro.com> References: <20230815201559.398643-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::30; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Create a new riscv_cpu_experimental_exts[] to store the non-ratified extensions properties. Once they are ratified we'll move them back to riscv_cpu_extensions[]. riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties() are changed to keep adding non-ratified properties to users. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 42 +++++++++++++++++++++++++++--------------- 1 file changed, 27 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3cd025b678..520c5c9f96 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1807,21 +1807,6 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false), DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false), - /* These are experimental so mark with 'x-' */ - DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), - - /* ePMP 0.9.3 */ - DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), - DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), - DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), - - DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), - DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), - - DEFINE_PROP_BOOL("x-zfbfmin", RISCVCPU, cfg.ext_zfbfmin, false), - DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false), - DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false), - DEFINE_PROP_END_OF_LIST(), }; @@ -1842,6 +1827,25 @@ static Property riscv_cpu_vendor_exts[] = { DEFINE_PROP_END_OF_LIST(), }; +/* These are experimental so mark with 'x-' */ +static Property riscv_cpu_experimental_exts[] = { + DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), + + /* ePMP 0.9.3 */ + DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), + DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), + DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), + + DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), + DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), + + DEFINE_PROP_BOOL("x-zfbfmin", RISCVCPU, cfg.ext_zfbfmin, false), + DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false), + DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false), + + DEFINE_PROP_END_OF_LIST(), +}; + static Property riscv_cpu_options[] = { DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), @@ -1913,6 +1917,10 @@ static void riscv_cpu_add_kvm_properties(Object *obj) riscv_cpu_add_kvm_unavail_prop(obj, prop->name); } + for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) { + riscv_cpu_add_kvm_unavail_prop(obj, prop->name); + } + for (prop = riscv_cpu_options; prop && prop->name; prop++) { /* Check if KVM created the property already */ if (object_property_find(obj, prop->name)) { @@ -1956,6 +1964,10 @@ static void riscv_cpu_add_user_properties(Object *obj) for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); } + + for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) { + qdev_property_add_static(dev, prop); + } } static Property riscv_cpu_properties[] = { From patchwork Tue Aug 15 20:15:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1821554 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id o14-20020a056870e80e00b001bb5b2a958csm6658203oan.23.2023.08.15.13.16.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 13:16:27 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v7 07/12] target/riscv/cpu.c: add ADD_CPU_QDEV_PROPERTIES_ARRAY() macro Date: Tue, 15 Aug 2023 17:15:54 -0300 Message-ID: <20230815201559.398643-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815201559.398643-1-dbarboza@ventanamicro.com> References: <20230815201559.398643-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32b; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The code inside riscv_cpu_add_user_properties() became quite repetitive after recent changes. Add a macro to hide the repetition away. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li --- target/riscv/cpu.c | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 520c5c9f96..8e1d944957 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1883,6 +1883,13 @@ static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, } #endif +#define ADD_CPU_QDEV_PROPERTIES_ARRAY(_dev, _array) \ + do { \ + for (Property *prop = _array; prop && prop->name; prop++) { \ + qdev_property_add_static(_dev, prop); \ + } \ + } while (0) + #ifndef CONFIG_USER_ONLY static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) { @@ -1939,7 +1946,6 @@ static void riscv_cpu_add_kvm_properties(Object *obj) */ static void riscv_cpu_add_user_properties(Object *obj) { - Property *prop; DeviceState *dev = DEVICE(obj); #ifndef CONFIG_USER_ONLY @@ -1953,21 +1959,10 @@ static void riscv_cpu_add_user_properties(Object *obj) riscv_cpu_add_misa_properties(obj); - for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { - qdev_property_add_static(dev, prop); - } - - for (prop = riscv_cpu_options; prop && prop->name; prop++) { - qdev_property_add_static(dev, prop); - } - - for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) { - qdev_property_add_static(dev, prop); - } - - for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) { - qdev_property_add_static(dev, prop); - } + ADD_CPU_QDEV_PROPERTIES_ARRAY(dev, riscv_cpu_extensions); + ADD_CPU_QDEV_PROPERTIES_ARRAY(dev, riscv_cpu_options); + ADD_CPU_QDEV_PROPERTIES_ARRAY(dev, riscv_cpu_vendor_exts); + ADD_CPU_QDEV_PROPERTIES_ARRAY(dev, riscv_cpu_experimental_exts); } static Property riscv_cpu_properties[] = { From patchwork Tue Aug 15 20:15:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1821561 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id o14-20020a056870e80e00b001bb5b2a958csm6658203oan.23.2023.08.15.13.16.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 13:16:30 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v7 08/12] target/riscv/cpu.c: add ADD_UNAVAIL_KVM_PROP_ARRAY() macro Date: Tue, 15 Aug 2023 17:15:55 -0300 Message-ID: <20230815201559.398643-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815201559.398643-1-dbarboza@ventanamicro.com> References: <20230815201559.398643-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Use a macro in riscv_cpu_add_kvm_properties() to eliminate some of its code repetition, similar to what we're already doing with ADD_CPU_QDEV_PROPERTIES_ARRAY(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li --- target/riscv/cpu.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8e1d944957..42f209cd17 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1908,6 +1908,13 @@ static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) NULL, (void *)prop_name); } +#define ADD_UNAVAIL_KVM_PROP_ARRAY(_obj, _array) \ + do { \ + for (Property *prop = _array; prop && prop->name; prop++) { \ + riscv_cpu_add_kvm_unavail_prop(_obj, prop->name); \ + } \ + } while (0) + static void riscv_cpu_add_kvm_properties(Object *obj) { Property *prop; @@ -1916,17 +1923,9 @@ static void riscv_cpu_add_kvm_properties(Object *obj) kvm_riscv_init_user_properties(obj); riscv_cpu_add_misa_properties(obj); - for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { - riscv_cpu_add_kvm_unavail_prop(obj, prop->name); - } - - for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) { - riscv_cpu_add_kvm_unavail_prop(obj, prop->name); - } - - for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) { - riscv_cpu_add_kvm_unavail_prop(obj, prop->name); - } + ADD_UNAVAIL_KVM_PROP_ARRAY(obj, riscv_cpu_extensions); + ADD_UNAVAIL_KVM_PROP_ARRAY(obj, riscv_cpu_vendor_exts); + ADD_UNAVAIL_KVM_PROP_ARRAY(obj, riscv_cpu_experimental_exts); for (prop = riscv_cpu_options; prop && prop->name; prop++) { /* Check if KVM created the property already */ From patchwork Tue Aug 15 20:15:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1821557 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; 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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id o14-20020a056870e80e00b001bb5b2a958csm6658203oan.23.2023.08.15.13.16.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 13:16:33 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v7 09/12] target/riscv/cpu.c: limit cfg->vext_spec log message Date: Tue, 15 Aug 2023 17:15:56 -0300 Message-ID: <20230815201559.398643-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815201559.398643-1-dbarboza@ventanamicro.com> References: <20230815201559.398643-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32b; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Inside riscv_cpu_validate_v() we're always throwing a log message if the user didn't set a vector version via 'vext_spec'. We're going to include one case with the 'max' CPU where env->vext_ver will be set in the cpu_init(). But that alone will not stop the "vector version is not specified" message from appearing. The usefulness of this log message is debatable for the generic CPUs, but for a 'max' CPU type, where we are supposed to deliver a CPU model with all features possible, it's strange to force users to set 'vext_spec' to get rid of this message. Change riscv_cpu_validate_v() to not throw this log message if env->vext_ver is already set. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li --- target/riscv/cpu.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 42f209cd17..33d7fa41d8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -937,8 +937,6 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, Error **errp) { - int vext_version = VEXT_VERSION_1_00_0; - if (!is_power_of_2(cfg->vlen)) { error_setg(errp, "Vector extension VLEN must be power of 2"); return; @@ -961,17 +959,18 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, } if (cfg->vext_spec) { if (!g_strcmp0(cfg->vext_spec, "v1.0")) { - vext_version = VEXT_VERSION_1_00_0; + env->vext_ver = VEXT_VERSION_1_00_0; } else { error_setg(errp, "Unsupported vector spec version '%s'", cfg->vext_spec); return; } - } else { + } else if (env->vext_ver == 0) { qemu_log("vector version is not specified, " "use the default value v1.0\n"); + + env->vext_ver = VEXT_VERSION_1_00_0; } - env->vext_ver = vext_version; } static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) From patchwork Tue Aug 15 20:15:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1821562 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=YuMgEBzC; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RQMzQ3HSxz1yf2 for ; Wed, 16 Aug 2023 06:18:42 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qW0T7-0001hR-Dl; Tue, 15 Aug 2023 16:16:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qW0T3-0001eG-4T for qemu-devel@nongnu.org; Tue, 15 Aug 2023 16:16:43 -0400 Received: from mail-ot1-x330.google.com ([2607:f8b0:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qW0T0-00056x-Kd for qemu-devel@nongnu.org; Tue, 15 Aug 2023 16:16:40 -0400 Received: by mail-ot1-x330.google.com with SMTP id 46e09a7af769-6b9cf1997c4so4856222a34.3 for ; Tue, 15 Aug 2023 13:16:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1692130596; x=1692735396; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SQa80frBZDzPMInF9YH9siPx+DRekb7+dleQtZpjcHk=; b=YuMgEBzCCANFVMl+1tn/om4KjcL6Y58AjbTTdoTGKPM1SYZfa2jDet77djQQNGsg7d PYGXxEN/M64wtIaV6tgaFg3DP4ReL432Izgp4uvlnkZWw3Ioa2tREUcIiaAWZEw/Co2O rAjmdLL00R/Axi4WBGjrSmWqcERN8KhkfvO6Mxtc5g0d0pMOic7VEcOWsRB43wpMMFkH DRWCZyfu6quTY/N8T/EdoScu3mzx1qXNqsW3uCOtp+IYMu1ogBQEMuOuKr3nTXeKOZyL 1IpLDdRAMb4LDzC6OfcCc1lV9/W3Ii8AVJDfENlvCvZwu+KcGVy3daSxUY2PCjomvduw D5ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692130596; x=1692735396; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SQa80frBZDzPMInF9YH9siPx+DRekb7+dleQtZpjcHk=; b=I4NBSliDudojqcXpwjKZKziDOUDs4bRyDJKW6n+MtY3p6WSND+TfVNRswG4DYt3zo6 MgMKRqpV0tHTH5JRxVOJuaMtx9HsfdWzG8ZOJ3eK9nLMRAHwTVFNSIlVBiux0+j0kCb/ 4ErKfJEMJuIAzFo5U8ddst1xR79uImhuv6uvisNI2lF5kyNyXjKKQnGun4iBQrO9YlsU WVLcMKddfbpcWjT75+eHSOgHFZKP4wkUPEfPDjnFXkVsTWD4moRCOKCMWDDxdMf8r+5U TvfueWm42bnI/xcpJEibqitgAqovw3ZuqPTy2mAag7PPsfLXzPhL/6WbB+AWqjEQbKvB 48Ag== X-Gm-Message-State: AOJu0YzNpRrjWJ0F2tjrQ/Jhg/cS9suBI07AUhsJzHsYSpkGdigp8Ra8 BcQwgn1m9JBC0puXBKA+eccGbL9rRVI+LslNorw= X-Google-Smtp-Source: AGHT+IGwL5Uz0ZTx6EkCWLGK/FykNTGYW62FFtdAvMk6JYBBOQIhsDadk3D9G6YlnIsO56X82Idw0A== X-Received: by 2002:a05:6870:ac2b:b0:19f:6711:8e0a with SMTP id kw43-20020a056870ac2b00b0019f67118e0amr16027888oab.32.1692130596202; Tue, 15 Aug 2023 13:16:36 -0700 (PDT) Received: from grind.. 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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id o14-20020a056870e80e00b001bb5b2a958csm6658203oan.23.2023.08.15.13.16.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 13:16:35 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v7 10/12] target/riscv: add 'max' CPU type Date: Tue, 15 Aug 2023 17:15:57 -0300 Message-ID: <20230815201559.398643-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815201559.398643-1-dbarboza@ventanamicro.com> References: <20230815201559.398643-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::330; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The 'max' CPU type is used by tooling to determine what's the most capable CPU a current QEMU version implements. Other archs such as ARM implements this type. Let's add it to RISC-V. What we consider "most capable CPU" in this context are related to ratified, non-vendor extensions. This means that we want the 'max' CPU to enable all (possible) ratified extensions by default. The reasoning behind this design is (1) vendor extensions can conflict with each other and we won't play favorities deciding which one is default or not and (2) non-ratified extensions are always prone to changes, not being stable enough to be enabled by default. All this said, we're still not able to enable all ratified extensions due to conflicts between them. Zfinx and all its dependencies aren't enabled because of a conflict with RVF. zce, zcmp and zcmt are also disabled due to RVD conflicts. When running with 64 bits we're also disabling zcf. MISA bits RVG, RVJ and RVV are also being set manually since they're default disabled. This is the resulting 'riscv,isa' DT for this new CPU: rv64imafdcvh_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_ zfh_zfhmin_zca_zcb_zcd_zba_zbb_zbc_zbkb_zbkc_zbkx_zbs_zk_zkn_zknd_ zkne_zknh_zkr_zks_zksed_zksh_zkt_zve32f_zve64f_zve64d_ smstateen_sscofpmf_sstc_svadu_svinval_svnapot_svpbmt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 57 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 04af50983e..f3fbe37a2c 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -30,6 +30,7 @@ #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") +#define TYPE_RISCV_CPU_MAX RISCV_CPU_TYPE_NAME("max") #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 33d7fa41d8..592808939f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -248,6 +248,7 @@ static const char * const riscv_intr_names[] = { }; static void riscv_cpu_add_user_properties(Object *obj); +static void riscv_init_max_cpu_extensions(Object *obj); const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) { @@ -374,6 +375,25 @@ static void riscv_any_cpu_init(Object *obj) cpu->cfg.pmp = true; } +static void riscv_max_cpu_init(Object *obj) +{ + RISCVCPU *cpu = RISCV_CPU(obj); + CPURISCVState *env = &cpu->env; + RISCVMXL mlx = MXL_RV64; + +#ifdef TARGET_RISCV32 + mlx = MXL_RV32; +#endif + set_misa(env, mlx, 0); + riscv_cpu_add_user_properties(obj); + riscv_init_max_cpu_extensions(obj); + env->priv_ver = PRIV_VERSION_LATEST; +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ? + VM_1_10_SV32 : VM_1_10_SV57); +#endif +} + #if defined(TARGET_RISCV64) static void rv64_base_cpu_init(Object *obj) { @@ -1963,6 +1983,42 @@ static void riscv_cpu_add_user_properties(Object *obj) ADD_CPU_QDEV_PROPERTIES_ARRAY(dev, riscv_cpu_experimental_exts); } +/* + * The 'max' type CPU will have all possible ratified + * non-vendor extensions enabled. + */ +static void riscv_init_max_cpu_extensions(Object *obj) +{ + RISCVCPU *cpu = RISCV_CPU(obj); + CPURISCVState *env = &cpu->env; + Property *prop; + + /* Enable RVG, RVJ and RVV that are disabled by default */ + set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); + + + for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { + object_property_set_bool(obj, prop->name, true, NULL); + } + + /* set vector version */ + env->vext_ver = VEXT_VERSION_1_00_0; + + /* Zfinx is not compatible with F. Disable it */ + object_property_set_bool(obj, "zfinx", false, NULL); + object_property_set_bool(obj, "zdinx", false, NULL); + object_property_set_bool(obj, "zhinx", false, NULL); + object_property_set_bool(obj, "zhinxmin", false, NULL); + + object_property_set_bool(obj, "zce", false, NULL); + object_property_set_bool(obj, "zcmp", false, NULL); + object_property_set_bool(obj, "zcmt", false, NULL); + + if (env->misa_mxl != MXL_RV32) { + object_property_set_bool(obj, "zcf", false, NULL); + } +} + static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), @@ -2301,6 +2357,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { .abstract = true, }, DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init), #if defined(CONFIG_KVM) DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), #endif From patchwork Tue Aug 15 20:15:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1821558 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=Qk8qEsQ7; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RQMyv5q9nz1yfb for ; Wed, 16 Aug 2023 06:18:15 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qW0T7-0001iB-T0; Tue, 15 Aug 2023 16:16:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qW0T6-0001h2-4H for qemu-devel@nongnu.org; Tue, 15 Aug 2023 16:16:44 -0400 Received: from mail-oo1-xc30.google.com ([2607:f8b0:4864:20::c30]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qW0T3-00057g-W4 for qemu-devel@nongnu.org; Tue, 15 Aug 2023 16:16:43 -0400 Received: by mail-oo1-xc30.google.com with SMTP id 006d021491bc7-56d0f4180bbso4303628eaf.1 for ; Tue, 15 Aug 2023 13:16:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1692130600; x=1692735400; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pO3wz5fop7wDys5r1Ax7UI+xFmY6OiD4k73j8kol0RM=; b=Qk8qEsQ7Oap0rO4/dmESf+FGyxAX/N6Ptw++P+t3NuGCNCs14OCMKMe/o58KUn2h5v DoWDn91woZ5kqyJnIi64dvGgYhYUIqQyOhiyWp2SgBnVWxsHiyzJWO4KN6erdcY9E8Fo yrnnFUOvNNzGaDw62pAeKEHXGHlP7cFDy9ZK5olAifl8LEB8RAq/J/XI/Zslom8BGu7+ 6rVqmKLxc3il87ZCzXdGw/TPOzzhlbW+tm49tao9UcxLv8grXDsGrF2ubHKdkJ3nv1EN 7G+rM2PVIdpD+0f8H3YYZcdGvV6vyfDk6Z1Y4n7bXJY/obaCQly1wKY0yjoSR02ThL+o Xo9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692130600; x=1692735400; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pO3wz5fop7wDys5r1Ax7UI+xFmY6OiD4k73j8kol0RM=; b=NHFwydP/b4OL8iAfwMkZVVljs5VqQNavu2rkmGMNFylIPNHccbFjqqpZHTDuIObWbr mJ2s1ccePXykSsx29mR04lELxKhh7cV3Olfgo0PS+ws/hVdpSp9QEucQWPXDtezXtGdH KCR6/kRUv/VAjbyVaReHPaSS/Z5U7P3M9XmOPCwRCtcSWyF/tvEe8wSNGZRm1brlByQh R2scLPGD5+vyuztftlJMi6zl75JJerkTQkhTsCNcRZIic7cH/to+NMgZwyn4jR3s7mBp IkSorP3CeHcEUv5F2wuFHxeUcBscfGJ6bbjH/NYPVnlPN0O75lnkevnc/1XC+mHMS5fX gCxQ== X-Gm-Message-State: AOJu0Yw/yB0ycevTOjgFcA5N9K8Ql9xpvamZvXsAP9R8ggArNnT1nKKA P8HNP1H3r5505j1s3xBNisFkkmbhyCp/r8EmXBc= X-Google-Smtp-Source: AGHT+IHAxYdFaeFyjR9KpuIaRf+PuBmvtTQn/JwH/ddlTGp4HqQf2TWRTgnF1Ah1n9eIWxZuK5ePQg== X-Received: by 2002:a05:6870:3102:b0:1bf:d8a:b5bf with SMTP id v2-20020a056870310200b001bf0d8ab5bfmr16341109oaa.36.1692130599168; Tue, 15 Aug 2023 13:16:39 -0700 (PDT) Received: from grind.. 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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id o14-20020a056870e80e00b001bb5b2a958csm6658203oan.23.2023.08.15.13.16.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 13:16:38 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v7 11/12] avocado, risc-v: add opensbi tests for 'max' CPU Date: Tue, 15 Aug 2023 17:15:58 -0300 Message-ID: <20230815201559.398643-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815201559.398643-1-dbarboza@ventanamicro.com> References: <20230815201559.398643-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c30; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add smoke tests to ensure that we'll not break the 'max' CPU type when adding new ratified extensions to be enabled. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- tests/avocado/riscv_opensbi.py | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py index bfff9cc3c3..15fd57fe51 100644 --- a/tests/avocado/riscv_opensbi.py +++ b/tests/avocado/riscv_opensbi.py @@ -61,3 +61,19 @@ def test_riscv64_virt(self): :avocado: tags=machine:virt """ self.boot_opensbi() + + def test_riscv32_virt_maxcpu(self): + """ + :avocado: tags=arch:riscv32 + :avocado: tags=machine:virt + :avocado: tags=cpu:max + """ + self.boot_opensbi() + + def test_riscv64_virt_maxcpu(self): + """ + :avocado: tags=arch:riscv64 + :avocado: tags=machine:virt + :avocado: tags=cpu:max + """ + self.boot_opensbi() From patchwork Tue Aug 15 20:15:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1821560 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=gmKq3fJj; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RQMz40FVNz1yf2 for ; Wed, 16 Aug 2023 06:18:24 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qW0TA-0001kL-5w; Tue, 15 Aug 2023 16:16:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qW0T8-0001iV-Cf for qemu-devel@nongnu.org; Tue, 15 Aug 2023 16:16:46 -0400 Received: from mail-ot1-x32b.google.com ([2607:f8b0:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qW0T5-00059F-9H for qemu-devel@nongnu.org; Tue, 15 Aug 2023 16:16:46 -0400 Received: by mail-ot1-x32b.google.com with SMTP id 46e09a7af769-6bd0911c95dso5174845a34.3 for ; Tue, 15 Aug 2023 13:16:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1692130602; x=1692735402; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Lo3i5N5BbKo6DP4yawS4oeiSuoKJHFlJGeBJBU9cGgc=; b=gmKq3fJjJzeUjvSGnsU7oCh34vwqmuckT9Bu3NFRHArW7gp6Qa+YSSq9ZmUCgWfzGN eZSpFB5MwI63HhQy5zQxzcRAS8HQX+gyQnFyt1Px+Hiod+fM7Hysac3PXuT5erkBS96L hZQsWG5NT3GGvZkRxnrJS4LjIr8nPVcsu7hNjZPEtMi8o2B663C+3/w2CHAAAsbN4oM3 ijgUVzWgrc8LAUEZTeyytfHlyjzjyqdl1Mwjg6ntE+vQwJn34AG4Ka/idV60X6eXUOS/ jYwT4nwg5z7CIQj+8zN0d04Cri/6F15jG5jXipx4e+0eiU/mjxSOjyTjTcHY8A2gnUCN zKRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692130602; x=1692735402; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lo3i5N5BbKo6DP4yawS4oeiSuoKJHFlJGeBJBU9cGgc=; b=djt4pxb03sTqrcZSc/m+8QdRk9c3IdpEidYhSVJ/kJUo6+KtTu22lgbHDToaOd5CQn HX0ZW+CUBkZxYqmmGQjLWjdAvRnlJRcePVklyaPlUvaHbl7cJq5UqhsNSqy8iZA65CX0 9l0IGB7eFU5JgF9jz6DROLrC5BOSt0lRIUUbzSove+IHzGxAQLBZzOmUyEe0uPhMwINn KDcluwU/QZd0pPD5rh1eMM41roIAhgzYrpfbKE0IQR3DrCqs3xGCAtv0rXtY5/xs9YHt bE4J3n31mN5UkSTftSfwcMf04YtIf28iMMYI0g86NlUYM/5qPOMIR51tqUG0XNaEM86B wafw== X-Gm-Message-State: AOJu0YzAcYXwDMcn1CmNYXS+Xc9mUtpRG0pCQyXYF1YFNIfpNKhJVB6e wvVUn2BTacMKxQmr1nf0192qzsg9cuagv8Td3ds= X-Google-Smtp-Source: AGHT+IGXcxoL6ufyaRynV1T+E9EvKyBaUfKSUqnQcO2PsXCrtjamS4w9CNZZmBVjATPGvvEZb2EzEw== X-Received: by 2002:a05:6870:6091:b0:1bf:440:a055 with SMTP id t17-20020a056870609100b001bf0440a055mr12901224oae.4.1692130602032; Tue, 15 Aug 2023 13:16:42 -0700 (PDT) Received: from grind.. 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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id o14-20020a056870e80e00b001bb5b2a958csm6658203oan.23.2023.08.15.13.16.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 13:16:41 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v7 12/12] target/riscv: deprecate the 'any' CPU type Date: Tue, 15 Aug 2023 17:15:59 -0300 Message-ID: <20230815201559.398643-13-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815201559.398643-1-dbarboza@ventanamicro.com> References: <20230815201559.398643-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32b; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The 'any' CPU type was introduced in commit dc5bd18fa5725 ("RISC-V CPU Core Definition"), being around since the beginning. It's not an easy CPU to use: it's undocumented and its name doesn't tell users much about what the CPU is supposed to bring. 'git log' doesn't help us either in knowing what was the original design of this CPU type. The closest we have is a comment from Alistair [1] where he recalls from memory that the 'any' CPU is supposed to behave like the newly added 'max' CPU. He also suggested that the 'any' CPU should be removed. The default CPUs are rv32 and rv64, so removing the 'any' CPU will have impact only on users that might have a script that uses '-cpu any'. And those users are better off using the default CPUs or the new 'max' CPU. We would love to just remove the code and be done with it, but one does not simply remove a feature in QEMU. We'll put the CPU in quarantine first, letting users know that we have the intent of removing it in the future. [1] https://lists.gnu.org/archive/html/qemu-devel/2023-07/msg02891.html Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- docs/about/deprecated.rst | 12 ++++++++++++ target/riscv/cpu.c | 5 +++++ 2 files changed, 17 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 92a2bafd2b..4ced7427ac 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -371,6 +371,18 @@ QEMU's ``vhost`` feature, which would eliminate the high latency costs under which the 9p ``proxy`` backend currently suffers. However as of to date nobody has indicated plans for such kind of reimplementation unfortunately. +RISC-V 'any' CPU type ``-cpu any`` (since 8.2) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The 'any' CPU type was introduced back in 2018 and has been around since the +initial RISC-V QEMU port. Its usage has always been unclear: users don't know +what to expect from a CPU called 'any', and in fact the CPU does not do anything +special that aren't already done by the default CPUs rv32/rv64. + +After the introduction of the 'max' CPU type RISC-V now has a good coverage +of generic CPUs: rv32 and rv64 as default CPUs and 'max' as a feature complete +CPU for both 32 and 64 bit builds. Users are then discouraged to use the 'any' +CPU type starting in 8.2. Block device options '''''''''''''''''''' diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 592808939f..3930c85341 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1470,6 +1470,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); Error *local_err = NULL; + if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_ANY) != NULL) { + warn_report("The 'any' CPU is deprecated and will be " + "removed in the future."); + } + cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err);