From patchwork Thu Aug 10 12:41:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Song Gao X-Patchwork-Id: 1819834 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RM65R16l7z1yf6 for ; Thu, 10 Aug 2023 22:42:35 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qU4yk-0001Aw-Dd; Thu, 10 Aug 2023 08:41:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qU4yh-00018h-Cx for qemu-devel@nongnu.org; Thu, 10 Aug 2023 08:41:23 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qU4yd-00044E-9B for qemu-devel@nongnu.org; Thu, 10 Aug 2023 08:41:22 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8BxuOjp2tRkaqsUAA--.8735S3; Thu, 10 Aug 2023 20:41:13 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Ax3c7o2tRkoiNTAA--.11480S3; Thu, 10 Aug 2023 20:41:13 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, philmd@linaro.org, maobibo@loongson.cn, yangxiaojuan@loongson.cn Subject: [PATCH v1 1/6] target/loongarch: Fix loongarch_la464_initfn() misses setting LSPW. Date: Thu, 10 Aug 2023 20:41:07 +0800 Message-Id: <20230810124112.236640-2-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230810124112.236640-1-gaosong@loongson.cn> References: <20230810124112.236640-1-gaosong@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Ax3c7o2tRkoiNTAA--.11480S3 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index dd1cd7d7d2..95e00a044c 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -391,6 +391,7 @@ static void loongarch_la464_initfn(Object *obj) data = FIELD_DP32(data, CPUCFG2, LSX, 1), data = FIELD_DP32(data, CPUCFG2, LLFTP, 1); data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1); + data = FIELD_DP32(data, CPUCFG2, LSPW, 1); data = FIELD_DP32(data, CPUCFG2, LAM, 1); env->cpucfg[2] = data; From patchwork Thu Aug 10 12:41:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Song Gao X-Patchwork-Id: 1819837 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RM65Y55rTz1yf6 for ; Thu, 10 Aug 2023 22:42:41 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qU4yk-0001BG-EY; Thu, 10 Aug 2023 08:41:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qU4yi-00019I-Aj for qemu-devel@nongnu.org; Thu, 10 Aug 2023 08:41:24 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qU4ye-00044K-3H for qemu-devel@nongnu.org; Thu, 10 Aug 2023 08:41:24 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Dxfevq2tRkbqsUAA--.42245S3; Thu, 10 Aug 2023 20:41:14 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Ax3c7o2tRkoiNTAA--.11480S4; Thu, 10 Aug 2023 20:41:13 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, philmd@linaro.org, maobibo@loongson.cn, yangxiaojuan@loongson.cn Subject: [PATCH v1 2/6] target/loongarch: Add some checks before translating fpu instructions Date: Thu, 10 Aug 2023 20:41:08 +0800 Message-Id: <20230810124112.236640-3-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230810124112.236640-1-gaosong@loongson.cn> References: <20230810124112.236640-1-gaosong@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Ax3c7o2tRkoiNTAA--.11480S4 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds REQUIRE_FP/FP_SP/FP_DP to check CPUCFG2.FP/FP_SP/FP_DP. Signed-off-by: Song Gao --- target/loongarch/cpu.h | 6 + .../loongarch/insn_trans/trans_farith.c.inc | 132 ++++++++++++------ target/loongarch/insn_trans/trans_fcmp.c.inc | 4 + target/loongarch/insn_trans/trans_fcnv.c.inc | 56 ++++---- .../loongarch/insn_trans/trans_fmemory.c.inc | 104 ++++++++++---- target/loongarch/insn_trans/trans_fmov.c.inc | 47 +++++-- 6 files changed, 247 insertions(+), 102 deletions(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 9f550793ca..5594d83011 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -459,6 +459,9 @@ static inline void set_pc(CPULoongArchState *env, uint64_t value) #define HW_FLAGS_EUEN_FPE 0x04 #define HW_FLAGS_EUEN_SXE 0x08 #define HW_FLAGS_VA32 0x20 +#define HW_FLAGS_FP 0x40 +#define HW_FLAGS_FP_SP 0x80 +#define HW_FLAGS_FP_DP 0x100 static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) @@ -469,6 +472,9 @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE; *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE; *flags |= is_va32(env) * HW_FLAGS_VA32; + *flags |= FIELD_EX32(env->cpucfg[2], CPUCFG2, FP) * HW_FLAGS_FP; + *flags |= FIELD_EX32(env->cpucfg[2], CPUCFG2, FP_SP) * HW_FLAGS_FP_SP; + *flags |= FIELD_EX32(env->cpucfg[2], CPUCFG2, FP_DP) * HW_FLAGS_FP_DP; } void loongarch_cpu_list(void); diff --git a/target/loongarch/insn_trans/trans_farith.c.inc b/target/loongarch/insn_trans/trans_farith.c.inc index 21ea47308b..f8ff5b7bb6 100644 --- a/target/loongarch/insn_trans/trans_farith.c.inc +++ b/target/loongarch/insn_trans/trans_farith.c.inc @@ -10,17 +10,45 @@ return true; \ } \ } while (0) + +#define REQUIRE_FP do { \ + if ((ctx->base.tb->flags & HW_FLAGS_FP) == 0) { \ + return false; \ + } \ +} while (0) + +#define REQUIRE_FP_SP do { \ + if ((ctx->base.tb->flags & HW_FLAGS_FP_SP) == 0) { \ + return false; \ + } \ +} while (0) + +#define REQUIRE_FP_DP do { \ + if ((ctx->base.tb->flags & HW_FLAGS_FP_DP) == 0) { \ + return false; \ + } \ +} while (0) #else #define CHECK_FPE +#define REQUIRE_FP +#define REQUIRE_FP_SP +#define REQUIRE_FP_DP #endif -static bool gen_fff(DisasContext *ctx, arg_fff *a, +static bool gen_fff(DisasContext *ctx, arg_fff *a, int mode, void (*func)(TCGv, TCGv_env, TCGv, TCGv)) { TCGv dest = get_fpr(ctx, a->fd); TCGv src1 = get_fpr(ctx, a->fj); TCGv src2 = get_fpr(ctx, a->fk); + REQUIRE_FP; + if (mode == 0) { + REQUIRE_FP_SP; + } else { + REQUIRE_FP_DP; + } + CHECK_FPE; func(dest, cpu_env, src1, src2); @@ -29,12 +57,19 @@ static bool gen_fff(DisasContext *ctx, arg_fff *a, return true; } -static bool gen_ff(DisasContext *ctx, arg_ff *a, +static bool gen_ff(DisasContext *ctx, arg_ff *a, int mode, void (*func)(TCGv, TCGv_env, TCGv)) { TCGv dest = get_fpr(ctx, a->fd); TCGv src = get_fpr(ctx, a->fj); + REQUIRE_FP; + if (mode == 0) { + REQUIRE_FP_SP; + } else { + REQUIRE_FP_DP; + } + CHECK_FPE; func(dest, cpu_env, src); @@ -43,7 +78,7 @@ static bool gen_ff(DisasContext *ctx, arg_ff *a, return true; } -static bool gen_muladd(DisasContext *ctx, arg_ffff *a, +static bool gen_muladd(DisasContext *ctx, arg_ffff *a, int mode, void (*func)(TCGv, TCGv_env, TCGv, TCGv, TCGv, TCGv_i32), int flag) { @@ -53,6 +88,13 @@ static bool gen_muladd(DisasContext *ctx, arg_ffff *a, TCGv src2 = get_fpr(ctx, a->fk); TCGv src3 = get_fpr(ctx, a->fa); + REQUIRE_FP; + if (mode == 0) { + REQUIRE_FP_SP; + } else { + REQUIRE_FP_DP; + } + CHECK_FPE; func(dest, cpu_env, src1, src2, src3, tflag); @@ -67,6 +109,8 @@ static bool trans_fcopysign_s(DisasContext *ctx, arg_fcopysign_s *a) TCGv src1 = get_fpr(ctx, a->fk); TCGv src2 = get_fpr(ctx, a->fj); + REQUIRE_FP; + REQUIRE_FP_SP; CHECK_FPE; tcg_gen_deposit_i64(dest, src1, src2, 0, 31); @@ -81,6 +125,8 @@ static bool trans_fcopysign_d(DisasContext *ctx, arg_fcopysign_d *a) TCGv src1 = get_fpr(ctx, a->fk); TCGv src2 = get_fpr(ctx, a->fj); + REQUIRE_FP; + REQUIRE_FP_DP; CHECK_FPE; tcg_gen_deposit_i64(dest, src1, src2, 0, 63); @@ -94,6 +140,8 @@ static bool trans_fabs_s(DisasContext *ctx, arg_fabs_s *a) TCGv dest = get_fpr(ctx, a->fd); TCGv src = get_fpr(ctx, a->fj); + REQUIRE_FP; + REQUIRE_FP_SP; CHECK_FPE; tcg_gen_andi_i64(dest, src, MAKE_64BIT_MASK(0, 31)); @@ -108,6 +156,8 @@ static bool trans_fabs_d(DisasContext *ctx, arg_fabs_d *a) TCGv dest = get_fpr(ctx, a->fd); TCGv src = get_fpr(ctx, a->fj); + REQUIRE_FP; + REQUIRE_FP_DP; CHECK_FPE; tcg_gen_andi_i64(dest, src, MAKE_64BIT_MASK(0, 63)); @@ -121,6 +171,8 @@ static bool trans_fneg_s(DisasContext *ctx, arg_fneg_s *a) TCGv dest = get_fpr(ctx, a->fd); TCGv src = get_fpr(ctx, a->fj); + REQUIRE_FP; + REQUIRE_FP_SP; CHECK_FPE; tcg_gen_xori_i64(dest, src, 0x80000000); @@ -135,6 +187,8 @@ static bool trans_fneg_d(DisasContext *ctx, arg_fneg_d *a) TCGv dest = get_fpr(ctx, a->fd); TCGv src = get_fpr(ctx, a->fj); + REQUIRE_FP; + REQUIRE_FP_DP; CHECK_FPE; tcg_gen_xori_i64(dest, src, 0x8000000000000000LL); @@ -143,41 +197,41 @@ static bool trans_fneg_d(DisasContext *ctx, arg_fneg_d *a) return true; } -TRANS(fadd_s, gen_fff, gen_helper_fadd_s) -TRANS(fadd_d, gen_fff, gen_helper_fadd_d) -TRANS(fsub_s, gen_fff, gen_helper_fsub_s) -TRANS(fsub_d, gen_fff, gen_helper_fsub_d) -TRANS(fmul_s, gen_fff, gen_helper_fmul_s) -TRANS(fmul_d, gen_fff, gen_helper_fmul_d) -TRANS(fdiv_s, gen_fff, gen_helper_fdiv_s) -TRANS(fdiv_d, gen_fff, gen_helper_fdiv_d) -TRANS(fmax_s, gen_fff, gen_helper_fmax_s) -TRANS(fmax_d, gen_fff, gen_helper_fmax_d) -TRANS(fmin_s, gen_fff, gen_helper_fmin_s) -TRANS(fmin_d, gen_fff, gen_helper_fmin_d) -TRANS(fmaxa_s, gen_fff, gen_helper_fmaxa_s) -TRANS(fmaxa_d, gen_fff, gen_helper_fmaxa_d) -TRANS(fmina_s, gen_fff, gen_helper_fmina_s) -TRANS(fmina_d, gen_fff, gen_helper_fmina_d) -TRANS(fscaleb_s, gen_fff, gen_helper_fscaleb_s) -TRANS(fscaleb_d, gen_fff, gen_helper_fscaleb_d) -TRANS(fsqrt_s, gen_ff, gen_helper_fsqrt_s) -TRANS(fsqrt_d, gen_ff, gen_helper_fsqrt_d) -TRANS(frecip_s, gen_ff, gen_helper_frecip_s) -TRANS(frecip_d, gen_ff, gen_helper_frecip_d) -TRANS(frsqrt_s, gen_ff, gen_helper_frsqrt_s) -TRANS(frsqrt_d, gen_ff, gen_helper_frsqrt_d) -TRANS(flogb_s, gen_ff, gen_helper_flogb_s) -TRANS(flogb_d, gen_ff, gen_helper_flogb_d) -TRANS(fclass_s, gen_ff, gen_helper_fclass_s) -TRANS(fclass_d, gen_ff, gen_helper_fclass_d) -TRANS(fmadd_s, gen_muladd, gen_helper_fmuladd_s, 0) -TRANS(fmadd_d, gen_muladd, gen_helper_fmuladd_d, 0) -TRANS(fmsub_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_c) -TRANS(fmsub_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_c) -TRANS(fnmadd_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_result) -TRANS(fnmadd_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_result) -TRANS(fnmsub_s, gen_muladd, gen_helper_fmuladd_s, +TRANS(fadd_s, gen_fff, 0, gen_helper_fadd_s) +TRANS(fadd_d, gen_fff, 1, gen_helper_fadd_d) +TRANS(fsub_s, gen_fff, 0, gen_helper_fsub_s) +TRANS(fsub_d, gen_fff, 1, gen_helper_fsub_d) +TRANS(fmul_s, gen_fff, 0, gen_helper_fmul_s) +TRANS(fmul_d, gen_fff, 1, gen_helper_fmul_d) +TRANS(fdiv_s, gen_fff, 0, gen_helper_fdiv_s) +TRANS(fdiv_d, gen_fff, 1, gen_helper_fdiv_d) +TRANS(fmax_s, gen_fff, 0, gen_helper_fmax_s) +TRANS(fmax_d, gen_fff, 1, gen_helper_fmax_d) +TRANS(fmin_s, gen_fff, 0, gen_helper_fmin_s) +TRANS(fmin_d, gen_fff, 1, gen_helper_fmin_d) +TRANS(fmaxa_s, gen_fff, 0, gen_helper_fmaxa_s) +TRANS(fmaxa_d, gen_fff, 1, gen_helper_fmaxa_d) +TRANS(fmina_s, gen_fff, 0, gen_helper_fmina_s) +TRANS(fmina_d, gen_fff, 1, gen_helper_fmina_d) +TRANS(fscaleb_s, gen_fff, 0, gen_helper_fscaleb_s) +TRANS(fscaleb_d, gen_fff, 1, gen_helper_fscaleb_d) +TRANS(fsqrt_s, gen_ff, 0, gen_helper_fsqrt_s) +TRANS(fsqrt_d, gen_ff, 1, gen_helper_fsqrt_d) +TRANS(frecip_s, gen_ff, 0, gen_helper_frecip_s) +TRANS(frecip_d, gen_ff, 1, gen_helper_frecip_d) +TRANS(frsqrt_s, gen_ff, 0, gen_helper_frsqrt_s) +TRANS(frsqrt_d, gen_ff, 1, gen_helper_frsqrt_d) +TRANS(flogb_s, gen_ff, 0, gen_helper_flogb_s) +TRANS(flogb_d, gen_ff, 1, gen_helper_flogb_d) +TRANS(fclass_s, gen_ff, 0, gen_helper_fclass_s) +TRANS(fclass_d, gen_ff, 1, gen_helper_fclass_d) +TRANS(fmadd_s, gen_muladd, 0, gen_helper_fmuladd_s, 0) +TRANS(fmadd_d, gen_muladd, 1, gen_helper_fmuladd_d, 0) +TRANS(fmsub_s, gen_muladd, 0, gen_helper_fmuladd_s, float_muladd_negate_c) +TRANS(fmsub_d, gen_muladd, 1, gen_helper_fmuladd_d, float_muladd_negate_c) +TRANS(fnmadd_s, gen_muladd, 0, gen_helper_fmuladd_s, float_muladd_negate_result) +TRANS(fnmadd_d, gen_muladd, 1, gen_helper_fmuladd_d, float_muladd_negate_result) +TRANS(fnmsub_s, gen_muladd, 0, gen_helper_fmuladd_s, float_muladd_negate_c | float_muladd_negate_result) -TRANS(fnmsub_d, gen_muladd, gen_helper_fmuladd_d, +TRANS(fnmsub_d, gen_muladd, 1, gen_helper_fmuladd_d, float_muladd_negate_c | float_muladd_negate_result) diff --git a/target/loongarch/insn_trans/trans_fcmp.c.inc b/target/loongarch/insn_trans/trans_fcmp.c.inc index a78868dbc4..17ee28a1a2 100644 --- a/target/loongarch/insn_trans/trans_fcmp.c.inc +++ b/target/loongarch/insn_trans/trans_fcmp.c.inc @@ -29,6 +29,8 @@ static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a) uint32_t flags; void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32); + REQUIRE_FP; + REQUIRE_FP_SP; CHECK_FPE; var = tcg_temp_new(); @@ -49,6 +51,8 @@ static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp_cond_d *a) uint32_t flags; void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32); + REQUIRE_FP; + REQUIRE_FP_DP; CHECK_FPE; var = tcg_temp_new(); diff --git a/target/loongarch/insn_trans/trans_fcnv.c.inc b/target/loongarch/insn_trans/trans_fcnv.c.inc index c1c6918ad1..db33abcc32 100644 --- a/target/loongarch/insn_trans/trans_fcnv.c.inc +++ b/target/loongarch/insn_trans/trans_fcnv.c.inc @@ -3,31 +3,31 @@ * Copyright (c) 2021 Loongson Technology Corporation Limited */ -TRANS(fcvt_s_d, gen_ff, gen_helper_fcvt_s_d) -TRANS(fcvt_d_s, gen_ff, gen_helper_fcvt_d_s) -TRANS(ftintrm_w_s, gen_ff, gen_helper_ftintrm_w_s) -TRANS(ftintrm_w_d, gen_ff, gen_helper_ftintrm_w_d) -TRANS(ftintrm_l_s, gen_ff, gen_helper_ftintrm_l_s) -TRANS(ftintrm_l_d, gen_ff, gen_helper_ftintrm_l_d) -TRANS(ftintrp_w_s, gen_ff, gen_helper_ftintrp_w_s) -TRANS(ftintrp_w_d, gen_ff, gen_helper_ftintrp_w_d) -TRANS(ftintrp_l_s, gen_ff, gen_helper_ftintrp_l_s) -TRANS(ftintrp_l_d, gen_ff, gen_helper_ftintrp_l_d) -TRANS(ftintrz_w_s, gen_ff, gen_helper_ftintrz_w_s) -TRANS(ftintrz_w_d, gen_ff, gen_helper_ftintrz_w_d) -TRANS(ftintrz_l_s, gen_ff, gen_helper_ftintrz_l_s) -TRANS(ftintrz_l_d, gen_ff, gen_helper_ftintrz_l_d) -TRANS(ftintrne_w_s, gen_ff, gen_helper_ftintrne_w_s) -TRANS(ftintrne_w_d, gen_ff, gen_helper_ftintrne_w_d) -TRANS(ftintrne_l_s, gen_ff, gen_helper_ftintrne_l_s) -TRANS(ftintrne_l_d, gen_ff, gen_helper_ftintrne_l_d) -TRANS(ftint_w_s, gen_ff, gen_helper_ftint_w_s) -TRANS(ftint_w_d, gen_ff, gen_helper_ftint_w_d) -TRANS(ftint_l_s, gen_ff, gen_helper_ftint_l_s) -TRANS(ftint_l_d, gen_ff, gen_helper_ftint_l_d) -TRANS(ffint_s_w, gen_ff, gen_helper_ffint_s_w) -TRANS(ffint_s_l, gen_ff, gen_helper_ffint_s_l) -TRANS(ffint_d_w, gen_ff, gen_helper_ffint_d_w) -TRANS(ffint_d_l, gen_ff, gen_helper_ffint_d_l) -TRANS(frint_s, gen_ff, gen_helper_frint_s) -TRANS(frint_d, gen_ff, gen_helper_frint_d) +TRANS(fcvt_s_d, gen_ff, 0, gen_helper_fcvt_s_d) +TRANS(fcvt_d_s, gen_ff, 1, gen_helper_fcvt_d_s) +TRANS(ftintrm_w_s, gen_ff, 0, gen_helper_ftintrm_w_s) +TRANS(ftintrm_w_d, gen_ff, 1, gen_helper_ftintrm_w_d) +TRANS(ftintrm_l_s, gen_ff, 0, gen_helper_ftintrm_l_s) +TRANS(ftintrm_l_d, gen_ff, 1, gen_helper_ftintrm_l_d) +TRANS(ftintrp_w_s, gen_ff, 0, gen_helper_ftintrp_w_s) +TRANS(ftintrp_w_d, gen_ff, 1, gen_helper_ftintrp_w_d) +TRANS(ftintrp_l_s, gen_ff, 0, gen_helper_ftintrp_l_s) +TRANS(ftintrp_l_d, gen_ff, 1, gen_helper_ftintrp_l_d) +TRANS(ftintrz_w_s, gen_ff, 0, gen_helper_ftintrz_w_s) +TRANS(ftintrz_w_d, gen_ff, 1, gen_helper_ftintrz_w_d) +TRANS(ftintrz_l_s, gen_ff, 0, gen_helper_ftintrz_l_s) +TRANS(ftintrz_l_d, gen_ff, 1, gen_helper_ftintrz_l_d) +TRANS(ftintrne_w_s, gen_ff, 0, gen_helper_ftintrne_w_s) +TRANS(ftintrne_w_d, gen_ff, 1, gen_helper_ftintrne_w_d) +TRANS(ftintrne_l_s, gen_ff, 0, gen_helper_ftintrne_l_s) +TRANS(ftintrne_l_d, gen_ff, 1, gen_helper_ftintrne_l_d) +TRANS(ftint_w_s, gen_ff, 0, gen_helper_ftint_w_s) +TRANS(ftint_w_d, gen_ff, 1, gen_helper_ftint_w_d) +TRANS(ftint_l_s, gen_ff, 0, gen_helper_ftint_l_s) +TRANS(ftint_l_d, gen_ff, 1, gen_helper_ftint_l_d) +TRANS(ffint_s_w, gen_ff, 0, gen_helper_ffint_s_w) +TRANS(ffint_s_l, gen_ff, 1, gen_helper_ffint_s_l) +TRANS(ffint_d_w, gen_ff, 0, gen_helper_ffint_d_w) +TRANS(ffint_d_l, gen_ff, 1, gen_helper_ffint_d_l) +TRANS(frint_s, gen_ff, 0, gen_helper_frint_s) +TRANS(frint_d, gen_ff, 1, gen_helper_frint_d) diff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc b/target/loongarch/insn_trans/trans_fmemory.c.inc index bd3aba2c49..b8cf3f63b2 100644 --- a/target/loongarch/insn_trans/trans_fmemory.c.inc +++ b/target/loongarch/insn_trans/trans_fmemory.c.inc @@ -10,11 +10,18 @@ static void maybe_nanbox_load(TCGv freg, MemOp mop) } } -static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, MemOp mop) +static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, int mode, MemOp mop) { TCGv addr = gpr_src(ctx, a->rj, EXT_NONE); TCGv dest = get_fpr(ctx, a->fd); + REQUIRE_FP; + if (mode == 0) { + REQUIRE_FP_SP; + } else { + REQUIRE_FP_DP; + } + CHECK_FPE; addr = make_address_i(ctx, addr, a->imm); @@ -26,11 +33,18 @@ static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, MemOp mop) return true; } -static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a, MemOp mop) +static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a, int mode, MemOp mop) { TCGv addr = gpr_src(ctx, a->rj, EXT_NONE); TCGv src = get_fpr(ctx, a->fd); + REQUIRE_FP; + if (mode == 0) { + REQUIRE_FP_SP; + } else { + REQUIRE_FP_DP; + } + CHECK_FPE; addr = make_address_i(ctx, addr, a->imm); @@ -40,13 +54,20 @@ static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a, MemOp mop) return true; } -static bool gen_floadx(DisasContext *ctx, arg_frr *a, MemOp mop) +static bool gen_floadx(DisasContext *ctx, arg_frr *a, int mode, MemOp mop) { TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); TCGv dest = get_fpr(ctx, a->fd); TCGv addr; + REQUIRE_FP; + if (mode == 0) { + REQUIRE_FP_SP; + } else { + REQUIRE_FP_DP; + } + CHECK_FPE; addr = make_address_x(ctx, src1, src2); @@ -57,13 +78,20 @@ static bool gen_floadx(DisasContext *ctx, arg_frr *a, MemOp mop) return true; } -static bool gen_fstorex(DisasContext *ctx, arg_frr *a, MemOp mop) +static bool gen_fstorex(DisasContext *ctx, arg_frr *a, int mode, MemOp mop) { TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); TCGv src3 = get_fpr(ctx, a->fd); TCGv addr; + REQUIRE_FP; + if (mode == 0) { + REQUIRE_FP_SP; + } else { + REQUIRE_FP_DP; + } + CHECK_FPE; addr = make_address_x(ctx, src1, src2); @@ -72,13 +100,20 @@ static bool gen_fstorex(DisasContext *ctx, arg_frr *a, MemOp mop) return true; } -static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, MemOp mop) +static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, int mode, MemOp mop) { TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); TCGv dest = get_fpr(ctx, a->fd); TCGv addr; + REQUIRE_FP; + if (mode == 0) { + REQUIRE_FP_SP; + } else { + REQUIRE_FP_DP; + } + CHECK_FPE; gen_helper_asrtgt_d(cpu_env, src1, src2); @@ -90,13 +125,20 @@ static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, MemOp mop) return true; } -static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a, MemOp mop) +static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a, int mode, MemOp mop) { TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); TCGv src3 = get_fpr(ctx, a->fd); TCGv addr; + REQUIRE_FP; + if (mode == 0) { + REQUIRE_FP_SP; + } else { + REQUIRE_FP_DP; + } + CHECK_FPE; gen_helper_asrtgt_d(cpu_env, src1, src2); @@ -106,13 +148,20 @@ static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a, MemOp mop) return true; } -static bool gen_fload_le(DisasContext *ctx, arg_frr *a, MemOp mop) +static bool gen_fload_le(DisasContext *ctx, arg_frr *a, int mode, MemOp mop) { TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); TCGv dest = get_fpr(ctx, a->fd); TCGv addr; + REQUIRE_FP; + if (mode == 0) { + REQUIRE_FP_SP; + } else { + REQUIRE_FP_DP; + } + CHECK_FPE; gen_helper_asrtle_d(cpu_env, src1, src2); @@ -124,13 +173,20 @@ static bool gen_fload_le(DisasContext *ctx, arg_frr *a, MemOp mop) return true; } -static bool gen_fstore_le(DisasContext *ctx, arg_frr *a, MemOp mop) +static bool gen_fstore_le(DisasContext *ctx, arg_frr *a, int mode, MemOp mop) { TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); TCGv src3 = get_fpr(ctx, a->fd); TCGv addr; + REQUIRE_FP; + if (mode == 0) { + REQUIRE_FP_SP; + } else { + REQUIRE_FP_DP; + } + CHECK_FPE; gen_helper_asrtle_d(cpu_env, src1, src2); @@ -140,19 +196,19 @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a, MemOp mop) return true; } -TRANS(fld_s, gen_fload_i, MO_TEUL) -TRANS(fst_s, gen_fstore_i, MO_TEUL) -TRANS(fld_d, gen_fload_i, MO_TEUQ) -TRANS(fst_d, gen_fstore_i, MO_TEUQ) -TRANS(fldx_s, gen_floadx, MO_TEUL) -TRANS(fldx_d, gen_floadx, MO_TEUQ) -TRANS(fstx_s, gen_fstorex, MO_TEUL) -TRANS(fstx_d, gen_fstorex, MO_TEUQ) -TRANS(fldgt_s, gen_fload_gt, MO_TEUL) -TRANS(fldgt_d, gen_fload_gt, MO_TEUQ) -TRANS(fldle_s, gen_fload_le, MO_TEUL) -TRANS(fldle_d, gen_fload_le, MO_TEUQ) -TRANS(fstgt_s, gen_fstore_gt, MO_TEUL) -TRANS(fstgt_d, gen_fstore_gt, MO_TEUQ) -TRANS(fstle_s, gen_fstore_le, MO_TEUL) -TRANS(fstle_d, gen_fstore_le, MO_TEUQ) +TRANS(fld_s, gen_fload_i, 0, MO_TEUL) +TRANS(fst_s, gen_fstore_i, 0, MO_TEUL) +TRANS(fld_d, gen_fload_i, 1, MO_TEUQ) +TRANS(fst_d, gen_fstore_i, 1, MO_TEUQ) +TRANS(fldx_s, gen_floadx, 0, MO_TEUL) +TRANS(fldx_d, gen_floadx, 1, MO_TEUQ) +TRANS(fstx_s, gen_fstorex, 0, MO_TEUL) +TRANS(fstx_d, gen_fstorex, 1, MO_TEUQ) +TRANS(fldgt_s, gen_fload_gt, 0, MO_TEUL) +TRANS(fldgt_d, gen_fload_gt, 1, MO_TEUQ) +TRANS(fldle_s, gen_fload_le, 0, MO_TEUL) +TRANS(fldle_d, gen_fload_le, 1, MO_TEUQ) +TRANS(fstgt_s, gen_fstore_gt, 0, MO_TEUL) +TRANS(fstgt_d, gen_fstore_gt, 1, MO_TEUQ) +TRANS(fstle_s, gen_fstore_le, 0, MO_TEUL) +TRANS(fstle_d, gen_fstore_le, 1, MO_TEUQ) diff --git a/target/loongarch/insn_trans/trans_fmov.c.inc b/target/loongarch/insn_trans/trans_fmov.c.inc index c58c5c6534..09a7b5bc60 100644 --- a/target/loongarch/insn_trans/trans_fmov.c.inc +++ b/target/loongarch/insn_trans/trans_fmov.c.inc @@ -15,6 +15,7 @@ static bool trans_fsel(DisasContext *ctx, arg_fsel *a) TCGv src2 = get_fpr(ctx, a->fk); TCGv cond; + REQUIRE_FP; CHECK_FPE; cond = tcg_temp_new(); @@ -25,12 +26,20 @@ static bool trans_fsel(DisasContext *ctx, arg_fsel *a) return true; } -static bool gen_f2f(DisasContext *ctx, arg_ff *a, +static bool gen_f2f(DisasContext *ctx, arg_ff *a, int mode, void (*func)(TCGv, TCGv), bool nanbox) { TCGv dest = get_fpr(ctx, a->fd); TCGv src = get_fpr(ctx, a->fj); + + REQUIRE_FP; + if (mode == 0) { + REQUIRE_FP_SP; + } else { + REQUIRE_FP_DP; + } + CHECK_FPE; func(dest, src); @@ -42,12 +51,17 @@ static bool gen_f2f(DisasContext *ctx, arg_ff *a, return true; } -static bool gen_r2f(DisasContext *ctx, arg_fr *a, +static bool gen_r2f(DisasContext *ctx, arg_fr *a, int mode, void (*func)(TCGv, TCGv)) { TCGv src = gpr_src(ctx, a->rj, EXT_NONE); TCGv dest = get_fpr(ctx, a->fd); + REQUIRE_FP; + if (mode == 1) { + REQUIRE_FP_DP; + } + CHECK_FPE; func(dest, src); @@ -56,12 +70,17 @@ static bool gen_r2f(DisasContext *ctx, arg_fr *a, return true; } -static bool gen_f2r(DisasContext *ctx, arg_rf *a, +static bool gen_f2r(DisasContext *ctx, arg_rf *a, int mode, void (*func)(TCGv, TCGv)) { TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); TCGv src = get_fpr(ctx, a->fj); + REQUIRE_FP; + if (mode == 1) { + REQUIRE_FP_DP; + } + CHECK_FPE; func(dest, src); @@ -75,6 +94,7 @@ static bool trans_movgr2fcsr(DisasContext *ctx, arg_movgr2fcsr *a) uint32_t mask = fcsr_mask[a->fcsrd]; TCGv Rj = gpr_src(ctx, a->rj, EXT_NONE); + REQUIRE_FP; CHECK_FPE; if (mask == UINT32_MAX) { @@ -105,6 +125,7 @@ static bool trans_movfcsr2gr(DisasContext *ctx, arg_movfcsr2gr *a) { TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); + REQUIRE_FP; CHECK_FPE; tcg_gen_ld32u_i64(dest, cpu_env, offsetof(CPULoongArchState, fcsr0)); @@ -134,6 +155,7 @@ static bool trans_movfr2cf(DisasContext *ctx, arg_movfr2cf *a) TCGv t0; TCGv src = get_fpr(ctx, a->fj); + REQUIRE_FP; CHECK_FPE; t0 = tcg_temp_new(); @@ -147,6 +169,7 @@ static bool trans_movcf2fr(DisasContext *ctx, arg_movcf2fr *a) { TCGv dest = get_fpr(ctx, a->fd); + REQUIRE_FP; CHECK_FPE; tcg_gen_ld8u_tl(dest, cpu_env, @@ -160,6 +183,7 @@ static bool trans_movgr2cf(DisasContext *ctx, arg_movgr2cf *a) { TCGv t0; + REQUIRE_FP; CHECK_FPE; t0 = tcg_temp_new(); @@ -171,6 +195,7 @@ static bool trans_movgr2cf(DisasContext *ctx, arg_movgr2cf *a) static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a) { + REQUIRE_FP; CHECK_FPE; tcg_gen_ld8u_tl(gpr_dst(ctx, a->rd, EXT_NONE), cpu_env, @@ -178,11 +203,11 @@ static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a) return true; } -TRANS(fmov_s, gen_f2f, tcg_gen_mov_tl, true) -TRANS(fmov_d, gen_f2f, tcg_gen_mov_tl, false) -TRANS(movgr2fr_w, gen_r2f, gen_movgr2fr_w) -TRANS_64(movgr2fr_d, gen_r2f, tcg_gen_mov_tl) -TRANS(movgr2frh_w, gen_r2f, gen_movgr2frh_w) -TRANS(movfr2gr_s, gen_f2r, tcg_gen_ext32s_tl) -TRANS_64(movfr2gr_d, gen_f2r, tcg_gen_mov_tl) -TRANS(movfrh2gr_s, gen_f2r, gen_movfrh2gr_s) +TRANS(fmov_s, gen_f2f, 0, tcg_gen_mov_tl, true) +TRANS(fmov_d, gen_f2f, 1, tcg_gen_mov_tl, false) +TRANS(movgr2fr_w, gen_r2f, 0, gen_movgr2fr_w) +TRANS_64(movgr2fr_d, gen_r2f, 1, tcg_gen_mov_tl) +TRANS(movgr2frh_w, gen_r2f, 0, gen_movgr2frh_w) +TRANS(movfr2gr_s, gen_f2r, 0, tcg_gen_ext32s_tl) +TRANS_64(movfr2gr_d, gen_f2r, 1, tcg_gen_mov_tl) +TRANS(movfrh2gr_s, gen_f2r, 0, gen_movfrh2gr_s) From patchwork Thu Aug 10 12:41:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Song Gao X-Patchwork-Id: 1819838 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RM65f2W4gz1yf6 for ; Thu, 10 Aug 2023 22:42:46 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qU4yp-0001CZ-KJ; Thu, 10 Aug 2023 08:41:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qU4yh-00018j-Ic for qemu-devel@nongnu.org; Thu, 10 Aug 2023 08:41:23 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qU4yd-000448-Ve for qemu-devel@nongnu.org; Thu, 10 Aug 2023 08:41:23 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8CxLOvq2tRkcKsUAA--.39107S3; Thu, 10 Aug 2023 20:41:14 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Ax3c7o2tRkoiNTAA--.11480S5; Thu, 10 Aug 2023 20:41:14 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, philmd@linaro.org, maobibo@loongson.cn, yangxiaojuan@loongson.cn Subject: [PATCH v1 3/6] target/loongarch: Add REQUIRE_LSPW macro to check LSPW instructions Date: Thu, 10 Aug 2023 20:41:09 +0800 Message-Id: <20230810124112.236640-4-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230810124112.236640-1-gaosong@loongson.cn> References: <20230810124112.236640-1-gaosong@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Ax3c7o2tRkoiNTAA--.11480S5 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Song Gao --- target/loongarch/cpu.h | 2 ++ target/loongarch/insn_trans/trans_privileged.c.inc | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 5594d83011..13a4ab316a 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -462,6 +462,7 @@ static inline void set_pc(CPULoongArchState *env, uint64_t value) #define HW_FLAGS_FP 0x40 #define HW_FLAGS_FP_SP 0x80 #define HW_FLAGS_FP_DP 0x100 +#define HW_FLAGS_LSPW 0x200 static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) @@ -475,6 +476,7 @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, *flags |= FIELD_EX32(env->cpucfg[2], CPUCFG2, FP) * HW_FLAGS_FP; *flags |= FIELD_EX32(env->cpucfg[2], CPUCFG2, FP_SP) * HW_FLAGS_FP_SP; *flags |= FIELD_EX32(env->cpucfg[2], CPUCFG2, FP_DP) * HW_FLAGS_FP_DP; + *flags |= FIELD_EX32(env->cpucfg[2], CPUCFG2, LSPW) * HW_FLAGS_LSPW; } void loongarch_cpu_list(void); diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/loongarch/insn_trans/trans_privileged.c.inc index 9c9de090f0..210678dbb8 100644 --- a/target/loongarch/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/insn_trans/trans_privileged.c.inc @@ -432,11 +432,18 @@ static bool trans_cacop(DisasContext *ctx, arg_cacop *a) return true; } +#define REQUIRE_LSPW do { \ + if ((ctx->base.tb->flags & HW_FLAGS_LSPW) == 0) { \ + return false; \ + } \ +} while (0) + static bool trans_ldpte(DisasContext *ctx, arg_ldpte *a) { TCGv_i32 mem_idx = tcg_constant_i32(ctx->mem_idx); TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); + REQUIRE_LSPW; if (check_plv(ctx)) { return false; } @@ -450,6 +457,7 @@ static bool trans_lddir(DisasContext *ctx, arg_lddir *a) TCGv src = gpr_src(ctx, a->rj, EXT_NONE); TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); + REQUIRE_LSPW; if (check_plv(ctx)) { return false; } From patchwork Thu Aug 10 12:41:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Song Gao X-Patchwork-Id: 1819835 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RM65R55sRz1yfB for ; Thu, 10 Aug 2023 22:42:35 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qU4ym-0001Bz-VX; Thu, 10 Aug 2023 08:41:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qU4yh-00018i-EN for qemu-devel@nongnu.org; Thu, 10 Aug 2023 08:41:23 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qU4yd-00044F-AZ for qemu-devel@nongnu.org; Thu, 10 Aug 2023 08:41:22 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Dxfevr2tRkcqsUAA--.42246S3; Thu, 10 Aug 2023 20:41:15 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Ax3c7o2tRkoiNTAA--.11480S6; Thu, 10 Aug 2023 20:41:14 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, philmd@linaro.org, maobibo@loongson.cn, yangxiaojuan@loongson.cn Subject: [PATCH v1 4/6] target/loongarch: Add REQUIRE_LAM macro to check atomic instructions Date: Thu, 10 Aug 2023 20:41:10 +0800 Message-Id: <20230810124112.236640-5-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230810124112.236640-1-gaosong@loongson.cn> References: <20230810124112.236640-1-gaosong@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Ax3c7o2tRkoiNTAA--.11480S6 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Song Gao --- target/loongarch/cpu.h | 2 ++ target/loongarch/insn_trans/trans_atomic.c.inc | 12 ++++++++++++ 2 files changed, 14 insertions(+) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 13a4ab316a..0166ec3d7b 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -463,6 +463,7 @@ static inline void set_pc(CPULoongArchState *env, uint64_t value) #define HW_FLAGS_FP_SP 0x80 #define HW_FLAGS_FP_DP 0x100 #define HW_FLAGS_LSPW 0x200 +#define HW_FLAGS_LAM 0x400 static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) @@ -477,6 +478,7 @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, *flags |= FIELD_EX32(env->cpucfg[2], CPUCFG2, FP_SP) * HW_FLAGS_FP_SP; *flags |= FIELD_EX32(env->cpucfg[2], CPUCFG2, FP_DP) * HW_FLAGS_FP_DP; *flags |= FIELD_EX32(env->cpucfg[2], CPUCFG2, LSPW) * HW_FLAGS_LSPW; + *flags |= FIELD_EX32(env->cpucfg[2], CPUCFG2, LAM) * HW_FLAGS_LAM; } void loongarch_cpu_list(void); diff --git a/target/loongarch/insn_trans/trans_atomic.c.inc b/target/loongarch/insn_trans/trans_atomic.c.inc index d90312729b..c65d0da758 100644 --- a/target/loongarch/insn_trans/trans_atomic.c.inc +++ b/target/loongarch/insn_trans/trans_atomic.c.inc @@ -3,12 +3,20 @@ * Copyright (c) 2021 Loongson Technology Corporation Limited */ +#define REQUIRE_LAM do { \ + if ((ctx->base.tb->flags & HW_FLAGS_LAM) == 0) { \ + return false; \ + } \ +} while (0) + static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop) { TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); TCGv t0 = make_address_i(ctx, src1, a->imm); + REQUIRE_LAM; + tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, mop); tcg_gen_st_tl(t0, cpu_env, offsetof(CPULoongArchState, lladdr)); tcg_gen_st_tl(dest, cpu_env, offsetof(CPULoongArchState, llval)); @@ -25,6 +33,8 @@ static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop) TCGv t0 = tcg_temp_new(); TCGv val = tcg_temp_new(); + REQUIRE_LAM; + TCGLabel *l1 = gen_new_label(); TCGLabel *done = gen_new_label(); @@ -53,6 +63,8 @@ static bool gen_am(DisasContext *ctx, arg_rrr *a, TCGv addr = gpr_src(ctx, a->rj, EXT_NONE); TCGv val = gpr_src(ctx, a->rk, EXT_NONE); + REQUIRE_LAM; + if (a->rd != 0 && (a->rj == a->rd || a->rk == a->rd)) { qemu_log_mask(LOG_GUEST_ERROR, "Warning: source register overlaps destination register" From patchwork Thu Aug 10 12:41:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Song Gao X-Patchwork-Id: 1819839 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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Thu, 10 Aug 2023 20:41:15 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Ax3c7o2tRkoiNTAA--.11480S7; Thu, 10 Aug 2023 20:41:15 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, philmd@linaro.org, maobibo@loongson.cn, yangxiaojuan@loongson.cn Subject: [PATCH v1 5/6] target/loongarch: Add REQUIRE_LSX macro to check LSX instructions Date: Thu, 10 Aug 2023 20:41:11 +0800 Message-Id: <20230810124112.236640-6-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230810124112.236640-1-gaosong@loongson.cn> References: <20230810124112.236640-1-gaosong@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Ax3c7o2tRkoiNTAA--.11480S7 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Song Gao --- target/loongarch/cpu.h | 2 + target/loongarch/insn_trans/trans_lsx.c.inc | 71 ++++++++++++++++++++- 2 files changed, 72 insertions(+), 1 deletion(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 0166ec3d7b..19d2a28a47 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -464,6 +464,7 @@ static inline void set_pc(CPULoongArchState *env, uint64_t value) #define HW_FLAGS_FP_DP 0x100 #define HW_FLAGS_LSPW 0x200 #define HW_FLAGS_LAM 0x400 +#define HW_FLAGS_LSX 0x800 static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) @@ -479,6 +480,7 @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, *flags |= FIELD_EX32(env->cpucfg[2], CPUCFG2, FP_DP) * HW_FLAGS_FP_DP; *flags |= FIELD_EX32(env->cpucfg[2], CPUCFG2, LSPW) * HW_FLAGS_LSPW; *flags |= FIELD_EX32(env->cpucfg[2], CPUCFG2, LAM) * HW_FLAGS_LAM; + *flags |= FIELD_EX32(env->cpucfg[2], CPUCFG2, LSX) * HW_FLAGS_LSX; } void loongarch_cpu_list(void); diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch/insn_trans/trans_lsx.c.inc index 50153d6d0b..293f8c8c2a 100644 --- a/target/loongarch/insn_trans/trans_lsx.c.inc +++ b/target/loongarch/insn_trans/trans_lsx.c.inc @@ -15,6 +15,13 @@ #define CHECK_SXE #endif +#define REQUIRE_LSX do { \ + if ((ctx->base.tb->flags & HW_FLAGS_LSX) == 0) { \ + return false; \ + } \ +} while (0) + + static bool gen_vvvv(DisasContext *ctx, arg_vvvv *a, void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32)) @@ -24,6 +31,7 @@ static bool gen_vvvv(DisasContext *ctx, arg_vvvv *a, TCGv_i32 vk = tcg_constant_i32(a->vk); TCGv_i32 va = tcg_constant_i32(a->va); + REQUIRE_LSX; CHECK_SXE; func(cpu_env, vd, vj, vk, va); return true; @@ -36,6 +44,7 @@ static bool gen_vvv(DisasContext *ctx, arg_vvv *a, TCGv_i32 vj = tcg_constant_i32(a->vj); TCGv_i32 vk = tcg_constant_i32(a->vk); + REQUIRE_LSX; CHECK_SXE; func(cpu_env, vd, vj, vk); @@ -48,6 +57,7 @@ static bool gen_vv(DisasContext *ctx, arg_vv *a, TCGv_i32 vd = tcg_constant_i32(a->vd); TCGv_i32 vj = tcg_constant_i32(a->vj); + REQUIRE_LSX; CHECK_SXE; func(cpu_env, vd, vj); return true; @@ -60,6 +70,7 @@ static bool gen_vv_i(DisasContext *ctx, arg_vv_i *a, TCGv_i32 vj = tcg_constant_i32(a->vj); TCGv_i32 imm = tcg_constant_i32(a->imm); + REQUIRE_LSX; CHECK_SXE; func(cpu_env, vd, vj, imm); return true; @@ -71,6 +82,7 @@ static bool gen_cv(DisasContext *ctx, arg_cv *a, TCGv_i32 vj = tcg_constant_i32(a->vj); TCGv_i32 cd = tcg_constant_i32(a->cd); + REQUIRE_LSX; CHECK_SXE; func(cpu_env, cd, vj); return true; @@ -82,6 +94,7 @@ static bool gvec_vvv(DisasContext *ctx, arg_vvv *a, MemOp mop, { uint32_t vd_ofs, vj_ofs, vk_ofs; + REQUIRE_LSX; CHECK_SXE; vd_ofs = vec_full_offset(a->vd); @@ -98,6 +111,7 @@ static bool gvec_vv(DisasContext *ctx, arg_vv *a, MemOp mop, { uint32_t vd_ofs, vj_ofs; + REQUIRE_LSX; CHECK_SXE; vd_ofs = vec_full_offset(a->vd); @@ -113,6 +127,7 @@ static bool gvec_vv_i(DisasContext *ctx, arg_vv_i *a, MemOp mop, { uint32_t vd_ofs, vj_ofs; + REQUIRE_LSX; CHECK_SXE; vd_ofs = vec_full_offset(a->vd); @@ -126,6 +141,7 @@ static bool gvec_subi(DisasContext *ctx, arg_vv_i *a, MemOp mop) { uint32_t vd_ofs, vj_ofs; + REQUIRE_LSX; CHECK_SXE; vd_ofs = vec_full_offset(a->vd); @@ -145,6 +161,7 @@ static bool trans_v## NAME ##_q(DisasContext *ctx, arg_vvv *a) \ { \ TCGv_i64 rh, rl, ah, al, bh, bl; \ \ + REQUIRE_LSX; \ CHECK_SXE; \ \ rh = tcg_temp_new_i64(); \ @@ -3032,6 +3049,8 @@ static bool trans_vldi(DisasContext *ctx, arg_vldi *a) { int sel, vece; uint64_t value; + + REQUIRE_LSX; CHECK_SXE; sel = (a->imm >> 12) & 0x1; @@ -3058,6 +3077,7 @@ static bool trans_vandn_v(DisasContext *ctx, arg_vvv *a) { uint32_t vd_ofs, vj_ofs, vk_ofs; + REQUIRE_LSX; CHECK_SXE; vd_ofs = vec_full_offset(a->vd); @@ -3685,6 +3705,7 @@ static bool do_cmp(DisasContext *ctx, arg_vvv *a, MemOp mop, TCGCond cond) { uint32_t vd_ofs, vj_ofs, vk_ofs; + REQUIRE_LSX; CHECK_SXE; vd_ofs = vec_full_offset(a->vd); @@ -3731,6 +3752,7 @@ static bool do_## NAME ##_s(DisasContext *ctx, arg_vv_i *a, MemOp mop) \ { \ uint32_t vd_ofs, vj_ofs; \ \ + REQUIRE_LSX; \ CHECK_SXE; \ \ static const TCGOpcode vecop_list[] = { \ @@ -3780,6 +3802,7 @@ static bool do_## NAME ##_u(DisasContext *ctx, arg_vv_i *a, MemOp mop) \ { \ uint32_t vd_ofs, vj_ofs; \ \ + REQUIRE_LSX; \ CHECK_SXE; \ \ static const TCGOpcode vecop_list[] = { \ @@ -3874,6 +3897,7 @@ static bool trans_vfcmp_cond_s(DisasContext *ctx, arg_vvv_fcond *a) TCGv_i32 vj = tcg_constant_i32(a->vj); TCGv_i32 vk = tcg_constant_i32(a->vk); + REQUIRE_LSX; CHECK_SXE; fn = (a->fcond & 1 ? gen_helper_vfcmp_s_s : gen_helper_vfcmp_c_s); @@ -3900,6 +3924,7 @@ static bool trans_vfcmp_cond_d(DisasContext *ctx, arg_vvv_fcond *a) static bool trans_vbitsel_v(DisasContext *ctx, arg_vvvv *a) { + REQUIRE_LSX; CHECK_SXE; tcg_gen_gvec_bitsel(MO_64, vec_full_offset(a->vd), vec_full_offset(a->va), @@ -3922,6 +3947,7 @@ static bool trans_vbitseli_b(DisasContext *ctx, arg_vv_i *a) .load_dest = true }; + REQUIRE_LSX; CHECK_SXE; tcg_gen_gvec_2i(vec_full_offset(a->vd), vec_full_offset(a->vj), @@ -3941,6 +3967,7 @@ static bool trans_## NAME (DisasContext *ctx, arg_cv *a) \ get_vreg64(ah, a->vj, 1); \ get_vreg64(al, a->vj, 0); \ \ + REQUIRE_LSX; \ CHECK_SXE; \ tcg_gen_or_i64(t1, al, ah); \ tcg_gen_setcondi_i64(COND, t1, t1, 0); \ @@ -3964,6 +3991,8 @@ TRANS(vsetallnez_d, gen_cv, gen_helper_vsetallnez_d) static bool trans_vinsgr2vr_b(DisasContext *ctx, arg_vr_i *a) { TCGv src = gpr_src(ctx, a->rj, EXT_NONE); + + REQUIRE_LSX; CHECK_SXE; tcg_gen_st8_i64(src, cpu_env, offsetof(CPULoongArchState, fpr[a->vd].vreg.B(a->imm))); @@ -3973,6 +4002,8 @@ static bool trans_vinsgr2vr_b(DisasContext *ctx, arg_vr_i *a) static bool trans_vinsgr2vr_h(DisasContext *ctx, arg_vr_i *a) { TCGv src = gpr_src(ctx, a->rj, EXT_NONE); + + REQUIRE_LSX; CHECK_SXE; tcg_gen_st16_i64(src, cpu_env, offsetof(CPULoongArchState, fpr[a->vd].vreg.H(a->imm))); @@ -3982,6 +4013,8 @@ static bool trans_vinsgr2vr_h(DisasContext *ctx, arg_vr_i *a) static bool trans_vinsgr2vr_w(DisasContext *ctx, arg_vr_i *a) { TCGv src = gpr_src(ctx, a->rj, EXT_NONE); + + REQUIRE_LSX; CHECK_SXE; tcg_gen_st32_i64(src, cpu_env, offsetof(CPULoongArchState, fpr[a->vd].vreg.W(a->imm))); @@ -3991,6 +4024,8 @@ static bool trans_vinsgr2vr_w(DisasContext *ctx, arg_vr_i *a) static bool trans_vinsgr2vr_d(DisasContext *ctx, arg_vr_i *a) { TCGv src = gpr_src(ctx, a->rj, EXT_NONE); + + REQUIRE_LSX; CHECK_SXE; tcg_gen_st_i64(src, cpu_env, offsetof(CPULoongArchState, fpr[a->vd].vreg.D(a->imm))); @@ -4000,6 +4035,8 @@ static bool trans_vinsgr2vr_d(DisasContext *ctx, arg_vr_i *a) static bool trans_vpickve2gr_b(DisasContext *ctx, arg_rv_i *a) { TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); + + REQUIRE_LSX; CHECK_SXE; tcg_gen_ld8s_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm))); @@ -4009,6 +4046,8 @@ static bool trans_vpickve2gr_b(DisasContext *ctx, arg_rv_i *a) static bool trans_vpickve2gr_h(DisasContext *ctx, arg_rv_i *a) { TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); + + REQUIRE_LSX; CHECK_SXE; tcg_gen_ld16s_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm))); @@ -4018,6 +4057,8 @@ static bool trans_vpickve2gr_h(DisasContext *ctx, arg_rv_i *a) static bool trans_vpickve2gr_w(DisasContext *ctx, arg_rv_i *a) { TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); + + REQUIRE_LSX; CHECK_SXE; tcg_gen_ld32s_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm))); @@ -4027,6 +4068,8 @@ static bool trans_vpickve2gr_w(DisasContext *ctx, arg_rv_i *a) static bool trans_vpickve2gr_d(DisasContext *ctx, arg_rv_i *a) { TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); + + REQUIRE_LSX; CHECK_SXE; tcg_gen_ld_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm))); @@ -4036,6 +4079,8 @@ static bool trans_vpickve2gr_d(DisasContext *ctx, arg_rv_i *a) static bool trans_vpickve2gr_bu(DisasContext *ctx, arg_rv_i *a) { TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); + + REQUIRE_LSX; CHECK_SXE; tcg_gen_ld8u_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm))); @@ -4045,6 +4090,8 @@ static bool trans_vpickve2gr_bu(DisasContext *ctx, arg_rv_i *a) static bool trans_vpickve2gr_hu(DisasContext *ctx, arg_rv_i *a) { TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); + + REQUIRE_LSX; CHECK_SXE; tcg_gen_ld16u_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm))); @@ -4054,6 +4101,8 @@ static bool trans_vpickve2gr_hu(DisasContext *ctx, arg_rv_i *a) static bool trans_vpickve2gr_wu(DisasContext *ctx, arg_rv_i *a) { TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); + + REQUIRE_LSX; CHECK_SXE; tcg_gen_ld32u_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm))); @@ -4063,6 +4112,8 @@ static bool trans_vpickve2gr_wu(DisasContext *ctx, arg_rv_i *a) static bool trans_vpickve2gr_du(DisasContext *ctx, arg_rv_i *a) { TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); + + REQUIRE_LSX; CHECK_SXE; tcg_gen_ld_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm))); @@ -4072,8 +4123,9 @@ static bool trans_vpickve2gr_du(DisasContext *ctx, arg_rv_i *a) static bool gvec_dup(DisasContext *ctx, arg_vr *a, MemOp mop) { TCGv src = gpr_src(ctx, a->rj, EXT_NONE); - CHECK_SXE; + REQUIRE_LSX; + CHECK_SXE; tcg_gen_gvec_dup_i64(mop, vec_full_offset(a->vd), 16, ctx->vl/8, src); return true; @@ -4086,7 +4138,9 @@ TRANS(vreplgr2vr_d, gvec_dup, MO_64) static bool trans_vreplvei_b(DisasContext *ctx, arg_vv_i *a) { + REQUIRE_LSX; CHECK_SXE; + tcg_gen_gvec_dup_mem(MO_8,vec_full_offset(a->vd), offsetof(CPULoongArchState, fpr[a->vj].vreg.B((a->imm))), @@ -4096,7 +4150,9 @@ static bool trans_vreplvei_b(DisasContext *ctx, arg_vv_i *a) static bool trans_vreplvei_h(DisasContext *ctx, arg_vv_i *a) { + REQUIRE_LSX; CHECK_SXE; + tcg_gen_gvec_dup_mem(MO_16, vec_full_offset(a->vd), offsetof(CPULoongArchState, fpr[a->vj].vreg.H((a->imm))), @@ -4105,7 +4161,9 @@ static bool trans_vreplvei_h(DisasContext *ctx, arg_vv_i *a) } static bool trans_vreplvei_w(DisasContext *ctx, arg_vv_i *a) { + REQUIRE_LSX; CHECK_SXE; + tcg_gen_gvec_dup_mem(MO_32, vec_full_offset(a->vd), offsetof(CPULoongArchState, fpr[a->vj].vreg.W((a->imm))), @@ -4114,7 +4172,9 @@ static bool trans_vreplvei_w(DisasContext *ctx, arg_vv_i *a) } static bool trans_vreplvei_d(DisasContext *ctx, arg_vv_i *a) { + REQUIRE_LSX; CHECK_SXE; + tcg_gen_gvec_dup_mem(MO_64, vec_full_offset(a->vd), offsetof(CPULoongArchState, fpr[a->vj].vreg.D((a->imm))), @@ -4129,6 +4189,7 @@ static bool gen_vreplve(DisasContext *ctx, arg_vvr *a, int vece, int bit, TCGv_ptr t1 = tcg_temp_new_ptr(); TCGv_i64 t2 = tcg_temp_new_i64(); + REQUIRE_LSX; CHECK_SXE; tcg_gen_andi_i64(t0, gpr_src(ctx, a->rk, EXT_NONE), (LSX_LEN/bit) -1); @@ -4155,6 +4216,7 @@ static bool trans_vbsll_v(DisasContext *ctx, arg_vv_i *a) int ofs; TCGv_i64 desthigh, destlow, high, low; + REQUIRE_LSX; CHECK_SXE; desthigh = tcg_temp_new_i64(); @@ -4185,6 +4247,7 @@ static bool trans_vbsrl_v(DisasContext *ctx, arg_vv_i *a) TCGv_i64 desthigh, destlow, high, low; int ofs; + REQUIRE_LSX; CHECK_SXE; desthigh = tcg_temp_new_i64(); @@ -4259,6 +4322,7 @@ static bool trans_vld(DisasContext *ctx, arg_vr_i *a) TCGv_i64 rl, rh; TCGv_i128 val; + REQUIRE_LSX; CHECK_SXE; addr = gpr_src(ctx, a->rj, EXT_NONE); @@ -4282,6 +4346,7 @@ static bool trans_vst(DisasContext *ctx, arg_vr_i *a) TCGv_i128 val; TCGv_i64 ah, al; + REQUIRE_LSX; CHECK_SXE; addr = gpr_src(ctx, a->rj, EXT_NONE); @@ -4305,6 +4370,7 @@ static bool trans_vldx(DisasContext *ctx, arg_vrr *a) TCGv_i64 rl, rh; TCGv_i128 val; + REQUIRE_LSX; CHECK_SXE; src1 = gpr_src(ctx, a->rj, EXT_NONE); @@ -4328,6 +4394,7 @@ static bool trans_vstx(DisasContext *ctx, arg_vrr *a) TCGv_i64 ah, al; TCGv_i128 val; + REQUIRE_LSX; CHECK_SXE; src1 = gpr_src(ctx, a->rj, EXT_NONE); @@ -4351,6 +4418,7 @@ static bool trans_## NAME (DisasContext *ctx, arg_vr_i *a) \ TCGv addr; \ TCGv_i64 val; \ \ + REQUIRE_LSX; \ CHECK_SXE; \ \ addr = gpr_src(ctx, a->rj, EXT_NONE); \ @@ -4375,6 +4443,7 @@ static bool trans_## NAME (DisasContext *ctx, arg_vr_ii *a) \ TCGv addr; \ TCGv_i64 val; \ \ + REQUIRE_LSX; \ CHECK_SXE; \ \ addr = gpr_src(ctx, a->rj, EXT_NONE); \ From patchwork Thu Aug 10 12:41:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Song Gao X-Patchwork-Id: 1819833 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Thu, 10 Aug 2023 08:41:24 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Dxg_Ds2tRkd6sUAA--.44860S3; Thu, 10 Aug 2023 20:41:16 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Ax3c7o2tRkoiNTAA--.11480S8; Thu, 10 Aug 2023 20:41:15 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, philmd@linaro.org, maobibo@loongson.cn, yangxiaojuan@loongson.cn Subject: [PATCH v1 6/6] target/loongarch: Add REQUIRE_IOCSR macro to check IOCSR instructions Date: Thu, 10 Aug 2023 20:41:12 +0800 Message-Id: <20230810124112.236640-7-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230810124112.236640-1-gaosong@loongson.cn> References: <20230810124112.236640-1-gaosong@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Ax3c7o2tRkoiNTAA--.11480S8 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Song Gao --- target/loongarch/cpu.h | 2 ++ target/loongarch/insn_trans/trans_privileged.c.inc | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 19d2a28a47..69a3ab16ee 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -465,6 +465,7 @@ static inline void set_pc(CPULoongArchState *env, uint64_t value) #define HW_FLAGS_LSPW 0x200 #define HW_FLAGS_LAM 0x400 #define HW_FLAGS_LSX 0x800 +#define HW_FLAGS_IOCSR 0x2000 static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) @@ -481,6 +482,7 @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, *flags |= FIELD_EX32(env->cpucfg[2], CPUCFG2, LSPW) * HW_FLAGS_LSPW; *flags |= FIELD_EX32(env->cpucfg[2], CPUCFG2, LAM) * HW_FLAGS_LAM; *flags |= FIELD_EX32(env->cpucfg[2], CPUCFG2, LSX) * HW_FLAGS_LSX; + *flags |= FIELD_EX32(env->cpucfg[1], CPUCFG1, IOCSR) * HW_FLAGS_IOCSR; } void loongarch_cpu_list(void); diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/loongarch/insn_trans/trans_privileged.c.inc index 210678dbb8..78badf4bbb 100644 --- a/target/loongarch/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/insn_trans/trans_privileged.c.inc @@ -286,12 +286,19 @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxchg *a) return true; } +#define REQUIRE_IOCSR do { \ + if ((ctx->base.tb->flags & HW_FLAGS_IOCSR) == 0) { \ + return false; \ + } \ +} while (0) + static bool gen_iocsrrd(DisasContext *ctx, arg_rr *a, void (*func)(TCGv, TCGv_ptr, TCGv)) { TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); + REQUIRE_IOCSR; if (check_plv(ctx)) { return false; } @@ -305,6 +312,7 @@ static bool gen_iocsrwr(DisasContext *ctx, arg_rr *a, TCGv val = gpr_src(ctx, a->rd, EXT_NONE); TCGv addr = gpr_src(ctx, a->rj, EXT_NONE); + REQUIRE_IOCSR; if (check_plv(ctx)) { return false; }