From patchwork Tue Aug 8 03:11:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1818409 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=m8H0z09X; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RKdXn6L2Yz1yYC for ; Tue, 8 Aug 2023 13:12:41 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qTD8C-0008Dw-6J; Mon, 07 Aug 2023 23:11:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qTD89-0008DQ-A4; Mon, 07 Aug 2023 23:11:33 -0400 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qTD87-0008Uo-QV; Mon, 07 Aug 2023 23:11:33 -0400 Received: by mail-pg1-x531.google.com with SMTP id 41be03b00d2f7-564cd28d48dso1759033a12.0; Mon, 07 Aug 2023 20:11:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1691464290; x=1692069090; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HHTYl0Q8/otY2A0K5afGJk1HMia3iXDDoE/2IoDVxBA=; b=m8H0z09XupGdQcf7dtTrGA4udh9frVLuCMK703pvWTvpDt9lzSdq8N/kvKRWX1SfYm cLV2/ZnoBGTaQ2lFtn+/YE1m3lRSRTdGCQAlO/Dc4rFQh49S/m/MH5MFBhJuX9GGeb24 cINzOT0gIQIe8jGFQNXoixrZQo4LF0v0xqc2GaOyf+csczk0fmlmSnSwpixrXhzsz/tE ApomNwdoMNRqISu+PrHmPxZ7d+fWXzmvYJxQjNFL0k238ii1D5s4cMs/TDBgjP91xRjh 4joVEwM8ri1TLLfPiQulPGNxGi1Y58k7zpmEu/hIStsF7yXf4j5XELSq8yfu0ZqhM2tt 62qQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691464290; x=1692069090; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HHTYl0Q8/otY2A0K5afGJk1HMia3iXDDoE/2IoDVxBA=; b=Fjdkpm92h2qvgfggL7wNaHylvYXzVstehp6LQkm0mOAQrJsUvLwYOieBi2tboszouE p61h/ZsumHvyzdFvpqmIhuOQnJyLI5aLd2lwLnWOYCez4XbKJU8w+RfSrzviVaktX6NF l1VyrZJIDTGSfiqk0dFuWKG3b/+QmlwdwAdbroUDoCgLSzY2oZ6vb5g57ZZG2hYzrf04 suZXxeFY6r3A+0uM09+ABIe37hB3VpbY5+I4pktrtdaLZVzr9Gm/wuv9QZ5MbOfPKic8 kI0kxXCcOwmTBBBAYcy+l4+0eURZVkkyv9oxBhWykyQ8mlis69KzdLoWqPgLKybyHw56 xGuA== X-Gm-Message-State: AOJu0Yworng+Jtxv6H274X+/dJc9XX35wKetX/93aXa4P5KxIIjDZxyK pNW3ab6I2I9IX5y56QGNHRQ= X-Google-Smtp-Source: AGHT+IGY+J2Zzp989rztIaWGkP2Y+KYYOgip7Ua95B1HFzheg8nM68kDFxgtLnEVRzWz+PMbRrpjdQ== X-Received: by 2002:a05:6a20:9151:b0:134:37bb:89be with SMTP id x17-20020a056a20915100b0013437bb89bemr10415613pzc.57.1691464289977; Mon, 07 Aug 2023 20:11:29 -0700 (PDT) Received: from wheely.local0.net (61-68-137-140.tpgi.com.au. [61.68.137.140]) by smtp.gmail.com with ESMTPSA id i21-20020aa79095000000b00687ce7c6540sm482642pfa.99.2023.08.07.20.11.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:29 -0700 (PDT) From: Nicholas Piggin To: Daniel Henrique Barboza Cc: Nicholas Piggin , =?utf-8?q?C=C3=A9dric_Le_Goater?= , David Gibson , Greg Kurz , Harsh Prateek Bora , Shivaprasad G Bhat , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/6] target/ppc: Remove single-step suppression inside 0x100-0xf00 Date: Tue, 8 Aug 2023 13:11:11 +1000 Message-Id: <20230808031116.398205-2-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230808031116.398205-1-npiggin@gmail.com> References: <20230808031116.398205-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=npiggin@gmail.com; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Single-step interrputs are suppressed if the nip is between 0x100 and 0xf00. This has been the case for a long time and it's not clear what the intention is. Likely either an attempt to suppress trace interrupts for instructions that cause an interrupt on completion, or a workaround to prevent software tripping over itself single stepping its interrupt handlers. BookE interrupt vectors are set by IVOR registers, and BookS has AIL modes and new interrupt types, so there are many interrupts including the debug interrupt which can be outside this range. So any effect it might have had does not cover most cases (including Linux on recent BookS CPUs). Remove this special case. Signed-off-by: Nicholas Piggin --- target/ppc/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 74796ec7ba..06530dd782 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7410,8 +7410,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) } /* Honor single stepping. */ - if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) - && (nip <= 0x100 || nip > 0xf00)) { + if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)) { switch (is_jmp) { case DISAS_TOO_MANY: case DISAS_EXIT_UPDATE: From patchwork Tue Aug 8 03:11:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1818426 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=KybHgjr9; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RKdZW1nxSz1yYC for ; Tue, 8 Aug 2023 13:14:11 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qTD8J-0008KA-5H; Mon, 07 Aug 2023 23:11:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qTD8F-0008F3-5i; Mon, 07 Aug 2023 23:11:39 -0400 Received: from mail-oo1-xc36.google.com ([2607:f8b0:4864:20::c36]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qTD8D-0008VN-08; Mon, 07 Aug 2023 23:11:38 -0400 Received: by mail-oo1-xc36.google.com with SMTP id 006d021491bc7-56d455462c2so2573860eaf.2; Mon, 07 Aug 2023 20:11:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1691464294; x=1692069094; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5/ZvPprF7EhR5iTohUEXU14+rKjINMUPIVmqhU8o4NA=; b=KybHgjr9YY0nmjrsqlXrNYSNhubjDJcjLeWkok2kNHVGXtq6SiG0Ld8SVXvJWSSzNR JoGEY627Qm7DXhVCt7KSV9JgG7v1lC6dYm0VFv7LwY2U25pSFjUpZGQuVwQaMB1i5s+C ywbb5MHT0yXx3nRfjGadsHmo8cRezeO2c9PgA3t3+0F/V0pEcGEEifIGLw4ohyxw71oI OmNfIXaKiX22VyLqJrQxRQzEpUsvklfjN1X+dqkNlE3Tx45zR4tJxIwyEmheMnuw9W2+ IbNMqOMR3Zutc//QICHY9mkegEek65enpRSSw+au6O5Gg4ogbu/Q80zoFEgeHG/6yXje Xf/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691464294; x=1692069094; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5/ZvPprF7EhR5iTohUEXU14+rKjINMUPIVmqhU8o4NA=; b=GfEenxDIJU+z1vGldEAYSXBpp8Un7H211e7bNDE7AwatcSYlBWp2u+Xc+Y+yclq0pt K61NCuzIM39WaSkE6GG2Tp9qxOO0vrvpfNiN3TnHyy50Su8C+ESvNCS1sO9z33fvHa1c nXeI01Ff+h10OUFgpXXB+C8PujEz0Lpeb3LlGUyvUDp7Wm5RQuq4eXNPDg5DrAh5T0Hq 86fNxa+xjDdVBrZdLNEJHokOcP3Zzt/6Rc8bf4Tug4su3qCwYZkLP+7UXUUqggC+sFNb 9ZSzr3+yRV9+jj/lMoztdgAjLHbVosGojXqFvu4H7GZP6D0b2/ePZdRQxcFFvLoFbVVi uvEA== X-Gm-Message-State: AOJu0YxPGLXME8+OgwJiyZ8jkIbsWxvYQJosW7k2XBGqPAGvLl1tEI0w pOtJQtOV0Y97cN0Pe7EQPIs= X-Google-Smtp-Source: AGHT+IHFe4W/qhAWBKmQlJs5xTxZTlp+6fepkC2aKR3kdmcbbUXgL/OHVtmrznyid32bGD6NjZeupA== X-Received: by 2002:a05:6808:213:b0:3a7:56a1:9bbe with SMTP id l19-20020a056808021300b003a756a19bbemr10872463oie.45.1691464294384; Mon, 07 Aug 2023 20:11:34 -0700 (PDT) Received: from wheely.local0.net (61-68-137-140.tpgi.com.au. [61.68.137.140]) by smtp.gmail.com with ESMTPSA id i21-20020aa79095000000b00687ce7c6540sm482642pfa.99.2023.08.07.20.11.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:34 -0700 (PDT) From: Nicholas Piggin To: Daniel Henrique Barboza Cc: Nicholas Piggin , =?utf-8?q?C=C3=A9dric_Le_Goater?= , David Gibson , Greg Kurz , Harsh Prateek Bora , Shivaprasad G Bhat , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/6] target/ppc: Improve book3s branch trace interrupt for v2.07S Date: Tue, 8 Aug 2023 13:11:12 +1000 Message-Id: <20230808031116.398205-3-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230808031116.398205-1-npiggin@gmail.com> References: <20230808031116.398205-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c36; envelope-from=npiggin@gmail.com; helo=mail-oo1-xc36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Improve the emulation accuracy of the single step and branch trace interrupts for v2.07S. Set SRR1[33]=1, and set SIAR to completed instruction address. Signed-off-by: Nicholas Piggin --- target/ppc/excp_helper.c | 16 +++++++++++++++- target/ppc/helper.h | 1 + target/ppc/translate.c | 21 +++++++++++---------- 3 files changed, 27 insertions(+), 11 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 9aa8e46566..2d6aef5e66 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1571,9 +1571,11 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp) } } break; + case POWERPC_EXCP_TRACE: /* Trace exception */ + msr |= env->error_code; + /* fall through */ case POWERPC_EXCP_DSEG: /* Data segment exception */ case POWERPC_EXCP_ISEG: /* Instruction segment exception */ - case POWERPC_EXCP_TRACE: /* Trace exception */ case POWERPC_EXCP_SDOOR: /* Doorbell interrupt */ case POWERPC_EXCP_PERFM: /* Performance monitor interrupt */ break; @@ -3168,6 +3170,18 @@ void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb) } #endif /* TARGET_PPC64 */ +/* Single-step tracing */ +void helper_book3s_trace(CPUPPCState *env, target_ulong prev_ip) +{ + uint32_t error_code = 0; + if (env->insns_flags2 & PPC2_ISA207S) { + /* Load/store reporting, SRR1[35, 36] and SDAR, are not implemented. */ + env->spr[SPR_POWER_SIAR] = prev_ip; + error_code = PPC_BIT(33); + } + raise_exception_err(env, POWERPC_EXCP_TRACE, error_code); +} + void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index abec6fe341..f4db32ee1a 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -32,6 +32,7 @@ DEF_HELPER_2(read_pmc, tl, env, i32) DEF_HELPER_2(insns_inc, void, env, i32) DEF_HELPER_1(handle_pmc5_overflow, void, env) #endif +DEF_HELPER_2(book3s_trace, void, env, tl) DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) #endif diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 06530dd782..5051596670 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -338,8 +338,9 @@ static void gen_ppc_maybe_interrupt(DisasContext *ctx) * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or * POWERPC_EXCP_DEBUG (on BookE). */ -static uint32_t gen_prep_dbgex(DisasContext *ctx) +static void gen_debug_exception(DisasContext *ctx) { +#if !defined(CONFIG_USER_ONLY) if (ctx->flags & POWERPC_FLAG_DE) { target_ulong dbsr = 0; if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { @@ -352,16 +353,16 @@ static uint32_t gen_prep_dbgex(DisasContext *ctx) gen_load_spr(t0, SPR_BOOKE_DBSR); tcg_gen_ori_tl(t0, t0, dbsr); gen_store_spr(SPR_BOOKE_DBSR, t0); - return POWERPC_EXCP_DEBUG; + gen_helper_raise_exception(cpu_env, + tcg_constant_i32(POWERPC_EXCP_DEBUG)); + ctx->base.is_jmp = DISAS_NORETURN; } else { - return POWERPC_EXCP_TRACE; + TCGv t0 = tcg_temp_new(); + tcg_gen_movi_tl(t0, ctx->cia); + gen_helper_book3s_trace(cpu_env, t0); + ctx->base.is_jmp = DISAS_NORETURN; } -} - -static void gen_debug_exception(DisasContext *ctx) -{ - gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); - ctx->base.is_jmp = DISAS_NORETURN; +#endif } static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) @@ -4184,7 +4185,7 @@ static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) static void gen_lookup_and_goto_ptr(DisasContext *ctx) { if (unlikely(ctx->singlestep_enabled)) { - gen_debug_exception(ctx); + gen_debug_exception(ctx, false); } else { /* * tcg_gen_lookup_and_goto_ptr will exit the TB if From patchwork Tue Aug 8 03:11:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1818411 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=LaxAb0tn; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RKdYC0PPQz1yYC for ; Tue, 8 Aug 2023 13:13:03 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qTD8M-0008Lt-7g; Mon, 07 Aug 2023 23:11:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qTD8I-0008K3-Ud; Mon, 07 Aug 2023 23:11:42 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qTD8G-0008Vy-Ee; Mon, 07 Aug 2023 23:11:41 -0400 Received: by mail-pg1-x534.google.com with SMTP id 41be03b00d2f7-55fcc15e109so2860709a12.3; Mon, 07 Aug 2023 20:11:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1691464299; x=1692069099; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DdO+BgECe+NBqSgQRBKGGSekj1Ses6+qG4z/10qrFu4=; b=LaxAb0tnWl+Cas3A4/SxcjS2iv3mtQmkfOQHPJl9ZlLs7Zrk0wHI7qNJ5JlD0FCFVm WXxBh0d7B2VpVt55tA7eiLMUGvBf+5q4GfIwc2YYhpo/ly+VcjcJlJEXWV+GW+FKYVde zgFMq/24D+0+hQFlm2G1SoUqgp4EpV9+X+FUaUwVMsTN+CNIaA8Xq+rd9jNgOdaa3vdY AITh0aqzgVd7im1z8XIRi/PilIfZxuoQG18ioL/wsdJMh11D+KZRN57Joy/ewHbZXby4 fh6xUk5ngv1OufGqiuXL0q744UWqMhZdT1IpJNBtX6XccDmNNE8XmZZGYpC6hOGB/BPb NV8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691464299; x=1692069099; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DdO+BgECe+NBqSgQRBKGGSekj1Ses6+qG4z/10qrFu4=; b=AqjCfctyk8Q6Q68ew7oSJoIVVoF9RNpbxXqF0El5t1EX63F4unpYTF+jFi22WN4egZ 0d/lhwJY1pPb8TF8dcNgRZmrLypV1uLEQ7iL4L4AikYgTwuUMOtvk/Pql2Q+YL0DfFBo K6o9YP+6KfprwWKZhTm1/8xfqhcxilN22sxdQ3mHmJk9hiDwsfmLXB0WoWQxuZKbmRgh vhB760Rsi7wr4c1mLzhsUqfRISnz0dEsMPwKl5gL606XunrRUFIJrA82egEjT/RxRISm gNNwA4rTfgf5XBu2e0FY/j2BecnhMkWotmShWoaRCNTmgIkCizYvZHya6MiEJTCijluD rM1A== X-Gm-Message-State: AOJu0Yzg/7l6ZM2utId9D0D5VzMT75U6gML5/esjsXCCgNpKrAnPX5C5 rkE3uxFV/d52dinl2JFg4tk= X-Google-Smtp-Source: AGHT+IFlFgxPiOAqxlG46MvqtmpXqEmxMKS7TNaYBGDo2ayu+deqFtQHjIYcPmvN5A6OIALfsNjB6w== X-Received: by 2002:a05:6a20:728a:b0:133:dc0a:37e7 with SMTP id o10-20020a056a20728a00b00133dc0a37e7mr11270661pzk.13.1691464298665; Mon, 07 Aug 2023 20:11:38 -0700 (PDT) Received: from wheely.local0.net (61-68-137-140.tpgi.com.au. [61.68.137.140]) by smtp.gmail.com with ESMTPSA id i21-20020aa79095000000b00687ce7c6540sm482642pfa.99.2023.08.07.20.11.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:38 -0700 (PDT) From: Nicholas Piggin To: Daniel Henrique Barboza Cc: Nicholas Piggin , =?utf-8?q?C=C3=A9dric_Le_Goater?= , David Gibson , Greg Kurz , Harsh Prateek Bora , Shivaprasad G Bhat , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/6] target/ppc: Suppress single step interrupts on rfi-type instructions Date: Tue, 8 Aug 2023 13:11:13 +1000 Message-Id: <20230808031116.398205-4-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230808031116.398205-1-npiggin@gmail.com> References: <20230808031116.398205-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=npiggin@gmail.com; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org BookS does not take single step interrupts on completion of rfi and similar (rfid, hrfid, rfscv). This is not a completely clean way to do it, but in general non-branch instructions that change NIP on completion are excluded. Signed-off-by: Nicholas Piggin --- target/ppc/translate.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 5051596670..6e8f1797ac 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -338,7 +338,7 @@ static void gen_ppc_maybe_interrupt(DisasContext *ctx) * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or * POWERPC_EXCP_DEBUG (on BookE). */ -static void gen_debug_exception(DisasContext *ctx) +static void gen_debug_exception(DisasContext *ctx, bool rfi_type) { #if !defined(CONFIG_USER_ONLY) if (ctx->flags & POWERPC_FLAG_DE) { @@ -357,10 +357,12 @@ static void gen_debug_exception(DisasContext *ctx) tcg_constant_i32(POWERPC_EXCP_DEBUG)); ctx->base.is_jmp = DISAS_NORETURN; } else { - TCGv t0 = tcg_temp_new(); - tcg_gen_movi_tl(t0, ctx->cia); - gen_helper_book3s_trace(cpu_env, t0); - ctx->base.is_jmp = DISAS_NORETURN; + if (!rfi_type) { /* BookS does not single step rfi type instructions */ + TCGv t0 = tcg_temp_new(); + tcg_gen_movi_tl(t0, ctx->cia); + gen_helper_book3s_trace(cpu_env, t0); + ctx->base.is_jmp = DISAS_NORETURN; + } } #endif } @@ -7412,6 +7414,8 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) /* Honor single stepping. */ if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)) { + bool rfi_type = false; + switch (is_jmp) { case DISAS_TOO_MANY: case DISAS_EXIT_UPDATE: @@ -7420,12 +7424,19 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) break; case DISAS_EXIT: case DISAS_CHAIN: + /* + * This is a heuristic, to put it kindly. The rfi class of + * instructions are among the few outside branches that change + * NIP without taking an interrupt. Single step trace interrupts + * do not fire on completion of these instructions. + */ + rfi_type = true; break; default: g_assert_not_reached(); } - gen_debug_exception(ctx); + gen_debug_exception(ctx, rfi_type); return; } From patchwork Tue Aug 8 03:11:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1818436 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=ObQ5J7ws; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RKdb35txlz1yYC for ; Tue, 8 Aug 2023 13:14:39 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qTD8O-0008Ns-6R; Mon, 07 Aug 2023 23:11:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qTD8M-0008Ma-S8; Mon, 07 Aug 2023 23:11:46 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qTD8K-00006W-Rh; Mon, 07 Aug 2023 23:11:46 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-686f1240a22so5036671b3a.0; Mon, 07 Aug 2023 20:11:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1691464303; x=1692069103; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w1q5Gsi/L3hnN6qOaWO0OZSWxAFKtlVpAZ7WsDVYQCY=; b=ObQ5J7ws7qyYD2MmWZxAFGTSDQDFoSM3wtBdCtGoXiQepjbrJSrytqJNZkjnARGFG3 W3VZPY9a2VB1BPo+4AQHMjMKRJ/VPVxTwo+R6WUuKfDERAwnAYLD1L8FxOsCu0JRfrcg ACjKMETWS0p9EX5bn3jzakzX/BH2wdfvc+AvFo6jqelgANMY2am3KKB7ygJIUFNL+4F7 hcqzqe9jy+aD7fMIlwXp/5JMQnXnH4n2jbk3ssgXQAQyUTlCk1Y22DGmDWD7F536NaVf 8ylF/KrGiwMOZpCcOSW9DCxdBWaOphGxPQI2u2t+o0JIWlaGCZYhZ/NNyhsWN97oAL+K yOFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691464303; x=1692069103; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w1q5Gsi/L3hnN6qOaWO0OZSWxAFKtlVpAZ7WsDVYQCY=; b=JVyDpXxSova3fNtUaqEi5NcNCn2MUfE7B8dH2VN0AFEuxR7hBRBbMJVHHo1YZ8leLL FW5rbnuMK4itOjFt4qsTQ0Ani3yEio85nuR0i/a6Dr9KMAD2k0sHtRaWqIGU6zRELZ32 rPcmvCbLcF84aqJRZogKXZLDKZle+6uCqKZe2nHuHEdjNx9nCyVGKhVW26peiMkIPmtS DBeFCRF5nnQdU5Z80+jH5WNSTXMCA00URSUtALdtUScjW2cFAzIiQIVmwseuJHe/Zlbj P6df8Mgoc4Pd25Asbikg0sLvFW8U4T+NlDOqyFp4hg8h1VMHbJ1Z7l+7f0OiwC4j1RFJ y7PQ== X-Gm-Message-State: AOJu0Yz9zl93zDCjk6SjTMRLoX+KbymCs6aTI8Ja1QU5UeOCxH3gWUz0 wQ+1OrQrMbhvYWmCiPm7m1o= X-Google-Smtp-Source: AGHT+IGqkq5CCb4Mw1gbSE3q/qtW3ByEdh9vfhNn7npF/OCmCNM9pDCTA9Km2pLPSHaySoO41WAoow== X-Received: by 2002:a05:6a20:258b:b0:13e:e3aa:d871 with SMTP id k11-20020a056a20258b00b0013ee3aad871mr14458846pzd.53.1691464303125; Mon, 07 Aug 2023 20:11:43 -0700 (PDT) Received: from wheely.local0.net (61-68-137-140.tpgi.com.au. [61.68.137.140]) by smtp.gmail.com with ESMTPSA id i21-20020aa79095000000b00687ce7c6540sm482642pfa.99.2023.08.07.20.11.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:42 -0700 (PDT) From: Nicholas Piggin To: Daniel Henrique Barboza Cc: Nicholas Piggin , =?utf-8?q?C=C3=A9dric_Le_Goater?= , David Gibson , Greg Kurz , Harsh Prateek Bora , Shivaprasad G Bhat , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 4/6] target/ppc: Implement breakpoint debug facility for v2.07S Date: Tue, 8 Aug 2023 13:11:14 +1000 Message-Id: <20230808031116.398205-5-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230808031116.398205-1-npiggin@gmail.com> References: <20230808031116.398205-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org ISA v2.07S introduced the breakpoint facility based on the CIABR SPR. Implement this in TCG. Signed-off-by: Nicholas Piggin --- target/ppc/cpu.c | 27 ++++++++++++++++++++++++++ target/ppc/cpu.h | 3 +++ target/ppc/cpu_init.c | 5 ++++- target/ppc/excp_helper.c | 42 ++++++++++++++++++++++++++++++++++++++++ target/ppc/helper.h | 1 + target/ppc/internal.h | 2 ++ target/ppc/machine.c | 4 ++++ target/ppc/misc_helper.c | 5 +++++ target/ppc/spr_common.h | 1 + target/ppc/translate.c | 10 +++++++++- 10 files changed, 98 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index 424f2e1741..d9c665ce18 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -102,6 +102,33 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) ppc_maybe_interrupt(env); } + +#if defined(TARGET_PPC64) +void ppc_update_ciabr(CPUPPCState *env) +{ + CPUState *cs = env_cpu(env); + target_ulong ciabr = env->spr[SPR_CIABR]; + target_ulong ciea, priv; + + ciea = ciabr & PPC_BITMASK(0, 61); + priv = ciabr & PPC_BITMASK(62, 63); + + if (env->ciabr_breakpoint) { + cpu_breakpoint_remove_by_ref(cs, env->ciabr_breakpoint); + env->ciabr_breakpoint = NULL; + } + + if (priv) { + cpu_breakpoint_insert(cs, ciea, BP_CPU, &env->ciabr_breakpoint); + } +} + +void ppc_store_ciabr(CPUPPCState *env, target_ulong val) +{ + env->spr[SPR_CIABR] = val; + ppc_update_ciabr(env); +} +#endif #endif static inline void fpscr_set_rounding_mode(CPUPPCState *env) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 25fac9577a..d97fabd8f6 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1137,6 +1137,7 @@ struct CPUArchState { /* MMU context, only relevant for full system emulation */ #if defined(TARGET_PPC64) ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */ + struct CPUBreakpoint *ciabr_breakpoint; #endif target_ulong sr[32]; /* segment registers */ uint32_t nb_BATs; /* number of BATs */ @@ -1403,6 +1404,8 @@ void ppc_translate_init(void); #if !defined(CONFIG_USER_ONLY) void ppc_store_sdr1(CPUPPCState *env, target_ulong value); void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val); +void ppc_update_ciabr(CPUPPCState *env); +void ppc_store_ciabr(CPUPPCState *env, target_ulong value); #endif /* !defined(CONFIG_USER_ONLY) */ void ppc_store_msr(CPUPPCState *env, target_ulong value); diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 02b7aad9b0..a2820839b3 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5127,7 +5127,7 @@ static void register_book3s_207_dbg_sprs(CPUPPCState *env) spr_register_kvm_hv(env, SPR_CIABR, "CIABR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_ciabr, KVM_REG_PPC_CIABR, 0x00000000); } @@ -7149,6 +7149,7 @@ static void ppc_cpu_reset_hold(Object *obj) env->nip = env->hreset_vector | env->excp_prefix; if (tcg_enabled()) { + cpu_breakpoint_remove_all(s, BP_CPU); if (env->mmu_model != POWERPC_MMU_REAL) { ppc_tlb_invalidate_all(env); } @@ -7336,6 +7337,8 @@ static const struct TCGCPUOps ppc_tcg_ops = { .cpu_exec_exit = ppc_cpu_exec_exit, .do_unaligned_access = ppc_cpu_do_unaligned_access, .do_transaction_failed = ppc_cpu_do_transaction_failed, + .debug_excp_handler = ppc_cpu_debug_excp_handler, + .debug_check_breakpoint = ppc_cpu_debug_check_breakpoint, #endif /* !CONFIG_USER_ONLY */ }; #endif /* CONFIG_TCG */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 2d6aef5e66..9c9881ae19 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -3257,5 +3257,47 @@ void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, cs->exception_index = POWERPC_EXCP_MCHECK; cpu_loop_exit_restore(cs, retaddr); } + +void ppc_cpu_debug_excp_handler(CPUState *cs) +{ +#if defined(TARGET_PPC64) + CPUPPCState *env = cs->env_ptr; + + if (env->insns_flags2 & PPC2_ISA207S) { + if (cpu_breakpoint_test(cs, env->nip, BP_CPU)) { + raise_exception_err(env, POWERPC_EXCP_TRACE, + PPC_BIT(33) | PPC_BIT(43)); + } + } +#endif +} + +bool ppc_cpu_debug_check_breakpoint(CPUState *cs) +{ +#if defined(TARGET_PPC64) + CPUPPCState *env = cs->env_ptr; + + if (env->insns_flags2 & PPC2_ISA207S) { + target_ulong priv; + + priv = env->spr[SPR_CIABR] & PPC_BITMASK(62, 63); + switch (priv) { + case 0x1: /* problem */ + return env->msr & ((target_ulong)1 << MSR_PR); + case 0x2: /* supervisor */ + return (!(env->msr & ((target_ulong)1 << MSR_PR)) && + !(env->msr & ((target_ulong)1 << MSR_HV))); + case 0x3: /* hypervisor */ + return (!(env->msr & ((target_ulong)1 << MSR_PR)) && + (env->msr & ((target_ulong)1 << MSR_HV))); + default: + g_assert_not_reached(); + } + } +#endif + + return false; +} + #endif /* CONFIG_TCG */ #endif /* !CONFIG_USER_ONLY */ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index f4db32ee1a..83d5deec07 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -25,6 +25,7 @@ DEF_HELPER_1(hrfid, void, env) DEF_HELPER_2(rfebb, void, env, tl) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) +DEF_HELPER_2(store_ciabr, void, env, tl) DEF_HELPER_2(store_mmcr0, void, env, tl) DEF_HELPER_2(store_mmcr1, void, env, tl) DEF_HELPER_3(store_pmc, void, env, i32, i64) diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 57acb3212c..16f02fd9c4 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -301,6 +301,8 @@ void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); +void ppc_cpu_debug_excp_handler(CPUState *cs); +bool ppc_cpu_debug_check_breakpoint(CPUState *cs); #endif FIELD(GER_MSK, XMSK, 0, 4) diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 134b16c625..560a875454 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -314,6 +314,10 @@ static int cpu_post_load(void *opaque, int version_id) post_load_update_msr(env); if (tcg_enabled()) { + /* Re-set breaks based on regs */ +#if defined(TARGET_PPC64) + ppc_update_ciabr(env); +#endif pmu_mmcr01_updated(env); } diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 692d058665..0b0f2e59a7 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -199,6 +199,11 @@ void helper_store_pcr(CPUPPCState *env, target_ulong value) env->spr[SPR_PCR] = value & pcc->pcr_mask; } +void helper_store_ciabr(CPUPPCState *env, target_ulong value) +{ + ppc_store_ciabr(env, value); +} + /* * DPDES register is shared. Each bit reflects the state of the * doorbell interrupt of a thread of the same core. diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h index 5995070eaf..b7bedd9ef1 100644 --- a/target/ppc/spr_common.h +++ b/target/ppc/spr_common.h @@ -159,6 +159,7 @@ void spr_read_mas73(DisasContext *ctx, int gprn, int sprn); #ifdef TARGET_PPC64 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn); void spr_write_cfar(DisasContext *ctx, int sprn, int gprn); +void spr_write_ciabr(DisasContext *ctx, int sprn, int gprn); void spr_write_ureg(DisasContext *ctx, int sprn, int gprn); void spr_read_purr(DisasContext *ctx, int gprn, int sprn); void spr_write_purr(DisasContext *ctx, int sprn, int gprn); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 6e8f1797ac..69dd1ba036 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -559,8 +559,9 @@ void spr_write_lr(DisasContext *ctx, int sprn, int gprn) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); } -/* CFAR */ #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +/* Debug facilities */ +/* CFAR */ void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) { tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); @@ -570,6 +571,13 @@ void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) { tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); } + +/* Breakpoint */ +void spr_write_ciabr(DisasContext *ctx, int sprn, int gprn) +{ + translator_io_start(&ctx->base); + gen_helper_store_ciabr(cpu_env, cpu_gpr[gprn]); +} #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ /* CTR */ From patchwork Tue Aug 8 03:11:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1818463 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=W+97vf+P; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RKdgS366wz1yfM for ; Tue, 8 Aug 2023 13:18:28 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qTD8a-0000F8-3i; Mon, 07 Aug 2023 23:12:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qTD8W-0000Ac-Lg; Mon, 07 Aug 2023 23:11:56 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qTD8P-00008Y-6S; Mon, 07 Aug 2023 23:11:56 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-686ed1d2594so5018717b3a.2; Mon, 07 Aug 2023 20:11:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1691464307; x=1692069107; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ubGDB2qj8/qo/M7/3E+WlIgrPNVGuE9tGgWRkmW+aeo=; b=W+97vf+P6yxlzhVdPA8EnJ7g5Qpc/6jARDmmdKk4JEAQMQOTWScsT7B2xHZWJRX65v 4YESCxDmTkxpRKuRo3kg0oynq9DZGxdazN++A3ILWQUf7t4VnsEpoJuKEphJb/GGT5KC MIUDPp+GdLfAC68rAYbpTPLNJqTMhpqjVNhWjJNS4yo092r4NqbFZM9tXIsqhLj3/qyU MVnKtkIu0U7yUM/LqEaws72phF3f46v64DqqxT1KbLGUDWbbiOakzJp/cjDTh/HRQeeF Vjs5N2/2BwObryANLfUZRABCslcKF6cLUngwWLzf/WT7p7hw73xRkE0Qe12olznOZRYJ WVuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691464307; x=1692069107; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ubGDB2qj8/qo/M7/3E+WlIgrPNVGuE9tGgWRkmW+aeo=; b=QAs61S4tKztSm6QBeNG+YyPC9LBM7JOSmkuxA8Qps3ocMDmbwDPfKUX9f+6Us8eRDk Mv5HXMCBIRpWR8hxFHdX8XKWp/V43IK/B5NzLeuINUUZpYEPD/UGUU0HUKk2p5thcY/U jsTVds4V/ZffT5ZuXBR6irgAoAqjhmh/XPXLEnHkJFKSBI+dqkjk2Sm2vm+KUG1v1BsO bpZK9Uw+xoHslOGzTrMwpxXnTnftmJ7YKO90yEMHGjrM5n6Bi96Cw/n/akkYV7KRfQ1Z Gkaw23c4aNPlHQb1nm5wWGZdfrY/wsrvtgz627zOX/VfR4wgMrTpsYXG31e73zuMX1U0 ybBw== X-Gm-Message-State: AOJu0YzsyEV0QzoOfvFBPhpuhH40jRJWI72CHlP5OnTjAnHXRi2vuT60 UePI97Z/REvsI1UmCacXHME= X-Google-Smtp-Source: AGHT+IHemeHd2yw143JuZGoW9Q76hNA2DX5rkCaDB6AUHpCIYR5W/WCA6YslUTb8k8JP1ccw0LdaWQ== X-Received: by 2002:a05:6a21:6da6:b0:140:54ab:7f3f with SMTP id wl38-20020a056a216da600b0014054ab7f3fmr11142392pzb.50.1691464307572; Mon, 07 Aug 2023 20:11:47 -0700 (PDT) Received: from wheely.local0.net (61-68-137-140.tpgi.com.au. [61.68.137.140]) by smtp.gmail.com with ESMTPSA id i21-20020aa79095000000b00687ce7c6540sm482642pfa.99.2023.08.07.20.11.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:47 -0700 (PDT) From: Nicholas Piggin To: Daniel Henrique Barboza Cc: Nicholas Piggin , =?utf-8?q?C=C3=A9dric_Le_Goater?= , David Gibson , Greg Kurz , Harsh Prateek Bora , Shivaprasad G Bhat , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 5/6] target/ppc: Implement watchpoint debug facility for v2.07S Date: Tue, 8 Aug 2023 13:11:15 +1000 Message-Id: <20230808031116.398205-6-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230808031116.398205-1-npiggin@gmail.com> References: <20230808031116.398205-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=npiggin@gmail.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org ISA v2.07S introduced the watchpoint facility based on the DAWR0 and DAWRX0 SPRs. Implement this in TCG. Signed-off-by: Nicholas Piggin --- target/ppc/cpu.c | 59 ++++++++++++++++++++++++++++++++++++++++ target/ppc/cpu.h | 4 +++ target/ppc/cpu_init.c | 6 ++-- target/ppc/excp_helper.c | 52 ++++++++++++++++++++++++++++++++++- target/ppc/helper.h | 2 ++ target/ppc/internal.h | 1 + target/ppc/machine.c | 1 + target/ppc/misc_helper.c | 10 +++++++ target/ppc/spr_common.h | 2 ++ target/ppc/translate.c | 13 +++++++++ 10 files changed, 147 insertions(+), 3 deletions(-) diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index d9c665ce18..62e1c15e3d 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -128,6 +128,65 @@ void ppc_store_ciabr(CPUPPCState *env, target_ulong val) env->spr[SPR_CIABR] = val; ppc_update_ciabr(env); } + +void ppc_update_daw0(CPUPPCState *env) +{ + CPUState *cs = env_cpu(env); + target_ulong deaw = env->spr[SPR_DAWR0] & PPC_BITMASK(0, 60); + uint32_t dawrx = env->spr[SPR_DAWRX0]; + int mrd = extract32(dawrx, PPC_BIT_NR(48), 54 - 48); + bool dw = extract32(dawrx, PPC_BIT_NR(57), 1); + bool dr = extract32(dawrx, PPC_BIT_NR(58), 1); + bool hv = extract32(dawrx, PPC_BIT_NR(61), 1); + bool sv = extract32(dawrx, PPC_BIT_NR(62), 1); + bool pr = extract32(dawrx, PPC_BIT_NR(62), 1); + vaddr len; + int flags; + + if (env->dawr0_watchpoint) { + cpu_watchpoint_remove_by_ref(cs, env->dawr0_watchpoint); + env->dawr0_watchpoint = NULL; + } + + if (!dr && !dw) { + return; + } + + if (!hv && !sv && !pr) { + return; + } + + len = (mrd + 1) * 8; + flags = BP_CPU | BP_STOP_BEFORE_ACCESS; + if (dr) { + flags |= BP_MEM_READ; + } + if (dw) { + flags |= BP_MEM_WRITE; + } + + cpu_watchpoint_insert(cs, deaw, len, flags, &env->dawr0_watchpoint); +} + +void ppc_store_dawr0(CPUPPCState *env, target_ulong val) +{ + env->spr[SPR_DAWR0] = val; + ppc_update_daw0(env); +} + +void ppc_store_dawrx0(CPUPPCState *env, uint32_t val) +{ + int hrammc = extract32(val, PPC_BIT_NR(56), 1); + + if (hrammc) { + /* This might be done with a second watchpoint at the xor of DEAW[0] */ + qemu_log_mask(LOG_UNIMP, "%s: DAWRX0[HRAMMC] is unimplemented\n", + __func__); + } + + env->spr[SPR_DAWRX0] = val; + ppc_update_daw0(env); +} #endif #endif diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index d97fabd8f6..2777ea3110 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1138,6 +1138,7 @@ struct CPUArchState { #if defined(TARGET_PPC64) ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */ struct CPUBreakpoint *ciabr_breakpoint; + struct CPUWatchpoint *dawr0_watchpoint; #endif target_ulong sr[32]; /* segment registers */ uint32_t nb_BATs; /* number of BATs */ @@ -1406,6 +1407,9 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value); void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val); void ppc_update_ciabr(CPUPPCState *env); void ppc_store_ciabr(CPUPPCState *env, target_ulong value); +void ppc_update_daw0(CPUPPCState *env); +void ppc_store_dawr0(CPUPPCState *env, target_ulong value); +void ppc_store_dawrx0(CPUPPCState *env, uint32_t value); #endif /* !defined(CONFIG_USER_ONLY) */ void ppc_store_msr(CPUPPCState *env, target_ulong value); diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index a2820839b3..9c1c045d1b 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5117,12 +5117,12 @@ static void register_book3s_207_dbg_sprs(CPUPPCState *env) spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_dawr0, KVM_REG_PPC_DAWR, 0x00000000); spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic32, + &spr_read_generic, &spr_write_dawrx0, KVM_REG_PPC_DAWRX, 0x00000000); spr_register_kvm_hv(env, SPR_CIABR, "CIABR", SPR_NOACCESS, SPR_NOACCESS, @@ -7150,6 +7150,7 @@ static void ppc_cpu_reset_hold(Object *obj) if (tcg_enabled()) { cpu_breakpoint_remove_all(s, BP_CPU); + cpu_watchpoint_remove_all(s, BP_CPU); if (env->mmu_model != POWERPC_MMU_REAL) { ppc_tlb_invalidate_all(env); } @@ -7339,6 +7340,7 @@ static const struct TCGCPUOps ppc_tcg_ops = { .do_transaction_failed = ppc_cpu_do_transaction_failed, .debug_excp_handler = ppc_cpu_debug_excp_handler, .debug_check_breakpoint = ppc_cpu_debug_check_breakpoint, + .debug_check_watchpoint = ppc_cpu_debug_check_watchpoint, #endif /* !CONFIG_USER_ONLY */ }; #endif /* CONFIG_TCG */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 9c9881ae19..32e46e56b3 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -3264,7 +3264,15 @@ void ppc_cpu_debug_excp_handler(CPUState *cs) CPUPPCState *env = cs->env_ptr; if (env->insns_flags2 & PPC2_ISA207S) { - if (cpu_breakpoint_test(cs, env->nip, BP_CPU)) { + if (cs->watchpoint_hit) { + if (cs->watchpoint_hit->flags & BP_CPU) { + env->spr[SPR_DAR] = cs->watchpoint_hit->hitaddr; + env->spr[SPR_DSISR] = PPC_BIT(41); + cs->watchpoint_hit = NULL; + raise_exception(env, POWERPC_EXCP_DSI); + } + cs->watchpoint_hit = NULL; + } else if (cpu_breakpoint_test(cs, env->nip, BP_CPU)) { raise_exception_err(env, POWERPC_EXCP_TRACE, PPC_BIT(33) | PPC_BIT(43)); } @@ -3299,5 +3307,47 @@ bool ppc_cpu_debug_check_breakpoint(CPUState *cs) return false; } +bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) +{ +#if defined(TARGET_PPC64) + CPUPPCState *env = cs->env_ptr; + + if (env->insns_flags2 & PPC2_ISA207S) { + if (wp == env->dawr0_watchpoint) { + uint32_t dawrx = env->spr[SPR_DAWRX0]; + bool wt = extract32(dawrx, PPC_BIT_NR(59), 1); + bool wti = extract32(dawrx, PPC_BIT_NR(60), 1); + bool hv = extract32(dawrx, PPC_BIT_NR(61), 1); + bool sv = extract32(dawrx, PPC_BIT_NR(62), 1); + bool pr = extract32(dawrx, PPC_BIT_NR(62), 1); + + if ((env->msr & ((target_ulong)1 << MSR_PR)) && !pr) { + return false; + } else if ((env->msr & ((target_ulong)1 << MSR_HV)) && !hv) { + return false; + } else if (!sv) { + return false; + } + + if (!wti) { + if (env->msr & ((target_ulong)1 << MSR_DR)) { + if (!wt) { + return false; + } + } else { + if (wt) { + return false; + } + } + } + + return true; + } + } +#endif + + return false; +} + #endif /* CONFIG_TCG */ #endif /* !CONFIG_USER_ONLY */ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 83d5deec07..86f97ee1e7 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -26,6 +26,8 @@ DEF_HELPER_2(rfebb, void, env, tl) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) DEF_HELPER_2(store_ciabr, void, env, tl) +DEF_HELPER_2(store_dawr0, void, env, tl) +DEF_HELPER_2(store_dawrx0, void, env, tl) DEF_HELPER_2(store_mmcr0, void, env, tl) DEF_HELPER_2(store_mmcr1, void, env, tl) DEF_HELPER_3(store_pmc, void, env, i32, i64) diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 16f02fd9c4..15803bc313 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -303,6 +303,7 @@ void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, MemTxResult response, uintptr_t retaddr); void ppc_cpu_debug_excp_handler(CPUState *cs); bool ppc_cpu_debug_check_breakpoint(CPUState *cs); +bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); #endif FIELD(GER_MSK, XMSK, 0, 4) diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 560a875454..8234e35d69 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -317,6 +317,7 @@ static int cpu_post_load(void *opaque, int version_id) /* Re-set breaks based on regs */ #if defined(TARGET_PPC64) ppc_update_ciabr(env); + ppc_update_daw0(env); #endif pmu_mmcr01_updated(env); } diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 0b0f2e59a7..a05bdf78c9 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -204,6 +204,16 @@ void helper_store_ciabr(CPUPPCState *env, target_ulong value) ppc_store_ciabr(env, value); } +void helper_store_dawr0(CPUPPCState *env, target_ulong value) +{ + ppc_store_dawr0(env, value); +} + +void helper_store_dawrx0(CPUPPCState *env, target_ulong value) +{ + ppc_store_dawrx0(env, value); +} + /* * DPDES register is shared. Each bit reflects the state of the * doorbell interrupt of a thread of the same core. diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h index b7bedd9ef1..8a9d6cd994 100644 --- a/target/ppc/spr_common.h +++ b/target/ppc/spr_common.h @@ -160,6 +160,8 @@ void spr_read_mas73(DisasContext *ctx, int gprn, int sprn); void spr_read_cfar(DisasContext *ctx, int gprn, int sprn); void spr_write_cfar(DisasContext *ctx, int sprn, int gprn); void spr_write_ciabr(DisasContext *ctx, int sprn, int gprn); +void spr_write_dawr0(DisasContext *ctx, int sprn, int gprn); +void spr_write_dawrx0(DisasContext *ctx, int sprn, int gprn); void spr_write_ureg(DisasContext *ctx, int sprn, int gprn); void spr_read_purr(DisasContext *ctx, int gprn, int sprn); void spr_write_purr(DisasContext *ctx, int sprn, int gprn); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 69dd1ba036..b8c7f38ccd 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -578,6 +578,19 @@ void spr_write_ciabr(DisasContext *ctx, int sprn, int gprn) translator_io_start(&ctx->base); gen_helper_store_ciabr(cpu_env, cpu_gpr[gprn]); } + +/* Watchpoint */ +void spr_write_dawr0(DisasContext *ctx, int sprn, int gprn) +{ + translator_io_start(&ctx->base); + gen_helper_store_dawr0(cpu_env, cpu_gpr[gprn]); +} + +void spr_write_dawrx0(DisasContext *ctx, int sprn, int gprn) +{ + translator_io_start(&ctx->base); + gen_helper_store_dawrx0(cpu_env, cpu_gpr[gprn]); +} #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ /* CTR */ From patchwork Tue Aug 8 03:11:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1818413 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=dDEKvxkU; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RKdYD4Myvz1yfh for ; Tue, 8 Aug 2023 13:13:04 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qTD8f-0000hK-Vb; Mon, 07 Aug 2023 23:12:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qTD8d-0000R6-8k; Mon, 07 Aug 2023 23:12:03 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qTD8T-0000C8-LC; Mon, 07 Aug 2023 23:12:02 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-686b643df5dso3542108b3a.1; Mon, 07 Aug 2023 20:11:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1691464312; x=1692069112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EXoNaDMEIb16Of1z+9cYJroeocVZ6F6dzNKf9wLt4a8=; b=dDEKvxkUHvFwcuhC2e1u4F19bxYR3bGDiaTPAWV6/HdMUBd1g28M9Kb8avbhbKUBko MOLL08FLMRTlmcqfJfR79vLiB/7Qkw7wrgwX/ibDdlqa4sVmu3XZT7P3mS2Qe+MLK645 Cza54tjG258mFeU+2RMlPvebycr0XHY5uhptXCtwlBUtJt24S2k6m0wYTTfUpS6wsJsy MXQVF8ildWZFVT10n3pjootLr/5NEOGRcy++vldQCwjQbb+2vrUztO5ElqUv4pSiQvwI kDpeBPJ05pq4ZzLQ/Ek2Q2IgJJeE+Q0lWoMkNtBZ3WohqKW3icK1fT5SYTGn/1WYIPXy XAhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691464312; x=1692069112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EXoNaDMEIb16Of1z+9cYJroeocVZ6F6dzNKf9wLt4a8=; b=kloEuYnrB+06mysdsBQT+lYAADn2k+Yu7Jj1Sz+B/KMda0S/KYKfPa89ZfU+Gyv3jk 3gaEhdLu2+fPOWNDTcpjXvfJZMVm4+A02nNL0sAqrcpIT6OGxMzV8uHxvrZOz+RjszyA AZ5MmR9eaR1/NrVM0Hj7LKmZGj1Eg4tbpXoU8m2+klGVjbFt0xTbrRqQYGHzsHMjSar/ f82gkiQwdsSDVqe1TrFngkaES7ZhsGrgrDKu5Ndk8VtXnIVNKRDze8b0NGBgiJoi0z66 FdwkxneInLX92LndSo8je/WtKIlVWe5SM0HsmV/UW4DgkNSD0CqWfPPLickZHkQhG79o YI9w== X-Gm-Message-State: AOJu0YymzY6ZL8Gl39dLuccnaSiapsV3PuCYu/Z9qoyg36zZVLLplYBC sNqaBUNgfd1VSAU6hTI9WXyZ+fImNPY= X-Google-Smtp-Source: AGHT+IFjwmj+sRni1CyvSSVUX3oab5G1rxwYphtMGjlvUPIbcr1VsLiAMC1EuGoq8wSrw0rXATjxtg== X-Received: by 2002:a05:6a00:1810:b0:686:25fe:d575 with SMTP id y16-20020a056a00181000b0068625fed575mr10134947pfa.11.1691464311982; Mon, 07 Aug 2023 20:11:51 -0700 (PDT) Received: from wheely.local0.net (61-68-137-140.tpgi.com.au. [61.68.137.140]) by smtp.gmail.com with ESMTPSA id i21-20020aa79095000000b00687ce7c6540sm482642pfa.99.2023.08.07.20.11.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:51 -0700 (PDT) From: Nicholas Piggin To: Daniel Henrique Barboza Cc: Nicholas Piggin , =?utf-8?q?C=C3=A9dric_Le_Goater?= , David Gibson , Greg Kurz , Harsh Prateek Bora , Shivaprasad G Bhat , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 6/6] spapr: implement H_SET_MODE debug facilities Date: Tue, 8 Aug 2023 13:11:16 +1000 Message-Id: <20230808031116.398205-7-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230808031116.398205-1-npiggin@gmail.com> References: <20230808031116.398205-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=npiggin@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Wire up the H_SET_MODE debug resources to the CIABR and DAWR0 debug facilities in TCG. Signed-off-by: Nicholas Piggin --- hw/ppc/spapr_hcall.c | 57 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 9b1f225d4a..b7dc388f2f 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -3,6 +3,7 @@ #include "qapi/error.h" #include "sysemu/hw_accel.h" #include "sysemu/runstate.h" +#include "sysemu/tcg.h" #include "qemu/log.h" #include "qemu/main-loop.h" #include "qemu/module.h" @@ -789,6 +790,54 @@ static target_ulong h_logical_dcbf(PowerPCCPU *cpu, SpaprMachineState *spapr, return H_SUCCESS; } +static target_ulong h_set_mode_resource_set_ciabr(PowerPCCPU *cpu, + SpaprMachineState *spapr, + target_ulong mflags, + target_ulong value1, + target_ulong value2) +{ + CPUPPCState *env = &cpu->env; + + assert(tcg_enabled()); /* KVM will have handled this */ + + if (mflags) { + return H_UNSUPPORTED_FLAG; + } + if (value2) { + return H_P4; + } + if ((value1 & PPC_BITMASK(62, 63)) == 0x3) { + return H_P3; + } + + ppc_store_ciabr(env, value1); + + return H_SUCCESS; +} + +static target_ulong h_set_mode_resource_set_dawr0(PowerPCCPU *cpu, + SpaprMachineState *spapr, + target_ulong mflags, + target_ulong value1, + target_ulong value2) +{ + CPUPPCState *env = &cpu->env; + + assert(tcg_enabled()); /* KVM will have handled this */ + + if (mflags) { + return H_UNSUPPORTED_FLAG; + } + if (value2 & PPC_BIT(61)) { + return H_P4; + } + + ppc_store_dawr0(env, value1); + ppc_store_dawrx0(env, value2); + + return H_SUCCESS; +} + static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, SpaprMachineState *spapr, target_ulong mflags, @@ -858,6 +907,14 @@ static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMachineState *spapr, target_ulong ret = H_P2; switch (resource) { + case H_SET_MODE_RESOURCE_SET_CIABR: + ret = h_set_mode_resource_set_ciabr(cpu, spapr, args[0], args[2], + args[3]); + break; + case H_SET_MODE_RESOURCE_SET_DAWR0: + ret = h_set_mode_resource_set_dawr0(cpu, spapr, args[0], args[2], + args[3]); + break; case H_SET_MODE_RESOURCE_LE: ret = h_set_mode_resource_le(cpu, spapr, args[0], args[2], args[3]); break;