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(dynamic-077-191-074-208.77.191.pool.telefonica.de. [77.191.74.208]) by smtp.gmail.com with ESMTPSA id ec10-20020a170906b6ca00b00982be08a9besm6142817ejb.172.2023.06.28.12.52.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jun 2023 12:52:12 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , "Michael S. Tsirkin" , Marcel Apfelbaum , Richard Henderson , Paolo Bonzini , Bernhard Beschow , Thomas Huth Subject: [PATCH v2 01/16] hw/i386/pc_q35: Resolve redundant q35_host variable Date: Wed, 28 Jun 2023 21:51:49 +0200 Message-ID: <20230628195204.1241-2-shentey@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230628195204.1241-1-shentey@gmail.com> References: <20230628195204.1241-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=shentey@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The variable is redundant to "phb" and is never used by its real type. Signed-off-by: Bernhard Beschow Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé --- hw/i386/pc_q35.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 11a7084ea1..d9f3764184 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -120,8 +120,7 @@ static void pc_q35_init(MachineState *machine) PCMachineState *pcms = PC_MACHINE(machine); PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); X86MachineState *x86ms = X86_MACHINE(machine); - Q35PCIHost *q35_host; - PCIHostState *phb; + Object *phb; PCIBus *host_bus; PCIDevice *lpc; DeviceState *lpc_dev; @@ -207,10 +206,10 @@ static void pc_q35_init(MachineState *machine) } /* create pci host bus */ - q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE)); + phb = OBJECT(qdev_new(TYPE_Q35_HOST_DEVICE)); if (pcmc->pci_enabled) { - pci_hole64_size = object_property_get_uint(OBJECT(q35_host), + pci_hole64_size = object_property_get_uint(phb, PCI_HOST_PROP_PCI_HOLE64_SIZE, &error_abort); } @@ -218,23 +217,23 @@ static void pc_q35_init(MachineState *machine) /* allocate ram and load rom/bios */ pc_memory_init(pcms, system_memory, rom_memory, pci_hole64_size); - object_property_add_child(OBJECT(machine), "q35", OBJECT(q35_host)); - object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM, + object_property_add_child(OBJECT(machine), "q35", phb); + object_property_set_link(phb, MCH_HOST_PROP_RAM_MEM, OBJECT(machine->ram), NULL); - object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_PCI_MEM, + object_property_set_link(phb, MCH_HOST_PROP_PCI_MEM, OBJECT(pci_memory), NULL); - object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_SYSTEM_MEM, + object_property_set_link(phb, MCH_HOST_PROP_SYSTEM_MEM, OBJECT(system_memory), NULL); - object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_IO_MEM, + object_property_set_link(phb, MCH_HOST_PROP_IO_MEM, OBJECT(system_io), NULL); - object_property_set_int(OBJECT(q35_host), PCI_HOST_BELOW_4G_MEM_SIZE, + object_property_set_int(phb, PCI_HOST_BELOW_4G_MEM_SIZE, x86ms->below_4g_mem_size, NULL); - object_property_set_int(OBJECT(q35_host), PCI_HOST_ABOVE_4G_MEM_SIZE, + object_property_set_int(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, x86ms->above_4g_mem_size, NULL); + /* pci */ - sysbus_realize_and_unref(SYS_BUS_DEVICE(q35_host), &error_fatal); - phb = PCI_HOST_BRIDGE(q35_host); - host_bus = phb->bus; + sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); + host_bus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0")); /* create ISA bus */ lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), true, TYPE_ICH9_LPC_DEVICE); From patchwork Wed Jun 28 19:51:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1801244 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; 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(dynamic-077-191-074-208.77.191.pool.telefonica.de. [77.191.74.208]) by smtp.gmail.com with ESMTPSA id ec10-20020a170906b6ca00b00982be08a9besm6142817ejb.172.2023.06.28.12.52.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jun 2023 12:52:13 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , "Michael S. Tsirkin" , Marcel Apfelbaum , Richard Henderson , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 02/16] hw/pci-host/q35: Fix double, contradicting .endianness assignment Date: Wed, 28 Jun 2023 21:51:50 +0200 Message-ID: <20230628195204.1241-3-shentey@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230628195204.1241-1-shentey@gmail.com> References: <20230628195204.1241-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=shentey@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Fixes the following clangd warning (-Winitializer-overrides): q35.c:297:19: Initializer overrides prior initialization of this subobject q35.c:292:19: previous initialization is here Settle on little endian which is consistent with using pci_host_conf_le_ops. Fixes: bafc90bdc594 ("q35: implement TSEG") Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/pci-host/q35.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index fd18920e7f..84137b9ad9 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -285,7 +285,6 @@ static void blackhole_write(void *opaque, hwaddr addr, uint64_t val, static const MemoryRegionOps blackhole_ops = { .read = blackhole_read, .write = blackhole_write, - .endianness = DEVICE_NATIVE_ENDIAN, .valid.min_access_size = 1, .valid.max_access_size = 4, .impl.min_access_size = 4, From patchwork Wed Jun 28 19:51:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1801245 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=g4Zm4T/c; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Qrsh9674xz20b4 for ; Thu, 29 Jun 2023 05:53:13 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qEbDD-0004hP-JB; Wed, 28 Jun 2023 15:52:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qEbD9-0004g8-N0 for qemu-devel@nongnu.org; Wed, 28 Jun 2023 15:52:20 -0400 Received: from mail-lj1-x230.google.com ([2a00:1450:4864:20::230]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qEbD7-0005hx-DW for qemu-devel@nongnu.org; Wed, 28 Jun 2023 15:52:18 -0400 Received: by mail-lj1-x230.google.com with SMTP id 38308e7fff4ca-2b69e6d324aso3657561fa.0 for ; Wed, 28 Jun 2023 12:52:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687981935; x=1690573935; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CCVk7jdt1nDqHH6A+S2BbR5/KvJS5BvxayG0t6p+t7Q=; b=g4Zm4T/cD6DYwp5JSBB0X0v+RiO5uDIPzzlYAGxoch8ZLRDrvu5YE02aGTtwUM1nqD LBMVfM204G/JnDsAw2Cg7DXNd7Kn2zabQRh1gIHko70K8wH4DCWF3kPZlWio/pa1RpRi nkwAKsRgOVQEGuW7ly6hAcipTOg1wTesK3o51cltzhlLExrZJb1TaKejupaWW4Qx4jw8 bK/Vpfu6fcOTiojz25Wup3YAOP7ElYGYk5jlDUQMIyuXr5K1KDi3eVBfbLQ6EgggqU3B Wm/mO6zbVBxvfgHUmgoGt4zgVnJJbFX9f2TbaI/kNx9sC4fGk28Aw2KxqTuNKgrq6gmi fuqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687981935; x=1690573935; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CCVk7jdt1nDqHH6A+S2BbR5/KvJS5BvxayG0t6p+t7Q=; b=QiWj4M1uOKN6wA3BqrYFEn2P6N5ywKwZp3StFRWg4+E+rMi5QmPyTCAGxme3950FAD JN9Ymry4yQuBC2SGqE4mwpMKF0DVjcAq49W0y0BgWx4+aRhnrngYpmtmFDZxB3299Kcr 3b195MqkLQMjJiJhQnO5E0SwAJ1DlRIZwyPYEF7ieAkJDTG7BPkJsgmAf3l37KwOsQPc ZgqSsR79SBifXV3XcrXPev1W1ou9CnBIgEkbg7/YRP7VgNugO/q5QDccD/3BEPn3Zq4F 4fvbjDBsTagTWQvml2hA56TIHTzBNhir6+ZJ5UTRfo3j1kHK1buXJg7z3cM9Vey8fD6t m/0A== X-Gm-Message-State: AC+VfDwfRQe89EDP6/Eoz190sZGFtyoIjAMJZLKBRNkB+pYaceXhXEO9 RV9fd2el3g6SDMVJBUV0x1d3cwGB+J8= X-Google-Smtp-Source: ACHHUZ4XzFUe54bMOk0YomRIYK7gIFOvGZJcs0BNUJms0iw+xNxthUc2DBXatPOLdbaSXUrEDjKwUQ== X-Received: by 2002:a2e:9d4e:0:b0:2b4:67e0:4ce0 with SMTP id y14-20020a2e9d4e000000b002b467e04ce0mr18407294ljj.44.1687981935148; Wed, 28 Jun 2023 12:52:15 -0700 (PDT) Received: from archlinux.. (dynamic-077-191-074-208.77.191.pool.telefonica.de. [77.191.74.208]) by smtp.gmail.com with ESMTPSA id ec10-20020a170906b6ca00b00982be08a9besm6142817ejb.172.2023.06.28.12.52.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jun 2023 12:52:14 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , "Michael S. Tsirkin" , Marcel Apfelbaum , Richard Henderson , Paolo Bonzini , Bernhard Beschow , Igor Mammedov , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 03/16] hw/pci-host/q35: Initialize PCMachineState::bus in board code Date: Wed, 28 Jun 2023 21:51:51 +0200 Message-ID: <20230628195204.1241-4-shentey@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230628195204.1241-1-shentey@gmail.com> References: <20230628195204.1241-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::230; envelope-from=shentey@gmail.com; helo=mail-lj1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The Q35 PCI host currently sets the PC machine's PCI bus attribute through global state, thereby assuming the machine to be a PC machine. The Q35 machine code already holds on to Q35's pci bus attribute, so can easily set its own property while preserving encapsulation. Signed-off-by: Bernhard Beschow Reviewed-by: Igor Mammedov Reviewed-by: Philippe Mathieu-Daudé --- hw/i386/pc_q35.c | 4 +++- hw/pci-host/q35.c | 1 - 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index d9f3764184..4edc0b35f4 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -230,10 +230,12 @@ static void pc_q35_init(MachineState *machine) x86ms->below_4g_mem_size, NULL); object_property_set_int(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, x86ms->above_4g_mem_size, NULL); + sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); /* pci */ - sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); host_bus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0")); + pcms->bus = host_bus; + /* create ISA bus */ lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), true, TYPE_ICH9_LPC_DEVICE); diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 84137b9ad9..0604464074 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -66,7 +66,6 @@ static void q35_host_realize(DeviceState *dev, Error **errp) s->mch.pci_address_space, s->mch.address_space_io, 0, TYPE_PCIE_BUS); - PC_MACHINE(qdev_get_machine())->bus = pci->bus; pci->bypass_iommu = PC_MACHINE(qdev_get_machine())->default_bus_bypass_iommu; qdev_realize(DEVICE(&s->mch), BUS(pci->bus), &error_fatal); From patchwork Wed Jun 28 19:51:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1801247 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=iNk9AerB; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Qrshb617Jz20Xg for ; Thu, 29 Jun 2023 05:53:35 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qEbDE-0004hQ-64; Wed, 28 Jun 2023 15:52:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qEbDA-0004gM-UX for qemu-devel@nongnu.org; Wed, 28 Jun 2023 15:52:21 -0400 Received: from mail-ej1-x633.google.com ([2a00:1450:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qEbD9-0005iC-F8 for qemu-devel@nongnu.org; Wed, 28 Jun 2023 15:52:20 -0400 Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-986d8332f50so25154266b.0 for ; Wed, 28 Jun 2023 12:52:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687981936; x=1690573936; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3zxuFy1nKO4CI4FNaygwtRvNzJbOGIkhIVlB0FND1xI=; b=iNk9AerB1EuR7lMgwcmm81Z/3vVFueV6R0Ojb5oQgjTczIPhVl3PmrTBesMyU17MJF AFrAX6iEtu1Ni4U7nYUfrELKJnrItqUGbbtRaoY/pywbiQELK+nES/swA2qOGw7t+omF PTa1szS8JmQjdtb7JuaMG2VGhEyYTx51aVEN0VhhtIBQ+cTxpZKyFHm6wgpYvPWlhw7v CVIXHHlbndOSLME4Ojwi4IBjAS7qFkPFGvDg04zu0YxSCmfQ6xYsUL6/DovsL5h1DLXt VFLE2D5Or24Ccenu6+6oMXRT3U1xDdkhz5uq2jqaTb4wRlsOuGZnMxFzvv1x//X/yP+U +Rcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687981936; x=1690573936; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3zxuFy1nKO4CI4FNaygwtRvNzJbOGIkhIVlB0FND1xI=; b=Z4EGX88r+LVkn5FzSmcc+xmSJiBkUhfKiEwp5dC58Q7kJYtUCGq/HN+7ENjAtF0oLq ZXOv5r6oZtDqupLlnROpLb66QQwHYbELKPgi2/lybiot8e4JIFzoXKNeoEmpLIZ02gRQ wK5yLLEoYyxZ6upTnPUsARp8CMVWbuiql9owVCHT3kvutzQsjTjy8z5hylBCi2cEEnbl HIOgVEnYMIuW3co6a+ebKhlD8azpxhlIdUKOvFynvhauTuf64g9H5TzTusjbI+VYAoon 5ErLj3o2clN+CylSVj4Ldnh3II1xG2Algl708XfwOoJWKp/4gVyB0CgMcmg9aJ9hTb/l tKDg== X-Gm-Message-State: AC+VfDzkvF+ICM7fxArvXDIWxI6Y14QYe0GtL/MM6cR3C3dQF/jep9iZ iz9O6Wht1XxkMPVhXERv8os3/Dzuukc= X-Google-Smtp-Source: ACHHUZ431JrQQMgBSIZJcOVcHnwOtvvMiYgS8LSLFoGfl0VoHsYQ1r6d83AONOucJaN2BJ1tbFA0iA== X-Received: by 2002:a17:906:3c06:b0:991:e17c:f8fa with SMTP id h6-20020a1709063c0600b00991e17cf8famr5059546ejg.61.1687981936341; Wed, 28 Jun 2023 12:52:16 -0700 (PDT) Received: from archlinux.. (dynamic-077-191-074-208.77.191.pool.telefonica.de. [77.191.74.208]) by smtp.gmail.com with ESMTPSA id ec10-20020a170906b6ca00b00982be08a9besm6142817ejb.172.2023.06.28.12.52.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jun 2023 12:52:16 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , "Michael S. Tsirkin" , Marcel Apfelbaum , Richard Henderson , Paolo Bonzini , Bernhard Beschow , Igor Mammedov Subject: [PATCH v2 04/16] hw/pci/pci_host: Introduce PCI_HOST_BYPASS_IOMMU macro Date: Wed, 28 Jun 2023 21:51:52 +0200 Message-ID: <20230628195204.1241-5-shentey@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230628195204.1241-1-shentey@gmail.com> References: <20230628195204.1241-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=shentey@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Introduce a macro to avoid copy and pasting strings which can easily cause typos. Suggested-by: Michael S. Tsirkin Signed-off-by: Bernhard Beschow Reviewed-by: Igor Mammedov --- include/hw/pci/pci_host.h | 2 ++ hw/pci/pci_host.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/include/hw/pci/pci_host.h b/include/hw/pci/pci_host.h index c6f4eb4585..e52d8ec2cd 100644 --- a/include/hw/pci/pci_host.h +++ b/include/hw/pci/pci_host.h @@ -31,6 +31,8 @@ #include "hw/sysbus.h" #include "qom/object.h" +#define PCI_HOST_BYPASS_IOMMU "bypass-iommu" + #define TYPE_PCI_HOST_BRIDGE "pci-host-bridge" OBJECT_DECLARE_TYPE(PCIHostState, PCIHostBridgeClass, PCI_HOST_BRIDGE) diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c index dfd185bbb4..7af8afdcbe 100644 --- a/hw/pci/pci_host.c +++ b/hw/pci/pci_host.c @@ -232,7 +232,7 @@ const VMStateDescription vmstate_pcihost = { static Property pci_host_properties_common[] = { DEFINE_PROP_BOOL("x-config-reg-migration-enabled", PCIHostState, mig_enabled, true), - DEFINE_PROP_BOOL("bypass-iommu", PCIHostState, bypass_iommu, false), + DEFINE_PROP_BOOL(PCI_HOST_BYPASS_IOMMU, PCIHostState, bypass_iommu, false), DEFINE_PROP_END_OF_LIST(), }; From patchwork Wed Jun 28 19:51:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1801258 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=ZC/Xsx5/; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QrskB5xx6z20Xg for ; Thu, 29 Jun 2023 05:54:58 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qEbDI-0004j6-50; Wed, 28 Jun 2023 15:52:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qEbDB-0004gQ-Ce for qemu-devel@nongnu.org; Wed, 28 Jun 2023 15:52:21 -0400 Received: from mail-lj1-x22c.google.com ([2a00:1450:4864:20::22c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qEbD9-0005iL-P6 for qemu-devel@nongnu.org; Wed, 28 Jun 2023 15:52:21 -0400 Received: by mail-lj1-x22c.google.com with SMTP id 38308e7fff4ca-2b6a152a933so3318611fa.1 for ; Wed, 28 Jun 2023 12:52:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687981938; x=1690573938; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rtJ3y6eIvCQ3GWIbAZbSOrnzKk4wFNnFByJB8omAiJU=; b=ZC/Xsx5/QQOSSWgdWPF/3jl6ZZXO7ysNyR7PaPM4w1GbIvWcUrMIxRCHMO+5aBKW1J IBYiKDlzY/JIsNLmsgzI10AJqUZD3xmWHnnHD1S9ag9XRKpFmmrp3/b9RQ/nUywcTdwV qn4agobHIYL2x2IgwyYQ59OzNiAnPLncOMnZBy9jvwnY9MxraSf9Xzj3of5tY7b2oL8v Q1Mu7IeD2W/rroHIsDMgOyUtSDQOEj21qeYkqcuOGhpG+jBTn21z0sw2eduQjdEJpSa6 3EJgdahxPRgvuhydsQ2fitllyGMaVWYjxCBZbFXs39jcO0GKa7NcOkr310MGGhLYrI1C XpPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687981938; x=1690573938; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rtJ3y6eIvCQ3GWIbAZbSOrnzKk4wFNnFByJB8omAiJU=; b=U1NbswwjaeO7Wo5olJlSuv1IL0wqarEgyIbn5lBmMEaTg7nmMRHxZcijwndBv59fjx 3DHEahauufi+VS0TEVRJdLKzFjaFG1fyaxC/sOZvhk7bdqujta/e9gE75IsLm6sB1xlj rcJE1H3F11QqrEwLNdlk5+crylFK5WUC1jNuvfjAizoPVHcifJ/vSEAF9FJWWD3nChXX beSEj5d8y1RyxW57GPWCnnLkMsDlxx9rGqEvlyLBjV73PTzF/5ZPsDhqgS0E6lu7ACP/ ESWQbllfpJavyuIGIm8lO7ofo0rEt7uiQFclxMMNg2RyTKpgv5x3rk40OsHkPui9vVdL V59A== X-Gm-Message-State: AC+VfDwVvLyY8eRar3QaODbK7c2pl0uWGCmQaq8x9D1x79XR3xEY7ILc MZz7+wfdYlMAr9SEspIvIYFWEFp9/o0= X-Google-Smtp-Source: ACHHUZ5LnvxeG3A+9dPam1D2a0NQlXIQSXqx7QKUujZZfDMC/xoKzs/pQt7SUu8aQ3nJkqH21ryphQ== X-Received: by 2002:a2e:8443:0:b0:2b1:edfe:8171 with SMTP id u3-20020a2e8443000000b002b1edfe8171mr21950229ljh.36.1687981937707; Wed, 28 Jun 2023 12:52:17 -0700 (PDT) Received: from archlinux.. (dynamic-077-191-074-208.77.191.pool.telefonica.de. [77.191.74.208]) by smtp.gmail.com with ESMTPSA id ec10-20020a170906b6ca00b00982be08a9besm6142817ejb.172.2023.06.28.12.52.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jun 2023 12:52:17 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , "Michael S. Tsirkin" , Marcel Apfelbaum , Richard Henderson , Paolo Bonzini , Bernhard Beschow , Igor Mammedov , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 05/16] hw/pci-host/q35: Initialize PCI_HOST_BYPASS_IOMMU property from board code Date: Wed, 28 Jun 2023 21:51:53 +0200 Message-ID: <20230628195204.1241-6-shentey@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230628195204.1241-1-shentey@gmail.com> References: <20230628195204.1241-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22c; envelope-from=shentey@gmail.com; helo=mail-lj1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The Q35 PCI host already has a PCI_HOST_BYPASS_IOMMU property. However, the host initializes this property itself by accessing global machine state, thereby assuming it to be a PC machine. Avoid this by having board code set this property. Signed-off-by: Bernhard Beschow Reviewed-by: Igor Mammedov Reviewed-by: Philippe Mathieu-Daudé --- hw/i386/pc_q35.c | 2 ++ hw/pci-host/q35.c | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 4edc0b35f4..852250e8cb 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -230,6 +230,8 @@ static void pc_q35_init(MachineState *machine) x86ms->below_4g_mem_size, NULL); object_property_set_int(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, x86ms->above_4g_mem_size, NULL); + object_property_set_bool(phb, PCI_HOST_BYPASS_IOMMU, + pcms->default_bus_bypass_iommu, NULL); sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); /* pci */ diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 0604464074..d2830cee34 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -66,8 +66,7 @@ static void q35_host_realize(DeviceState *dev, Error **errp) s->mch.pci_address_space, s->mch.address_space_io, 0, TYPE_PCIE_BUS); - pci->bypass_iommu = - PC_MACHINE(qdev_get_machine())->default_bus_bypass_iommu; + qdev_realize(DEVICE(&s->mch), BUS(pci->bus), &error_fatal); } From patchwork Wed Jun 28 19:51:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1801249 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=dHQfj8xZ; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Qrsht3Cj7z20Xg for ; Thu, 29 Jun 2023 05:53:50 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qEbDJ-0004jc-0Q; Wed, 28 Jun 2023 15:52:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qEbDC-0004gr-9d for qemu-devel@nongnu.org; Wed, 28 Jun 2023 15:52:22 -0400 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qEbDA-0005iO-Mt for qemu-devel@nongnu.org; Wed, 28 Jun 2023 15:52:22 -0400 Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-991fee3a6b1so25188666b.0 for ; Wed, 28 Jun 2023 12:52:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687981939; x=1690573939; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fWlnycR5wJyTdbj8DEeaQ9aaDr9hN9D3c5m0fZQj8MU=; b=dHQfj8xZfVNPNi67NDDtMr6ztg98xEwGKlej5ZICK/2ijaI9VUqgtDvwatQm/8PcFX ekPJZUed90DuG8BX3JfBMhPCv7mBx0WEA9IZjgUEfVMkIaXnIy9wYsEEcAUfGDxbeAqH P1X1T411rAucl0HroOvDECsnNMLxQbU+O+6gwPY4Bn9m9lVxsnmO8AUJEmOXr5foXqxi rB3iDWdztNBQTkMlcEj1t08i35Okh4PokAl8RgofPO2XnpAuvV7VSx/Q4S9YOjdXXMC1 6eZka3ep/JIyyukUmwFfOncOtzN27FkmSWDcTyJAn4qW3pcONgvT4dOnRwJdNDOayd/t HBcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687981939; x=1690573939; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fWlnycR5wJyTdbj8DEeaQ9aaDr9hN9D3c5m0fZQj8MU=; b=FUgZYwzPKUXIW8B2nkrp75xDyzYQLIWgKLGj2ui3CMwcIlir77FI1BY9ly1cZJ51V5 gwjhnL6ypOeWyAcd2OTSx2dmuc+NYXKKbjOGoejvRoElqwkIun3vDM2XoKcUqyFstbe+ djlwE/8GV83IcdJLw2HOKioK5NMa0mcBfOT7e6R5KIWJcPFIzl5+JHLNkRiZ21UViYSd IEizs4oEXMguj86qhhAAupR/w06H+DH1zrRDQ4MmdfdeoGjfapk5z5BzQ7hXJ5lVrCGR kkvKEiQWOx2Ymhoo5wqkzq6sYGSEGZAyqhSk977pUiZL3814bqbkog9eSwEKI08nYtGY h6ig== X-Gm-Message-State: AC+VfDxsPRDH1mFwkVXX+jCCMPBp8HD3kQ4dC5PGk/W5UxU2pPBM0k8e 0Mw4beXOfuyen4u54JAa29Xdlcq4k9s= X-Google-Smtp-Source: ACHHUZ52DBeQ2cjjNsTmbdGi5j4ZEZnDL4RR6VsqkFGnT7bgJOZ6cDIPvUh+lZB6J7vtECx0oS448g== X-Received: by 2002:a17:907:3e16:b0:978:a186:464f with SMTP id hp22-20020a1709073e1600b00978a186464fmr35930860ejc.39.1687981938712; Wed, 28 Jun 2023 12:52:18 -0700 (PDT) Received: from archlinux.. (dynamic-077-191-074-208.77.191.pool.telefonica.de. [77.191.74.208]) by smtp.gmail.com with ESMTPSA id ec10-20020a170906b6ca00b00982be08a9besm6142817ejb.172.2023.06.28.12.52.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jun 2023 12:52:18 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , "Michael S. Tsirkin" , Marcel Apfelbaum , Richard Henderson , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 06/16] hw/pci-host/q35: Make some property name macros reusable by i440fx Date: Wed, 28 Jun 2023 21:51:54 +0200 Message-ID: <20230628195204.1241-7-shentey@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230628195204.1241-1-shentey@gmail.com> References: <20230628195204.1241-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=shentey@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Bernhard Beschow --- include/hw/i386/pc.h | 4 ++++ include/hw/pci-host/q35.h | 5 ----- hw/i386/pc_q35.c | 8 ++++---- hw/pci-host/q35.c | 8 ++++---- 4 files changed, 12 insertions(+), 13 deletions(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 6eec0fc51d..c34c698cdd 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -146,6 +146,10 @@ void pc_acpi_smi_interrupt(void *opaque, int irq, int level); void pc_guest_info_init(PCMachineState *pcms); +#define PCI_HOST_PROP_RAM_MEM "ram-mem" +#define PCI_HOST_PROP_PCI_MEM "pci-mem" +#define PCI_HOST_PROP_SYSTEM_MEM "system-mem" +#define PCI_HOST_PROP_IO_MEM "io-mem" #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start" #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end" #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start" diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index e89329c51e..1d98bbfe0d 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -74,11 +74,6 @@ struct Q35PCIHost { * gmch part */ -#define MCH_HOST_PROP_RAM_MEM "ram-mem" -#define MCH_HOST_PROP_PCI_MEM "pci-mem" -#define MCH_HOST_PROP_SYSTEM_MEM "system-mem" -#define MCH_HOST_PROP_IO_MEM "io-mem" - /* PCI configuration */ #define MCH_HOST_BRIDGE "MCH" diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 852250e8cb..02dd274276 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -218,13 +218,13 @@ static void pc_q35_init(MachineState *machine) pc_memory_init(pcms, system_memory, rom_memory, pci_hole64_size); object_property_add_child(OBJECT(machine), "q35", phb); - object_property_set_link(phb, MCH_HOST_PROP_RAM_MEM, + object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, OBJECT(machine->ram), NULL); - object_property_set_link(phb, MCH_HOST_PROP_PCI_MEM, + object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM, OBJECT(pci_memory), NULL); - object_property_set_link(phb, MCH_HOST_PROP_SYSTEM_MEM, + object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM, OBJECT(system_memory), NULL); - object_property_set_link(phb, MCH_HOST_PROP_IO_MEM, + object_property_set_link(phb, PCI_HOST_PROP_IO_MEM, OBJECT(system_io), NULL); object_property_set_int(phb, PCI_HOST_BELOW_4G_MEM_SIZE, x86ms->below_4g_mem_size, NULL); diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index d2830cee34..91c46df9ae 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -240,19 +240,19 @@ static void q35_host_initfn(Object *obj) object_property_add_uint64_ptr(obj, PCIE_HOST_MCFG_SIZE, &pehb->size, OBJ_PROP_FLAG_READ); - object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, + object_property_add_link(obj, PCI_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, (Object **) &s->mch.ram_memory, qdev_prop_allow_set_link_before_realize, 0); - object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, + object_property_add_link(obj, PCI_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, (Object **) &s->mch.pci_address_space, qdev_prop_allow_set_link_before_realize, 0); - object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, + object_property_add_link(obj, PCI_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, (Object **) &s->mch.system_memory, qdev_prop_allow_set_link_before_realize, 0); - object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, + object_property_add_link(obj, PCI_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, (Object **) &s->mch.address_space_io, qdev_prop_allow_set_link_before_realize, 0); } From patchwork Wed Jun 28 19:51:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1801248 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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(dynamic-077-191-074-208.77.191.pool.telefonica.de. [77.191.74.208]) by smtp.gmail.com with ESMTPSA id ec10-20020a170906b6ca00b00982be08a9besm6142817ejb.172.2023.06.28.12.52.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jun 2023 12:52:19 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , "Michael S. Tsirkin" , Marcel Apfelbaum , Richard Henderson , Paolo Bonzini , Bernhard Beschow , Igor Mammedov , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 07/16] hw/pci-host/i440fx: Replace magic values by existing constants Date: Wed, 28 Jun 2023 21:51:55 +0200 Message-ID: <20230628195204.1241-8-shentey@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230628195204.1241-1-shentey@gmail.com> References: <20230628195204.1241-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=shentey@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Bernhard Beschow Reviewed-by: Igor Mammedov Reviewed-by: Philippe Mathieu-Daudé --- hw/pci-host/i440fx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c index 61e7b97ff4..daa4d11104 100644 --- a/hw/pci-host/i440fx.c +++ b/hw/pci-host/i440fx.c @@ -277,8 +277,8 @@ PCIBus *i440fx_init(const char *pci_type, /* if *disabled* show SMRAM to all CPUs */ memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region", - f->pci_address_space, 0xa0000, 0x20000); - memory_region_add_subregion_overlap(f->system_memory, 0xa0000, + f->pci_address_space, SMRAM_C_BASE, SMRAM_C_SIZE); + memory_region_add_subregion_overlap(f->system_memory, SMRAM_C_BASE, &f->smram_region, 1); memory_region_set_enabled(&f->smram_region, true); @@ -286,9 +286,9 @@ PCIBus *i440fx_init(const char *pci_type, memory_region_init(&f->smram, OBJECT(d), "smram", 4 * GiB); memory_region_set_enabled(&f->smram, true); memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low", - f->ram_memory, 0xa0000, 0x20000); + f->ram_memory, SMRAM_C_BASE, SMRAM_C_SIZE); memory_region_set_enabled(&f->low_smram, true); - memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram); + memory_region_add_subregion(&f->smram, SMRAM_C_BASE, &f->low_smram); object_property_add_const_link(qdev_get_machine(), "smram", OBJECT(&f->smram)); From patchwork Wed Jun 28 19:51:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1801252 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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(dynamic-077-191-074-208.77.191.pool.telefonica.de. [77.191.74.208]) by smtp.gmail.com with ESMTPSA id ec10-20020a170906b6ca00b00982be08a9besm6142817ejb.172.2023.06.28.12.52.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jun 2023 12:52:20 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , "Michael S. Tsirkin" , Marcel Apfelbaum , Richard Henderson , Paolo Bonzini , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 08/16] hw/pci-host/i440fx: Have common names for some local variables Date: Wed, 28 Jun 2023 21:51:56 +0200 Message-ID: <20230628195204.1241-9-shentey@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230628195204.1241-1-shentey@gmail.com> References: <20230628195204.1241-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=shentey@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org `PCIHostState` is often referred to as `phb`, own device state usually as `s`. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/pci-host/i440fx.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c index daa4d11104..88beaf99c4 100644 --- a/hw/pci-host/i440fx.c +++ b/hw/pci-host/i440fx.c @@ -205,28 +205,28 @@ static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v, static void i440fx_pcihost_initfn(Object *obj) { - PCIHostState *s = PCI_HOST_BRIDGE(obj); + PCIHostState *phb = PCI_HOST_BRIDGE(obj); - memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s, + memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, "pci-conf-idx", 4); - memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s, + memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, "pci-conf-data", 4); } static void i440fx_pcihost_realize(DeviceState *dev, Error **errp) { - PCIHostState *s = PCI_HOST_BRIDGE(dev); + PCIHostState *phb = PCI_HOST_BRIDGE(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - memory_region_add_subregion(s->bus->address_space_io, 0xcf8, &s->conf_mem); + memory_region_add_subregion(phb->bus->address_space_io, 0xcf8, &phb->conf_mem); sysbus_init_ioports(sbd, 0xcf8, 4); - memory_region_add_subregion(s->bus->address_space_io, 0xcfc, &s->data_mem); + memory_region_add_subregion(phb->bus->address_space_io, 0xcfc, &phb->data_mem); sysbus_init_ioports(sbd, 0xcfc, 4); /* register i440fx 0xcf8 port as coalesced pio */ - memory_region_set_flush_coalesced(&s->data_mem); - memory_region_add_coalescing(&s->conf_mem, 0, 4); + memory_region_set_flush_coalesced(&phb->data_mem); + memory_region_add_coalescing(&phb->conf_mem, 0, 4); } static void i440fx_realize(PCIDevice *dev, Error **errp) @@ -248,17 +248,16 @@ PCIBus *i440fx_init(const char *pci_type, MemoryRegion *pci_address_space, MemoryRegion *ram_memory) { + I440FXState *s = I440FX_PCI_HOST_BRIDGE(dev); + PCIHostState *phb = PCI_HOST_BRIDGE(dev); PCIBus *b; PCIDevice *d; - PCIHostState *s; PCII440FXState *f; unsigned i; - I440FXState *i440fx; - s = PCI_HOST_BRIDGE(dev); b = pci_root_bus_new(dev, NULL, pci_address_space, address_space_io, 0, TYPE_PCI_BUS); - s->bus = b; + phb->bus = b; object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev)); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -268,8 +267,7 @@ PCIBus *i440fx_init(const char *pci_type, f->pci_address_space = pci_address_space; f->ram_memory = ram_memory; - i440fx = I440FX_PCI_HOST_BRIDGE(dev); - range_set_bounds(&i440fx->pci_hole, below_4g_mem_size, + range_set_bounds(&s->pci_hole, below_4g_mem_size, IO_APIC_DEFAULT_ADDRESS - 1); /* setup pci memory mapping */ From patchwork Wed Jun 28 19:51:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1801255 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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(dynamic-077-191-074-208.77.191.pool.telefonica.de. [77.191.74.208]) by smtp.gmail.com with ESMTPSA id ec10-20020a170906b6ca00b00982be08a9besm6142817ejb.172.2023.06.28.12.52.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jun 2023 12:52:21 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , "Michael S. Tsirkin" , Marcel Apfelbaum , Richard Henderson , Paolo Bonzini , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 09/16] hw/pci-host/i440fx: Move i440fx_realize() into PCII440FXState section Date: Wed, 28 Jun 2023 21:51:57 +0200 Message-ID: <20230628195204.1241-10-shentey@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230628195204.1241-1-shentey@gmail.com> References: <20230628195204.1241-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=shentey@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org i440fx_realize() realizes the PCI device inside the host bridge (PCII440FXState), but is implemented between i440fx_pcihost_realize() and i440fx_init() which deal with the host bridge itself (I440FXState). Since we want to append i440fx_init() to i440fx_pcihost_realize() later let's move i440fx_realize() out of the way. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/pci-host/i440fx.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c index 88beaf99c4..9df4688b2e 100644 --- a/hw/pci-host/i440fx.c +++ b/hw/pci-host/i440fx.c @@ -65,6 +65,15 @@ struct I440FXState { */ #define I440FX_COREBOOT_RAM_SIZE 0x57 +static void i440fx_realize(PCIDevice *dev, Error **errp) +{ + dev->config[I440FX_SMRAM] = 0x02; + + if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) { + warn_report("i440fx doesn't support emulated iommu"); + } +} + static void i440fx_update_memory_mappings(PCII440FXState *d) { int i; @@ -229,15 +238,6 @@ static void i440fx_pcihost_realize(DeviceState *dev, Error **errp) memory_region_add_coalescing(&phb->conf_mem, 0, 4); } -static void i440fx_realize(PCIDevice *dev, Error **errp) -{ - dev->config[I440FX_SMRAM] = 0x02; - - if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) { - warn_report("i440fx doesn't support emulated iommu"); - } -} - PCIBus *i440fx_init(const char *pci_type, DeviceState *dev, MemoryRegion *address_space_mem, From patchwork Wed Jun 28 19:51:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1801257 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=L1UlLDKP; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Qrsk84C90z20Xg for ; Thu, 29 Jun 2023 05:54:56 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qEbDI-0004jC-OJ; Wed, 28 Jun 2023 15:52:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qEbDH-0004ip-6V for qemu-devel@nongnu.org; Wed, 28 Jun 2023 15:52:27 -0400 Received: from mail-lj1-x22c.google.com ([2a00:1450:4864:20::22c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qEbDF-0005jJ-E5 for qemu-devel@nongnu.org; Wed, 28 Jun 2023 15:52:26 -0400 Received: by mail-lj1-x22c.google.com with SMTP id 38308e7fff4ca-2b69f1570b2so3698311fa.0 for ; Wed, 28 Jun 2023 12:52:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687981943; x=1690573943; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WiFO595PbyvHK55Z+oXifs8Sd0sd0acHPDSBWvnuw9s=; b=L1UlLDKPd7NqZty+eYZZ3GDaWRfUwW6WSS97zQpxhcz2u2PKpQ3jQRSGNL+eOtp/aP cka0+vzIpOxfA0qyum3UUbmff5Jl4BhNici0VvL1RE9mOmSn2HUicdsKKZCM1KbzLc+j +fRnEXxmCUp8Z2Ju+b4w+Sde/esliihDkIAGubUylC6LGxRfrBwrSqa1qdlpwuN98fPX L//WmXLUveYNfMR0uH95Rh+MHJvBUVlS2x9izbQ0PM4rqZRWzMJqm3KXLSiw3lh4Zpv4 /HNKlTy0OQgVkKjNvKRGanmkpMcEM0rFGszbhocFBKxaS74vOc7zLRFFdW28RLO6+RSc HosA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687981943; x=1690573943; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WiFO595PbyvHK55Z+oXifs8Sd0sd0acHPDSBWvnuw9s=; b=RHX11evkpNPr9eBZqwGhW4UufI89SuThGknLxeHYohsEA8t4jg4PLfzPIhQyftGnsL 5ryIMcQRTpsy9IcFnkVv+r2wWZAcYmEivGAarMnhRgXQb98Dv5IMIyhJMK8kp68lFCM2 dXeCOdNns+cQksjFsAZ+Yrt+EfLm1sJMlF+WprJCxEUETlTE2XEwi40YRfXgl+xWz7Xu 8oUcGXKPsqvEc4qghpqTwcWEwAWd/AhC4WJPNJK/uyLZTL4dqkOhfmub6qDIa3WQ+uEC G22eSdz3Gim+/cgxPSbx2JTF7vZQvkaw5SGlPC1+c6bn027vgXZQCGA7UxAktdfeNn9I 9NXg== X-Gm-Message-State: AC+VfDxvML1qF8IMjz79qCEC664MWR5s/PYXfHD2ZK4HcMay4iQKoD4T 6YiPhd2tDkb7XPWL05+G29vIKs2DgAA= X-Google-Smtp-Source: ACHHUZ4kj94VZRo41x56imYiVk7FGchoA3dnFGcld5SdcNxbKZcp/xJKcJsi5Md+OjmW+GN4D9vl7Q== X-Received: by 2002:a2e:8089:0:b0:2b6:b88b:6689 with SMTP id i9-20020a2e8089000000b002b6b88b6689mr3429637ljg.22.1687981943301; Wed, 28 Jun 2023 12:52:23 -0700 (PDT) Received: from archlinux.. (dynamic-077-191-074-208.77.191.pool.telefonica.de. [77.191.74.208]) by smtp.gmail.com with ESMTPSA id ec10-20020a170906b6ca00b00982be08a9besm6142817ejb.172.2023.06.28.12.52.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jun 2023 12:52:22 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , "Michael S. Tsirkin" , Marcel Apfelbaum , Richard Henderson , Paolo Bonzini , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 10/16] hw/pci-host/i440fx: Make MemoryRegion pointers accessible as properties Date: Wed, 28 Jun 2023 21:51:58 +0200 Message-ID: <20230628195204.1241-11-shentey@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230628195204.1241-1-shentey@gmail.com> References: <20230628195204.1241-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22c; envelope-from=shentey@gmail.com; helo=mail-lj1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The goal is to eliminate i440fx_init() which is a legacy init function. This neccessitates the memory regions to be properties, like in Q35, which will be assigned in board code. Since i440fx needs different PCI devices in Xen mode, and since i440fx shall be self-contained, the PCI device will be created during realization of the host. Thus the pointers need to be moved to the host structure to be usable as properties. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- include/hw/pci-host/i440fx.h | 3 --- hw/pci-host/i440fx.c | 42 +++++++++++++++++++++++++----------- 2 files changed, 30 insertions(+), 15 deletions(-) diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h index bf57216c78..e3a550021e 100644 --- a/include/hw/pci-host/i440fx.h +++ b/include/hw/pci-host/i440fx.h @@ -25,9 +25,6 @@ struct PCII440FXState { PCIDevice parent_obj; /*< public >*/ - MemoryRegion *system_memory; - MemoryRegion *pci_address_space; - MemoryRegion *ram_memory; PAMMemoryRegion pam_regions[PAM_REGIONS_COUNT]; MemoryRegion smram_region; MemoryRegion smram, low_smram; diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c index 9df4688b2e..efc940ba12 100644 --- a/hw/pci-host/i440fx.c +++ b/hw/pci-host/i440fx.c @@ -47,6 +47,10 @@ OBJECT_DECLARE_SIMPLE_TYPE(I440FXState, I440FX_PCI_HOST_BRIDGE) struct I440FXState { PCIHostState parent_obj; + + MemoryRegion *system_memory; + MemoryRegion *pci_address_space; + MemoryRegion *ram_memory; Range pci_hole; uint64_t pci_hole64_size; bool pci_hole64_fix; @@ -214,12 +218,25 @@ static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v, static void i440fx_pcihost_initfn(Object *obj) { + I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); PCIHostState *phb = PCI_HOST_BRIDGE(obj); memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, "pci-conf-idx", 4); memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, "pci-conf-data", 4); + + object_property_add_link(obj, PCI_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, + (Object **) &s->ram_memory, + qdev_prop_allow_set_link_before_realize, 0); + + object_property_add_link(obj, PCI_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, + (Object **) &s->pci_address_space, + qdev_prop_allow_set_link_before_realize, 0); + + object_property_add_link(obj, PCI_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, + (Object **) &s->system_memory, + qdev_prop_allow_set_link_before_realize, 0); } static void i440fx_pcihost_realize(DeviceState *dev, Error **errp) @@ -255,7 +272,11 @@ PCIBus *i440fx_init(const char *pci_type, PCII440FXState *f; unsigned i; - b = pci_root_bus_new(dev, NULL, pci_address_space, + s->system_memory = address_space_mem; + s->pci_address_space = pci_address_space; + s->ram_memory = ram_memory; + + b = pci_root_bus_new(dev, NULL, s->pci_address_space, address_space_io, 0, TYPE_PCI_BUS); phb->bus = b; object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev)); @@ -263,20 +284,17 @@ PCIBus *i440fx_init(const char *pci_type, d = pci_create_simple(b, 0, pci_type); f = I440FX_PCI_DEVICE(d); - f->system_memory = address_space_mem; - f->pci_address_space = pci_address_space; - f->ram_memory = ram_memory; range_set_bounds(&s->pci_hole, below_4g_mem_size, IO_APIC_DEFAULT_ADDRESS - 1); /* setup pci memory mapping */ - pc_pci_as_mapping_init(f->system_memory, f->pci_address_space); + pc_pci_as_mapping_init(s->system_memory, s->pci_address_space); /* if *disabled* show SMRAM to all CPUs */ memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region", - f->pci_address_space, SMRAM_C_BASE, SMRAM_C_SIZE); - memory_region_add_subregion_overlap(f->system_memory, SMRAM_C_BASE, + s->pci_address_space, SMRAM_C_BASE, SMRAM_C_SIZE); + memory_region_add_subregion_overlap(s->system_memory, SMRAM_C_BASE, &f->smram_region, 1); memory_region_set_enabled(&f->smram_region, true); @@ -284,17 +302,17 @@ PCIBus *i440fx_init(const char *pci_type, memory_region_init(&f->smram, OBJECT(d), "smram", 4 * GiB); memory_region_set_enabled(&f->smram, true); memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low", - f->ram_memory, SMRAM_C_BASE, SMRAM_C_SIZE); + s->ram_memory, SMRAM_C_BASE, SMRAM_C_SIZE); memory_region_set_enabled(&f->low_smram, true); memory_region_add_subregion(&f->smram, SMRAM_C_BASE, &f->low_smram); object_property_add_const_link(qdev_get_machine(), "smram", OBJECT(&f->smram)); - init_pam(&f->pam_regions[0], OBJECT(d), f->ram_memory, f->system_memory, - f->pci_address_space, PAM_BIOS_BASE, PAM_BIOS_SIZE); + init_pam(&f->pam_regions[0], OBJECT(d), s->ram_memory, s->system_memory, + s->pci_address_space, PAM_BIOS_BASE, PAM_BIOS_SIZE); for (i = 0; i < ARRAY_SIZE(f->pam_regions) - 1; ++i) { - init_pam(&f->pam_regions[i + 1], OBJECT(d), f->ram_memory, - f->system_memory, f->pci_address_space, + init_pam(&f->pam_regions[i + 1], OBJECT(d), s->ram_memory, + s->system_memory, s->pci_address_space, PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); } From patchwork Wed Jun 28 19:51:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1801259 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=rj5RKPkL; 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(dynamic-077-191-074-208.77.191.pool.telefonica.de. [77.191.74.208]) by smtp.gmail.com with ESMTPSA id ec10-20020a170906b6ca00b00982be08a9besm6142817ejb.172.2023.06.28.12.52.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jun 2023 12:52:23 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , "Michael S. Tsirkin" , Marcel Apfelbaum , Richard Henderson , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 11/16] hw/pci-host/i440fx: Add PCI_HOST_PROP_IO_MEM property Date: Wed, 28 Jun 2023 21:51:59 +0200 Message-ID: <20230628195204.1241-12-shentey@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230628195204.1241-1-shentey@gmail.com> References: <20230628195204.1241-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=shentey@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Introduce the property in anticipation of QOM'ification; Q35 has the same property. Signed-off-by: Bernhard Beschow --- hw/pci-host/i440fx.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c index efc940ba12..a740d1762b 100644 --- a/hw/pci-host/i440fx.c +++ b/hw/pci-host/i440fx.c @@ -27,7 +27,6 @@ #include "qemu/range.h" #include "hw/i386/pc.h" #include "hw/pci/pci.h" -#include "hw/pci/pci_bus.h" #include "hw/pci/pci_host.h" #include "hw/pci-host/i440fx.h" #include "hw/qdev-properties.h" @@ -49,6 +48,7 @@ struct I440FXState { PCIHostState parent_obj; MemoryRegion *system_memory; + MemoryRegion *io_memory; MemoryRegion *pci_address_space; MemoryRegion *ram_memory; Range pci_hole; @@ -237,17 +237,22 @@ static void i440fx_pcihost_initfn(Object *obj) object_property_add_link(obj, PCI_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, (Object **) &s->system_memory, qdev_prop_allow_set_link_before_realize, 0); + + object_property_add_link(obj, PCI_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, + (Object **) &s->io_memory, + qdev_prop_allow_set_link_before_realize, 0); } static void i440fx_pcihost_realize(DeviceState *dev, Error **errp) { + I440FXState *s = I440FX_PCI_HOST_BRIDGE(dev); PCIHostState *phb = PCI_HOST_BRIDGE(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - memory_region_add_subregion(phb->bus->address_space_io, 0xcf8, &phb->conf_mem); + memory_region_add_subregion(s->io_memory, 0xcf8, &phb->conf_mem); sysbus_init_ioports(sbd, 0xcf8, 4); - memory_region_add_subregion(phb->bus->address_space_io, 0xcfc, &phb->data_mem); + memory_region_add_subregion(s->io_memory, 0xcfc, &phb->data_mem); sysbus_init_ioports(sbd, 0xcfc, 4); /* register i440fx 0xcf8 port as coalesced pio */ @@ -273,11 +278,12 @@ PCIBus *i440fx_init(const char *pci_type, unsigned i; s->system_memory = address_space_mem; + s->io_memory = address_space_io; s->pci_address_space = pci_address_space; s->ram_memory = ram_memory; b = pci_root_bus_new(dev, NULL, s->pci_address_space, - address_space_io, 0, TYPE_PCI_BUS); + s->io_memory, 0, TYPE_PCI_BUS); phb->bus = b; object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev)); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); From patchwork Wed Jun 28 19:52:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1801250 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=RsTnsSRG; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Qrsj31cxPz20Xg for ; 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(dynamic-077-191-074-208.77.191.pool.telefonica.de. [77.191.74.208]) by smtp.gmail.com with ESMTPSA id ec10-20020a170906b6ca00b00982be08a9besm6142817ejb.172.2023.06.28.12.52.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jun 2023 12:52:25 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , "Michael S. Tsirkin" , Marcel Apfelbaum , Richard Henderson , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 12/16] hw/pci-host/i440fx: Add PCI_HOST_{ABOVE, BELOW}_4G_MEM_SIZE properties Date: Wed, 28 Jun 2023 21:52:00 +0200 Message-ID: <20230628195204.1241-13-shentey@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230628195204.1241-1-shentey@gmail.com> References: <20230628195204.1241-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=shentey@gmail.com; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Introduce the properties in anticipation of QOM'ification; Q35 has the same properties. Note that we want to avoid a "ram size" property in the QOM interface since it seems redundant to both properties introduced in this change. Thus the removal of the ram_size parameter. We assume the invariant of both properties to sum up to "ram size" which is already asserted in pc_memory_init(). Under Xen the invariant seems to hold as well, so we now also check it there. Signed-off-by: Bernhard Beschow --- include/hw/pci-host/i440fx.h | 1 - hw/i386/pc_piix.c | 5 ++++- hw/pci-host/i440fx.c | 12 ++++++++++-- 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h index e3a550021e..7e38456ebb 100644 --- a/include/hw/pci-host/i440fx.h +++ b/include/hw/pci-host/i440fx.h @@ -36,7 +36,6 @@ PCIBus *i440fx_init(const char *pci_type, DeviceState *dev, MemoryRegion *address_space_mem, MemoryRegion *address_space_io, - ram_addr_t ram_size, ram_addr_t below_4g_mem_size, ram_addr_t above_4g_mem_size, MemoryRegion *pci_memory, diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index f9947fbc10..87bee368fc 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -227,6 +227,9 @@ static void pc_init1(MachineState *machine, if (!xen_enabled()) { pc_memory_init(pcms, system_memory, rom_memory, hole64_size); } else { + assert(machine->ram_size == x86ms->below_4g_mem_size + + x86ms->above_4g_mem_size); + pc_system_flash_cleanup_unused(pcms); if (machine->kernel_filename != NULL) { /* For xen HVM direct kernel boot, load linux here */ @@ -242,7 +245,7 @@ static void pc_init1(MachineState *machine, pci_bus = i440fx_init(pci_type, i440fx_host, - system_memory, system_io, machine->ram_size, + system_memory, system_io, x86ms->below_4g_mem_size, x86ms->above_4g_mem_size, pci_memory, ram_memory); diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c index a740d1762b..4dd70e68fa 100644 --- a/hw/pci-host/i440fx.c +++ b/hw/pci-host/i440fx.c @@ -52,6 +52,8 @@ struct I440FXState { MemoryRegion *pci_address_space; MemoryRegion *ram_memory; Range pci_hole; + uint64_t below_4g_mem_size; + uint64_t above_4g_mem_size; uint64_t pci_hole64_size; bool pci_hole64_fix; uint32_t short_root_bus; @@ -264,7 +266,6 @@ PCIBus *i440fx_init(const char *pci_type, DeviceState *dev, MemoryRegion *address_space_mem, MemoryRegion *address_space_io, - ram_addr_t ram_size, ram_addr_t below_4g_mem_size, ram_addr_t above_4g_mem_size, MemoryRegion *pci_address_space, @@ -281,6 +282,8 @@ PCIBus *i440fx_init(const char *pci_type, s->io_memory = address_space_io; s->pci_address_space = pci_address_space; s->ram_memory = ram_memory; + s->below_4g_mem_size = below_4g_mem_size; + s->above_4g_mem_size = above_4g_mem_size; b = pci_root_bus_new(dev, NULL, s->pci_address_space, s->io_memory, 0, TYPE_PCI_BUS); @@ -291,7 +294,7 @@ PCIBus *i440fx_init(const char *pci_type, d = pci_create_simple(b, 0, pci_type); f = I440FX_PCI_DEVICE(d); - range_set_bounds(&s->pci_hole, below_4g_mem_size, + range_set_bounds(&s->pci_hole, s->below_4g_mem_size, IO_APIC_DEFAULT_ADDRESS - 1); /* setup pci memory mapping */ @@ -322,6 +325,7 @@ PCIBus *i440fx_init(const char *pci_type, PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); } + ram_addr_t ram_size = s->below_4g_mem_size + s->above_4g_mem_size; ram_size = ram_size / 8 / 1024 / 1024; if (ram_size > 255) { ram_size = 255; @@ -381,6 +385,10 @@ static Property i440fx_props[] = { DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState, pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT), DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0), + DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, I440FXState, + below_4g_mem_size, 0), + DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, I440FXState, + above_4g_mem_size, 0), DEFINE_PROP_BOOL("x-pci-hole64-fix", I440FXState, pci_hole64_fix, true), DEFINE_PROP_END_OF_LIST(), }; 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(dynamic-077-191-074-208.77.191.pool.telefonica.de. [77.191.74.208]) by smtp.gmail.com with ESMTPSA id ec10-20020a170906b6ca00b00982be08a9besm6142817ejb.172.2023.06.28.12.52.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jun 2023 12:52:26 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , "Michael S. Tsirkin" , Marcel Apfelbaum , Richard Henderson , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 13/16] hw/pci-host/i440fx: Add I440FX_HOST_PROP_PCI_TYPE property Date: Wed, 28 Jun 2023 21:52:01 +0200 Message-ID: <20230628195204.1241-14-shentey@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230628195204.1241-1-shentey@gmail.com> References: <20230628195204.1241-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=shentey@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org I440FX needs a different PCI device model if the "igd-passthru" property is enabled. The type name is currently passed as a parameter to i440fx_init(). This parameter will be replaced by a property assignment once i440fx_init() gets resolved. Signed-off-by: Bernhard Beschow --- include/hw/pci-host/i440fx.h | 2 ++ hw/pci-host/i440fx.c | 6 +++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h index 7e38456ebb..2d7bae5a45 100644 --- a/include/hw/pci-host/i440fx.h +++ b/include/hw/pci-host/i440fx.h @@ -15,6 +15,8 @@ #include "hw/pci-host/pam.h" #include "qom/object.h" +#define I440FX_HOST_PROP_PCI_TYPE "pci-type" + #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost" #define TYPE_I440FX_PCI_DEVICE "i440FX" diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c index 4dd70e68fa..e8e66afc11 100644 --- a/hw/pci-host/i440fx.c +++ b/hw/pci-host/i440fx.c @@ -57,6 +57,8 @@ struct I440FXState { uint64_t pci_hole64_size; bool pci_hole64_fix; uint32_t short_root_bus; + + char *pci_type; }; #define I440FX_PAM 0x59 @@ -284,6 +286,7 @@ PCIBus *i440fx_init(const char *pci_type, s->ram_memory = ram_memory; s->below_4g_mem_size = below_4g_mem_size; s->above_4g_mem_size = above_4g_mem_size; + s->pci_type = (char *)pci_type; b = pci_root_bus_new(dev, NULL, s->pci_address_space, s->io_memory, 0, TYPE_PCI_BUS); @@ -291,7 +294,7 @@ PCIBus *i440fx_init(const char *pci_type, object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev)); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - d = pci_create_simple(b, 0, pci_type); + d = pci_create_simple(b, 0, s->pci_type); f = I440FX_PCI_DEVICE(d); range_set_bounds(&s->pci_hole, s->below_4g_mem_size, @@ -390,6 +393,7 @@ static Property i440fx_props[] = { DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, I440FXState, above_4g_mem_size, 0), DEFINE_PROP_BOOL("x-pci-hole64-fix", I440FXState, pci_hole64_fix, true), + DEFINE_PROP_STRING(I440FX_HOST_PROP_PCI_TYPE, I440FXState, pci_type), DEFINE_PROP_END_OF_LIST(), }; From patchwork Wed Jun 28 19:52:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1801254 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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(dynamic-077-191-074-208.77.191.pool.telefonica.de. [77.191.74.208]) by smtp.gmail.com with ESMTPSA id ec10-20020a170906b6ca00b00982be08a9besm6142817ejb.172.2023.06.28.12.52.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jun 2023 12:52:27 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , "Michael S. Tsirkin" , Marcel Apfelbaum , Richard Henderson , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 14/16] hw/pci-host/i440fx: Resolve i440fx_init() Date: Wed, 28 Jun 2023 21:52:02 +0200 Message-ID: <20230628195204.1241-15-shentey@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230628195204.1241-1-shentey@gmail.com> References: <20230628195204.1241-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=shentey@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org i440fx_init() is a legacy init function. The previous patches worked towards TYPE_I440FX_PCI_HOST_BRIDGE to be instantiated the QOM way. Do this now by transforming the parameters passed to i440fx_init() into property assignments. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- include/hw/pci-host/i440fx.h | 10 ---------- hw/i386/pc_piix.c | 30 +++++++++++++++++++++--------- hw/pci-host/i440fx.c | 34 +++++----------------------------- 3 files changed, 26 insertions(+), 48 deletions(-) diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h index 2d7bae5a45..c988f70890 100644 --- a/include/hw/pci-host/i440fx.h +++ b/include/hw/pci-host/i440fx.h @@ -34,14 +34,4 @@ struct PCII440FXState { #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX" -PCIBus *i440fx_init(const char *pci_type, - DeviceState *dev, - MemoryRegion *address_space_mem, - MemoryRegion *address_space_io, - ram_addr_t below_4g_mem_size, - ram_addr_t above_4g_mem_size, - MemoryRegion *pci_memory, - MemoryRegion *ram_memory); - - #endif diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 87bee368fc..1df309b8e2 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -126,7 +126,7 @@ static void pc_init1(MachineState *machine, MemoryRegion *rom_memory; ram_addr_t lowmem; uint64_t hole64_size; - DeviceState *i440fx_host; + Object *i440fx_host; /* * Calculate ram split, for memory below and above 4G. It's a bit @@ -201,8 +201,8 @@ static void pc_init1(MachineState *machine, pci_memory = g_new(MemoryRegion, 1); memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); rom_memory = pci_memory; - i440fx_host = qdev_new(host_type); - hole64_size = object_property_get_uint(OBJECT(i440fx_host), + i440fx_host = OBJECT(qdev_new(host_type)); + hole64_size = object_property_get_uint(i440fx_host, PCI_HOST_PROP_PCI_HOLE64_SIZE, &error_abort); } else { @@ -243,12 +243,24 @@ static void pc_init1(MachineState *machine, PIIX3State *piix3; PCIDevice *pci_dev; - pci_bus = i440fx_init(pci_type, - i440fx_host, - system_memory, system_io, - x86ms->below_4g_mem_size, - x86ms->above_4g_mem_size, - pci_memory, ram_memory); + object_property_add_child(OBJECT(machine), "i440fx", i440fx_host); + object_property_set_link(i440fx_host, PCI_HOST_PROP_RAM_MEM, + OBJECT(ram_memory), &error_fatal); + object_property_set_link(i440fx_host, PCI_HOST_PROP_PCI_MEM, + OBJECT(pci_memory), &error_fatal); + object_property_set_link(i440fx_host, PCI_HOST_PROP_SYSTEM_MEM, + OBJECT(system_memory), &error_fatal); + object_property_set_link(i440fx_host, PCI_HOST_PROP_IO_MEM, + OBJECT(system_io), &error_fatal); + object_property_set_uint(i440fx_host, PCI_HOST_BELOW_4G_MEM_SIZE, + x86ms->below_4g_mem_size, &error_fatal); + object_property_set_uint(i440fx_host, PCI_HOST_ABOVE_4G_MEM_SIZE, + x86ms->above_4g_mem_size, &error_fatal); + object_property_set_str(i440fx_host, I440FX_HOST_PROP_PCI_TYPE, + pci_type, &error_fatal); + sysbus_realize_and_unref(SYS_BUS_DEVICE(i440fx_host), &error_fatal); + + pci_bus = PCI_BUS(qdev_get_child_bus(DEVICE(i440fx_host), "pci.0")); pci_bus_map_irqs(pci_bus, xen_enabled() ? xen_pci_slot_get_pirq : pc_pci_slot_get_pirq); diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c index e8e66afc11..62d6287681 100644 --- a/hw/pci-host/i440fx.c +++ b/hw/pci-host/i440fx.c @@ -249,9 +249,14 @@ static void i440fx_pcihost_initfn(Object *obj) static void i440fx_pcihost_realize(DeviceState *dev, Error **errp) { + ERRP_GUARD(); I440FXState *s = I440FX_PCI_HOST_BRIDGE(dev); PCIHostState *phb = PCI_HOST_BRIDGE(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + PCIBus *b; + PCIDevice *d; + PCII440FXState *f; + unsigned i; memory_region_add_subregion(s->io_memory, 0xcf8, &phb->conf_mem); sysbus_init_ioports(sbd, 0xcf8, 4); @@ -262,37 +267,10 @@ static void i440fx_pcihost_realize(DeviceState *dev, Error **errp) /* register i440fx 0xcf8 port as coalesced pio */ memory_region_set_flush_coalesced(&phb->data_mem); memory_region_add_coalescing(&phb->conf_mem, 0, 4); -} - -PCIBus *i440fx_init(const char *pci_type, - DeviceState *dev, - MemoryRegion *address_space_mem, - MemoryRegion *address_space_io, - ram_addr_t below_4g_mem_size, - ram_addr_t above_4g_mem_size, - MemoryRegion *pci_address_space, - MemoryRegion *ram_memory) -{ - I440FXState *s = I440FX_PCI_HOST_BRIDGE(dev); - PCIHostState *phb = PCI_HOST_BRIDGE(dev); - PCIBus *b; - PCIDevice *d; - PCII440FXState *f; - unsigned i; - - s->system_memory = address_space_mem; - s->io_memory = address_space_io; - s->pci_address_space = pci_address_space; - s->ram_memory = ram_memory; - s->below_4g_mem_size = below_4g_mem_size; - s->above_4g_mem_size = above_4g_mem_size; - s->pci_type = (char *)pci_type; b = pci_root_bus_new(dev, NULL, s->pci_address_space, s->io_memory, 0, TYPE_PCI_BUS); phb->bus = b; - object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev)); - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); d = pci_create_simple(b, 0, s->pci_type); f = I440FX_PCI_DEVICE(d); @@ -336,8 +314,6 @@ PCIBus *i440fx_init(const char *pci_type, d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size; i440fx_update_memory_mappings(f); - - return b; } static void i440fx_class_init(ObjectClass *klass, void *data) From patchwork Wed Jun 28 19:52:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1801256 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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(dynamic-077-191-074-208.77.191.pool.telefonica.de. [77.191.74.208]) by smtp.gmail.com with ESMTPSA id ec10-20020a170906b6ca00b00982be08a9besm6142817ejb.172.2023.06.28.12.52.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jun 2023 12:52:29 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , "Michael S. Tsirkin" , Marcel Apfelbaum , Richard Henderson , Paolo Bonzini , Bernhard Beschow , Igor Mammedov Subject: [PATCH v2 15/16] hw/i386/pc_piix: Turn some local variables into initializers Date: Wed, 28 Jun 2023 21:52:03 +0200 Message-ID: <20230628195204.1241-16-shentey@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230628195204.1241-1-shentey@gmail.com> References: <20230628195204.1241-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=shentey@gmail.com; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Eliminates an else branch. Suggested-by: Igor Mammedov Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/i386/pc_piix.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 1df309b8e2..d07218a8c9 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -122,11 +122,11 @@ static void pc_init1(MachineState *machine, BusState *idebus[MAX_IDE_BUS]; ISADevice *rtc_state; MemoryRegion *ram_memory; - MemoryRegion *pci_memory; - MemoryRegion *rom_memory; + MemoryRegion *pci_memory = NULL; + MemoryRegion *rom_memory = system_memory; ram_addr_t lowmem; - uint64_t hole64_size; - Object *i440fx_host; + uint64_t hole64_size = 0; + Object *i440fx_host = NULL; /* * Calculate ram split, for memory below and above 4G. It's a bit @@ -205,11 +205,6 @@ static void pc_init1(MachineState *machine, hole64_size = object_property_get_uint(i440fx_host, PCI_HOST_PROP_PCI_HOLE64_SIZE, &error_abort); - } else { - pci_memory = NULL; - rom_memory = system_memory; - i440fx_host = NULL; - hole64_size = 0; } pc_guest_info_init(pcms); From patchwork Wed Jun 28 19:52:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1801246 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=H38jqLkd; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Qrsh95Lyrz20Xg for ; Thu, 29 Jun 2023 05:53:13 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qEbDP-0004m0-Mz; Wed, 28 Jun 2023 15:52:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qEbDO-0004lY-3G for qemu-devel@nongnu.org; Wed, 28 Jun 2023 15:52:34 -0400 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qEbDM-0005ki-B7 for qemu-devel@nongnu.org; Wed, 28 Jun 2023 15:52:33 -0400 Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-991c786369cso23591066b.1 for ; Wed, 28 Jun 2023 12:52:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687981951; x=1690573951; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vuZVGOxAdERUIbSNFIHqfH0CMoojuSo58L7TfE1HkoU=; b=H38jqLkdOVLCAUiqIUZOfzr7ditKus67r8uMLTb3RNT1oYdu7zm1AUYtDChBZmSSRa 3SVuGbCO5fnBlybbNVTkfbSas7y6/RAy2ZFymtKsiTV9504UD4jIl/0fqnTf1duCEDSO fWCdb3HCVXHxU8qu8y29LnGC/kKIuEbhTHXAEO8qETMMXUtmZ3KH7OqBHIk1XV/MsTON 0T/kDTxkCpsJNHs+f/y5vQX6UoKIo3uKcZ+eBct088+BVmSXbCARqSTdkQgx7UpcBCPO 3+UQQ1Jd0Sq6/uJ1JPj9kWAL0H/oAQOYVrhNfIVI0TRlg8O4hVpwCUvjnIbaKdHA2en3 F3Uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687981951; x=1690573951; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vuZVGOxAdERUIbSNFIHqfH0CMoojuSo58L7TfE1HkoU=; b=dqnhWiqHhB1s7ohBuc3q32n3xwxhRrYRq82sskCjMlapVIeUkwFV5J+edE3KOTnqpX sk36jf1HgN5lyf0sBydO5dezYKGsHEG9z50l00AArafLLF+ophRiv2tH1607ivEElJ+2 Hp9vT54bvuVTVghv7yT+MpEz8s4NXGDZ2IJh+hoVpsKXY3dNEatPro0jjL1c2pzsMm86 nGJLfvu/f2pR+5icqtXsmkXSwoKQOD88sBIY2e6qp3uL8p7r9Ksb1OBbYwy3jiBii3Bq JNLOawc3J8MAiz8E0XTa0ou63ETK4XFN/ip5884TbyZeeMODL7i/MiXT31AmGvJcS2n4 1owA== X-Gm-Message-State: AC+VfDwIDldbJbWcI6ag0aIdzi4jhH7+jC5d/NoOzfrq9lYqTzy0zIwc sZZKHeYRmHLd7wXzHoqk0v5cj+NARp0= X-Google-Smtp-Source: ACHHUZ5/7G/5+vha9GIQqJbK8Qx4sUtUiP910aKgaiWhIv9EEVMmh2FS86wL6GRvWsBCLT9SC7+6Ag== X-Received: by 2002:a17:907:72c7:b0:98c:e72c:6b83 with SMTP id du7-20020a17090772c700b0098ce72c6b83mr18037098ejc.45.1687981950760; Wed, 28 Jun 2023 12:52:30 -0700 (PDT) Received: from archlinux.. (dynamic-077-191-074-208.77.191.pool.telefonica.de. [77.191.74.208]) by smtp.gmail.com with ESMTPSA id ec10-20020a170906b6ca00b00982be08a9besm6142817ejb.172.2023.06.28.12.52.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jun 2023 12:52:30 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , "Michael S. Tsirkin" , Marcel Apfelbaum , Richard Henderson , Paolo Bonzini , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 16/16] hw/i386/pc_piix: Move i440fx' realize near its qdev_new() Date: Wed, 28 Jun 2023 21:52:04 +0200 Message-ID: <20230628195204.1241-17-shentey@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230628195204.1241-1-shentey@gmail.com> References: <20230628195204.1241-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=shentey@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org I440FX realization is currently mixed with PIIX3 creation. Furthermore, it is common practice to only set properties between a device's qdev_new() and qdev_realize(). Clean up to resolve both issues. Since I440FX spawns a PCI bus let's also move the pci_bus initialization there. Note that when running `qemu-system-x86_64 -M pc -S` before and after this patch, `info mtree` in the QEMU console doesn't show any differences except that the ordering is different. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/i386/pc_piix.c | 57 ++++++++++++++++++++++++----------------------- 1 file changed, 29 insertions(+), 28 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index d07218a8c9..b18443d3df 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -114,7 +114,7 @@ static void pc_init1(MachineState *machine, X86MachineState *x86ms = X86_MACHINE(machine); MemoryRegion *system_memory = get_system_memory(); MemoryRegion *system_io = get_system_io(); - PCIBus *pci_bus; + PCIBus *pci_bus = NULL; ISABus *isa_bus; int piix3_devfn = -1; qemu_irq smi_irq; @@ -126,7 +126,6 @@ static void pc_init1(MachineState *machine, MemoryRegion *rom_memory = system_memory; ram_addr_t lowmem; uint64_t hole64_size = 0; - Object *i440fx_host = NULL; /* * Calculate ram split, for memory below and above 4G. It's a bit @@ -198,11 +197,37 @@ static void pc_init1(MachineState *machine, } if (pcmc->pci_enabled) { + Object *phb; + pci_memory = g_new(MemoryRegion, 1); memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); rom_memory = pci_memory; - i440fx_host = OBJECT(qdev_new(host_type)); - hole64_size = object_property_get_uint(i440fx_host, + + phb = OBJECT(qdev_new(host_type)); + object_property_add_child(OBJECT(machine), "i440fx", phb); + object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, + OBJECT(ram_memory), &error_fatal); + object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM, + OBJECT(pci_memory), &error_fatal); + object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM, + OBJECT(system_memory), &error_fatal); + object_property_set_link(phb, PCI_HOST_PROP_IO_MEM, + OBJECT(system_io), &error_fatal); + object_property_set_uint(phb, PCI_HOST_BELOW_4G_MEM_SIZE, + x86ms->below_4g_mem_size, &error_fatal); + object_property_set_uint(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, + x86ms->above_4g_mem_size, &error_fatal); + object_property_set_str(phb, I440FX_HOST_PROP_PCI_TYPE, pci_type, + &error_fatal); + sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); + + pci_bus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pci.0")); + pci_bus_map_irqs(pci_bus, + xen_enabled() ? xen_pci_slot_get_pirq + : pc_pci_slot_get_pirq); + pcms->bus = pci_bus; + + hole64_size = object_property_get_uint(phb, PCI_HOST_PROP_PCI_HOLE64_SIZE, &error_abort); } @@ -238,29 +263,6 @@ static void pc_init1(MachineState *machine, PIIX3State *piix3; PCIDevice *pci_dev; - object_property_add_child(OBJECT(machine), "i440fx", i440fx_host); - object_property_set_link(i440fx_host, PCI_HOST_PROP_RAM_MEM, - OBJECT(ram_memory), &error_fatal); - object_property_set_link(i440fx_host, PCI_HOST_PROP_PCI_MEM, - OBJECT(pci_memory), &error_fatal); - object_property_set_link(i440fx_host, PCI_HOST_PROP_SYSTEM_MEM, - OBJECT(system_memory), &error_fatal); - object_property_set_link(i440fx_host, PCI_HOST_PROP_IO_MEM, - OBJECT(system_io), &error_fatal); - object_property_set_uint(i440fx_host, PCI_HOST_BELOW_4G_MEM_SIZE, - x86ms->below_4g_mem_size, &error_fatal); - object_property_set_uint(i440fx_host, PCI_HOST_ABOVE_4G_MEM_SIZE, - x86ms->above_4g_mem_size, &error_fatal); - object_property_set_str(i440fx_host, I440FX_HOST_PROP_PCI_TYPE, - pci_type, &error_fatal); - sysbus_realize_and_unref(SYS_BUS_DEVICE(i440fx_host), &error_fatal); - - pci_bus = PCI_BUS(qdev_get_child_bus(DEVICE(i440fx_host), "pci.0")); - pci_bus_map_irqs(pci_bus, - xen_enabled() ? xen_pci_slot_get_pirq - : pc_pci_slot_get_pirq); - pcms->bus = pci_bus; - pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, TYPE_PIIX3_DEVICE); @@ -285,7 +287,6 @@ static void pc_init1(MachineState *machine, rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev), "rtc")); } else { - pci_bus = NULL; isa_bus = isa_bus_new(NULL, system_memory, system_io, &error_abort);