From patchwork Fri Jun 23 20:26:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 1799111 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=UpxdlJ6A; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QnphH4VlWz20Wk for ; Sat, 24 Jun 2023 06:27:42 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qCnMm-0005Vw-2w; Fri, 23 Jun 2023 16:26:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qCnMj-0005Vj-MF for qemu-devel@nongnu.org; Fri, 23 Jun 2023 16:26:45 -0400 Received: from mga09.intel.com ([134.134.136.24]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qCnMd-0004H1-Mz for qemu-devel@nongnu.org; Fri, 23 Jun 2023 16:26:45 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687551999; x=1719087999; h=date:from:to:cc:subject:message-id:mime-version; bh=A2vOZ5LrKFon+ktVAulSszTiqag9LzYoL32QNEaHZ0g=; b=UpxdlJ6AQ0cbt0KtaDey8KHcdauk3/nKvEmB9ZfJUYeObzY9LzMdp/IH LxbBf09qV4c9QxEuyD2KbFrJ9QFEMDrrkBmxNc6eHL7G0phwaEf+PUK8E y7XeFc4mIN03aGyg3F/lPE3x6qK4sQfcdXehaVNGPn34ttVpnn7Ic8iND Ry6dfCE1tlE/rldS557UZoegduP35iBreRR5O9/7ar55VYBC9VWLfPH/B pS79nKLr9cBKNeHHrXJZo3QpsVKuPlsT0YIs49T5ueMfeT/UUtJIS8Q47 mJF0dhhJdnvvabw5aVfpkm4MPY20vwBXrE+kRk88IIrlxWZWKJKqTMRAZ g==; X-IronPort-AV: E=McAfee;i="6600,9927,10750"; a="363405742" X-IronPort-AV: E=Sophos;i="6.01,153,1684825200"; d="scan'208";a="363405742" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2023 13:26:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10750"; a="745117011" X-IronPort-AV: E=Sophos;i="6.01,153,1684825200"; d="scan'208";a="745117011" Received: from mdissana-mobl.amr.corp.intel.com (HELO desk) ([10.209.104.138]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2023 13:26:33 -0700 Date: Fri, 23 Jun 2023 13:26:25 -0700 From: Pawan Gupta To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Chao Gao Subject: [PATCH] target/i386: Export MSR_ARCH_CAPABILITIES bits to guests Message-ID: <63d85cc76d4cdc51e6c732478b81d8f13be11e5a.1687551881.git.pawan.kumar.gupta@linux.intel.com> MIME-Version: 1.0 Content-Disposition: inline Received-SPF: none client-ip=134.134.136.24; envelope-from=pawan.kumar.gupta@linux.intel.com; helo=mga09.intel.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) AC_FROM_MANY_DOTS=2.999, BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On Intel CPUs there are certain bits in MSR_ARCH_CAPABILITIES that indicates if the CPU is not affected by a vulnerability. Without these bits guests may try to deploy the mitigation even if the CPU is not affected. Export the bits to guests that indicate immunity to hardware vulnerabilities. Signed-off-by: Pawan Gupta --- target/i386/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1242bd541a53..66d6062aea7c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1049,10 +1049,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", "taa-no", NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", NULL, "fb-clear", NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + "pbrsb-no", NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, .msr = {