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([91.223.100.38]) by smtp.gmail.com with ESMTPSA id v3-20020a2e9f43000000b002b47fc5219dsm1320276ljk.67.2023.06.22.08.12.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jun 2023 08:12:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 1/4] target/arm: Avoid splitting Zregs across lines in dump Date: Thu, 22 Jun 2023 17:11:58 +0200 Message-Id: <20230622151201.1578522-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230622151201.1578522-1-richard.henderson@linaro.org> References: <20230622151201.1578522-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::236; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Allow the line length to extend to 548 columns. While annoyingly wide, it's still less confusing than the continuations we print. Also, the default VL used by Linux (and max for A64FX) uses only 140 columns. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.c | 36 ++++++++++++++---------------------- 1 file changed, 14 insertions(+), 22 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 353fc48567..7cb70f9727 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -955,7 +955,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; uint32_t psr = pstate_read(env); - int i; + int i, j; int el = arm_current_el(env); const char *ns_status; bool sve; @@ -1014,7 +1014,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) } if (sve) { - int j, zcr_len = sve_vqm1_for_el(env, el); + int zcr_len = sve_vqm1_for_el(env, el); for (i = 0; i <= FFR_PRED_NUM; i++) { bool eol; @@ -1054,32 +1054,24 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) } } - for (i = 0; i < 32; i++) { - if (zcr_len == 0) { + if (zcr_len == 0) { + /* + * With vl=16, there are only 37 columns per register, + * so output two registers per line. + */ + for (i = 0; i < 32; i++) { qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", i, env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); - } else if (zcr_len == 1) { - qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 - ":%016" PRIx64 ":%016" PRIx64 "\n", - i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], - env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); - } else { + } + } else { + for (i = 0; i < 32; i++) { + qemu_fprintf(f, "Z%02d=", i); for (j = zcr_len; j >= 0; j--) { - bool odd = (zcr_len - j) % 2 != 0; - if (j == zcr_len) { - qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); - } else if (!odd) { - if (j > 0) { - qemu_fprintf(f, " [%x-%x]=", j, j - 1); - } else { - qemu_fprintf(f, " [%x]=", j); - } - } qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", env->vfp.zregs[i].d[j * 2 + 1], - env->vfp.zregs[i].d[j * 2], - odd || j == 0 ? "\n" : ":"); + env->vfp.zregs[i].d[j * 2 + 0], + j ? ":" : "\n"); } } } From patchwork Thu Jun 22 15:11:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1798471 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=gdi6maUL; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Qn3mW6XDrz20XS for ; Fri, 23 Jun 2023 01:13:47 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qCLyn-0006l8-JO; Thu, 22 Jun 2023 11:12:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qCLyl-0006kX-U3 for qemu-devel@nongnu.org; Thu, 22 Jun 2023 11:12:11 -0400 Received: from mail-lj1-x22d.google.com ([2a00:1450:4864:20::22d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qCLyk-0000Fk-8U for qemu-devel@nongnu.org; Thu, 22 Jun 2023 11:12:11 -0400 Received: by mail-lj1-x22d.google.com with SMTP id 38308e7fff4ca-2b46f5f4d79so9536971fa.1 for ; Thu, 22 Jun 2023 08:12:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687446728; x=1690038728; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fNQxNM+X/9et0gxYk0zQKZupNp4oqf6HxOnV5h8wxLw=; b=gdi6maUL2epezfn3klrOivgtT2f/8FIz6EM2IxFL3Ntn9FXho1hDaDNz8g8kKj4juX MPk11not16RbAhKvDlGEGrSPjS3qhBgDrgw4omkHitrXPhsjCJpNZAKN7V2ZyHaZdPta DSfeQxX9djSVXW/6NzgI7VYHZTCI2LnXLODsjCVXSP1TFHAXPjeg6++Co9EojVy404Vd cupTJ1ac09/jplNBwGXIlWxV+agKYsgOsJ1NkJ37yHmDUwe0xldihe6qOeIJ9pQnXiQv 7CCt4oMXKHUlMpc5MuaoofFJ5CzcSYGKBqUlcBkGCSOZKtwtqPCc6yOp07likf1R+tPh bk4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687446728; x=1690038728; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fNQxNM+X/9et0gxYk0zQKZupNp4oqf6HxOnV5h8wxLw=; b=e9IyX6fm/L9ZlI+YHa/YNa+9psTABaMNM05EAkO0qaAYh6nvXUJO3vWmN702zyeIpb PENhuuwWXThCA0hJwsB8AbzDVbQ67uvcsfEcplACvGYqModkz9JpIZXxOExxIjnCUmBN A+lnHZ9lmUIVxFXaimGViAqu1SRwWntaJAN8cqGGCsViywKyQlSivX/n2jtJQfZh9xRm xppTA8jedCEj44jd21C3xHcG3PVEgNXMm4zgdDKKDkI8PG9b0Z1ZI6JkvoQkAIw9cP8l R04GLBj9hSLqiN7YoijtqkoXxSelvHb1iQNzfBjSz7Ldcs3eYsA/hw2D5ScJ+1SbRiJ5 pH+A== X-Gm-Message-State: AC+VfDxvI42zdPxWNKBE/wyuFrQsbR4aHH7gRWxmMh7OG+qLOdg3SF5P 6S4WySdfTaIFj5fjA83d1VBYujtj/n3fKUNxFMusX5hl X-Google-Smtp-Source: ACHHUZ7WCTQf58wHvN5SWyuPShRWP1fhH+lCYUoZyRpGSUC6Jj+Ooa1onJp3O0d9AQ5ZmF+HGiyWQg== X-Received: by 2002:a2e:8e2b:0:b0:2b4:5d74:d760 with SMTP id r11-20020a2e8e2b000000b002b45d74d760mr5103734ljk.25.1687446728250; Thu, 22 Jun 2023 08:12:08 -0700 (PDT) Received: from stoup.. ([91.223.100.38]) by smtp.gmail.com with ESMTPSA id v3-20020a2e9f43000000b002b47fc5219dsm1320276ljk.67.2023.06.22.08.12.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jun 2023 08:12:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 2/4] target/arm: Dump ZA[] when active Date: Thu, 22 Jun 2023 17:11:59 +0200 Message-Id: <20230622151201.1578522-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230622151201.1578522-1-richard.henderson@linaro.org> References: <20230622151201.1578522-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Always print each matrix row whole, one per line, so that we get the entire matrix in the proper shape. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7cb70f9727..3da811bc5e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1082,6 +1082,24 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) i, q[1], q[0], (i & 1 ? "\n" : " ")); } } + + if (cpu_isar_feature(aa64_sme, cpu) && + FIELD_EX64(env->svcr, SVCR, ZA) && + sme_exception_el(env, el) == 0) { + int zcr_len = sve_vqm1_for_el_sm(env, el, true); + int svl = (zcr_len + 1) * 16; + int svl_lg10 = svl < 100 ? 2 : 3; + + for (i = 0; i < svl; i++) { + qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i); + for (j = zcr_len; j >= 0; --j) { + qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c", + env->zarray[i].d[2 * j + 1], + env->zarray[i].d[2 * j], + j ? ':' : '\n'); + } + } + } } #else From patchwork Thu Jun 22 15:12:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1798469 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=K/GQfdbn; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Qn3lw4d44z20XS for ; Fri, 23 Jun 2023 01:13:16 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qCLyp-0006la-6b; Thu, 22 Jun 2023 11:12:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qCLyn-0006kn-15 for qemu-devel@nongnu.org; Thu, 22 Jun 2023 11:12:13 -0400 Received: from mail-lj1-x22d.google.com ([2a00:1450:4864:20::22d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qCLyl-0000HW-5R for qemu-devel@nongnu.org; Thu, 22 Jun 2023 11:12:12 -0400 Received: by mail-lj1-x22d.google.com with SMTP id 38308e7fff4ca-2b47742de92so73350861fa.0 for ; Thu, 22 Jun 2023 08:12:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687446729; x=1690038729; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0TccvH+qpCGtNsDlIDGjbT6JxihYcWpoZghsjPC3N3M=; b=K/GQfdbnhevSVCFKwc9gSTJ14WkcvQbsUzsoUKbwohkXnuJBABCceoGjiqXgd2+0M9 ghL5RP566+mUry9jKXs767YiqAUTn1NZCGryPR9HElEh5CgTbk+O8R7oiENoCE+qZaPc HGQQ6rT8uxEbtEHXdEyEsXD15lc6CfP6xFuyv3ZopAjywxnmo6dq/LptGEEcBH7Hwqh9 t1nROplahVet7hGhg2Mc+tJYoN3OJCmbSf/kb/khr7sqcbRAIKJIOsLjXB3MXuGjpuox G1ER+1AlsL0gs6upmI2/5OWJ3q+JzHByd8J1mpSFI/JIShFyW0cC+Z5z3gHeIXLH1WBc hAgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687446729; x=1690038729; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0TccvH+qpCGtNsDlIDGjbT6JxihYcWpoZghsjPC3N3M=; b=EuvaKDTRF3aEz2gpgkHc3lXV0a82bPcTwJ6KZ/MRre7BukswHZa/pbknF9yzItFAPP /tu2cc5Tr0NtWzsR3ZN1jJjE5MCnLVZ1sdcGPoCsJP9sZVv0oZhTGOe2oS8eZLQZQUz3 EcvUPIy0GvMKXVrNHkrsoB2OxOQJMS5W6/Ncxj+Pz+gTRgmnnglaYV83+GuUXZLIOIu0 8gelvvCB9TbxcWeA+7LlV4MbctudYXE73cAcWAtjMVe2hoYQu2UHZulLFwjWj54OI/kp ZqYMH+IeCRwBGfnZj7o+xtzHoBPss0kuObKkQlJe1RxXab0RtyfxQKsldyb1kaDsJfDu xNew== X-Gm-Message-State: AC+VfDzqD9RJyiRV9xtHsjcfJSPr0kHux12SyO+ZI9Tp2k5QtLJ4mUBG BhSo63/rWPi8YJn39SkTtpqtvCVMgcxLUPl+tdTnegKW X-Google-Smtp-Source: ACHHUZ6cY91N81B0HBDL6OVMcQ1WWGoC0Logz0hwQ3wx6qaerxNS78YptZOEoWatB8dYuYHPbo1tLQ== X-Received: by 2002:a2e:8241:0:b0:2b5:84fb:5939 with SMTP id j1-20020a2e8241000000b002b584fb5939mr3641223ljh.30.1687446729573; Thu, 22 Jun 2023 08:12:09 -0700 (PDT) Received: from stoup.. ([91.223.100.38]) by smtp.gmail.com with ESMTPSA id v3-20020a2e9f43000000b002b47fc5219dsm1320276ljk.67.2023.06.22.08.12.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jun 2023 08:12:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 3/4] target/arm: Support reading ZA[] from gdbstub Date: Thu, 22 Jun 2023 17:12:00 +0200 Message-Id: <20230622151201.1578522-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230622151201.1578522-1-richard.henderson@linaro.org> References: <20230622151201.1578522-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Mirror the existing support for SVE. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/internals.h | 3 ++ target/arm/gdbstub.c | 8 ++++ target/arm/gdbstub64.c | 88 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 100 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index af0119addf..082617cfc6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -877,6 +877,7 @@ struct ArchCPU { DynamicGDBXMLInfo dyn_sysreg_xml; DynamicGDBXMLInfo dyn_svereg_xml; + DynamicGDBXMLInfo dyn_zareg_xml; DynamicGDBXMLInfo dyn_m_systemreg_xml; DynamicGDBXMLInfo dyn_m_secextreg_xml; diff --git a/target/arm/internals.h b/target/arm/internals.h index e3029bdc37..54d1f28992 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1362,12 +1362,15 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env) #ifdef TARGET_AARCH64 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); +int arm_gen_dynamic_zareg_xml(CPUState *cpu, int base_reg); int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg); int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg); +int aarch64_gdb_get_za_reg(CPUARMState *env, GByteArray *buf, int reg); +int aarch64_gdb_set_za_reg(CPUARMState *env, uint8_t *buf, int reg); void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 03b17c814f..1204eb40d7 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -490,6 +490,8 @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) return cpu->dyn_sysreg_xml.desc; } else if (strcmp(xmlname, "sve-registers.xml") == 0) { return cpu->dyn_svereg_xml.desc; + } else if (strcmp(xmlname, "za-registers.xml") == 0) { + return cpu->dyn_zareg_xml.desc; } else if (strcmp(xmlname, "arm-m-system.xml") == 0) { return cpu->dyn_m_systemreg_xml.desc; #ifndef CONFIG_USER_ONLY @@ -532,6 +534,12 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) aarch64_gdb_set_pauth_reg, 4, "aarch64-pauth.xml", 0); } + if (cpu_isar_feature(aa64_sme, cpu)) { + int nreg = arm_gen_dynamic_zareg_xml(cs, cs->gdb_num_regs); + gdb_register_coprocessor(cs, aarch64_gdb_get_za_reg, + aarch64_gdb_set_za_reg, nreg, + "za-registers.xml", 0); + } #endif } else { if (arm_feature(env, ARM_FEATURE_NEON)) { diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index d7b79a6589..b76fac9bd0 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -247,6 +247,61 @@ int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } +static int max_svq(ARMCPU *cpu) +{ + return 32 - clz32(cpu->sme_vq.map); +} + +int aarch64_gdb_get_za_reg(CPUARMState *env, GByteArray *buf, int reg) +{ + ARMCPU *cpu = env_archcpu(env); + int max_vq = max_svq(cpu); + int cur_vq = EX_TBFLAG_A64(env->hflags, SVL) + 1; + int i; + + if (reg >= max_vq * 16) { + return 0; + } + + /* If ZA is unset, or reg out of range, the contents are zero. */ + if (FIELD_EX64(env->svcr, SVCR, ZA) && reg < cur_vq * 16) { + for (i = 0; i < cur_vq; i++) { + gdb_get_reg128(buf, env->zarray[reg].d[i * 2 + 1], + env->zarray[reg].d[i * 2]); + } + } else { + cur_vq = 0; + } + + for (i = cur_vq; i < max_vq; i++) { + gdb_get_reg128(buf, 0, 0); + } + + return max_vq * 16; +} + +int aarch64_gdb_set_za_reg(CPUARMState *env, uint8_t *buf, int reg) +{ + ARMCPU *cpu = env_archcpu(env); + uint64_t *p = (uint64_t *) buf; + int max_vq = max_svq(cpu); + int cur_vq = EX_TBFLAG_A64(env->hflags, SVL) + 1; + int i; + + if (reg >= max_vq * 16) { + return 0; + } + + /* If ZA is unset, or reg out of range, the contents are zero. */ + if (FIELD_EX64(env->svcr, SVCR, ZA) && reg < cur_vq * 16) { + for (i = 0; i < cur_vq; i++) { + env->zarray[reg].d[i * 2 + 1] = *p++; + env->zarray[reg].d[i * 2 + 0] = *p++; + } + } + return max_vq * 16; +} + static void output_vector_union_type(GString *s, int reg_width, const char *name) { @@ -379,3 +434,36 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) info->num = base_reg - orig_base_reg; return info->num; } + +/* + * Generate the xml for SME, with matrix size set to the maximum + * for the cpu. Returns the number of registers generated. + */ +int arm_gen_dynamic_zareg_xml(CPUState *cs, int base_reg) +{ + ARMCPU *cpu = ARM_CPU(cs); + GString *s = g_string_new(NULL); + int vq = max_svq(cpu); + int row_count = vq * 16; + int row_width = vq * 128; + int i; + + g_string_printf(s, ""); + g_string_append_printf(s, ""); + g_string_append_printf(s, ""); + + output_vector_union_type(s, row_width, "zav"); + + for (i = 0; i < row_count; i++) { + g_string_append_printf(s, + "", + i, row_width, base_reg + i); + } + + g_string_append_printf(s, ""); + + cpu->dyn_zareg_xml.num = row_count; + cpu->dyn_zareg_xml.desc = g_string_free(s, false); + return row_count; +} From patchwork Thu Jun 22 15:12:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1798468 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=s72X3n2a; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Qn3ld63JTz20XS for ; Fri, 23 Jun 2023 01:13:01 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qCLyp-0006lq-Uq; Thu, 22 Jun 2023 11:12:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qCLyo-0006lR-Sk for qemu-devel@nongnu.org; Thu, 22 Jun 2023 11:12:14 -0400 Received: from mail-lj1-x22a.google.com ([2a00:1450:4864:20::22a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qCLym-0000Hr-Es for qemu-devel@nongnu.org; Thu, 22 Jun 2023 11:12:14 -0400 Received: by mail-lj1-x22a.google.com with SMTP id 38308e7fff4ca-2b46cad2fd9so81517361fa.1 for ; Thu, 22 Jun 2023 08:12:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687446731; x=1690038731; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IfVJcswhQ8kqab64RY2sMZ/e45jah2WOis+BNjLJ8rY=; b=s72X3n2abs/dVV0gHydSLfV5Ur0hNAmEzc28I4/pjjHqTdOKvh3ugHSZkj7SkBLJTd DXZQN2tjZowU3UvdUoLlC0R9HQ4nYemrFfHiQCyLcYh4nFfVLHGsoIh1KCpk16xwpAgj rv84TrGw3pbIgNYD1HPmCwVJRPf+T5q2hRQC3jJy7PCHydQVbPsbrTY1CyyHDCMG3+R+ upqEq/ShvUS0OTBZz+Tk2dy2xgpvoT4z7AdTI2DYVoSWafFiPHLOcenbxHUfrx+zhxGC jMfyinIDgPdn1JKQeX8nlB3MeQX9b/bfuisoXe6N1M9EPQLEKokH3FGWBrmKz5Ne8Ob+ 9w4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687446731; x=1690038731; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IfVJcswhQ8kqab64RY2sMZ/e45jah2WOis+BNjLJ8rY=; b=jIMZXr3RUCiL68v4gbL0XT2fJKxDCY06pPsGpbc8pdwgdOhRl0qeGogsgQYtJ2kcMK Wykv5Z4F48hAUzBh9e7pT9wzKhkm2ETqLL0+/7ixVxB3Hr2YVAs3nj1ZsXvnvj9KqP2d NyMrJo5Aeau2qXYyRpglnirp9zDLJ5q/jGzADMtCpoV08I31TX4TcMKrusLNVaqpNb4R wG2AL/RW3qtkaA1soxterB33LI0WJ+wtds1paTOy7NhrZBCjjlerhEKbsN6fWybYQyRR JADJ5D7p9hgXNnTW3Ci3axVtb3uxQiyqiAKGEEbQFV9ILM10l03lWM71hs+P10nsTUmz Ptig== X-Gm-Message-State: AC+VfDxjndJy+ENhqyaK3i7V0kkpCD9xiZ3Qdo3OnUnboNCtxaEXjmEA bal4gnHCy2v2rifvrXeRYXV4I/6MHmZecH6Muiq1sRyz X-Google-Smtp-Source: ACHHUZ5VlK8syDty+8SaZOoHxakNai97dFlJQWNQfsy/CSDJhBqwuAlNn3YRrm6pak6ilOIpVURThA== X-Received: by 2002:a2e:8887:0:b0:2b4:8239:b12d with SMTP id k7-20020a2e8887000000b002b48239b12dmr7081310lji.0.1687446730686; Thu, 22 Jun 2023 08:12:10 -0700 (PDT) Received: from stoup.. ([91.223.100.38]) by smtp.gmail.com with ESMTPSA id v3-20020a2e9f43000000b002b47fc5219dsm1320276ljk.67.2023.06.22.08.12.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jun 2023 08:12:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 4/4] target/arm: Fix SME full tile indexing Date: Thu, 22 Jun 2023 17:12:01 +0200 Message-Id: <20230622151201.1578522-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230622151201.1578522-1-richard.henderson@linaro.org> References: <20230622151201.1578522-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22a; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org For the outer product set of insns, which take an entire matrix tile as output, the argument is not a combined tile+column. Therefore using get_tile_rowcol was incorrect, as we extracted the tile number from itself. The test case relies only on assembler support for SME, since no release of GCC recognizes -march=armv9-a+sme yet. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1620 Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/tcg/translate-sme.c | 24 ++++++--- tests/tcg/aarch64/sme-outprod1.c | 83 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 10 ++-- 3 files changed, 108 insertions(+), 9 deletions(-) create mode 100644 tests/tcg/aarch64/sme-outprod1.c diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index d0054e3f77..6038b0a06f 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -95,6 +95,21 @@ static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz, int rs, return addr; } +/* + * Resolve tile.size[0] to a host pointer. + * Used by e.g. outer product insns where we require the entire tile. + */ +static TCGv_ptr get_tile(DisasContext *s, int esz, int tile) +{ + TCGv_ptr addr = tcg_temp_new_ptr(); + int offset; + + offset = tile * sizeof(ARMVectorReg) + offsetof(CPUARMState, zarray); + + tcg_gen_addi_ptr(addr, cpu_env, offset); + return addr; +} + static bool trans_ZERO(DisasContext *s, arg_ZERO *a) { if (!dc_isar_feature(aa64_sme, s)) { @@ -260,8 +275,7 @@ static bool do_adda(DisasContext *s, arg_adda *a, MemOp esz, return true; } - /* Sum XZR+zad to find ZAd. */ - za = get_tile_rowcol(s, esz, 31, a->zad, false); + za = get_tile(s, esz, a->zad); zn = vec_full_reg_ptr(s, a->zn); pn = pred_full_reg_ptr(s, a->pn); pm = pred_full_reg_ptr(s, a->pm); @@ -286,8 +300,7 @@ static bool do_outprod(DisasContext *s, arg_op *a, MemOp esz, return true; } - /* Sum XZR+zad to find ZAd. */ - za = get_tile_rowcol(s, esz, 31, a->zad, false); + za = get_tile(s, esz, a->zad); zn = vec_full_reg_ptr(s, a->zn); zm = vec_full_reg_ptr(s, a->zm); pn = pred_full_reg_ptr(s, a->pn); @@ -308,8 +321,7 @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, return true; } - /* Sum XZR+zad to find ZAd. */ - za = get_tile_rowcol(s, esz, 31, a->zad, false); + za = get_tile(s, esz, a->zad); zn = vec_full_reg_ptr(s, a->zn); zm = vec_full_reg_ptr(s, a->zm); pn = pred_full_reg_ptr(s, a->pn); diff --git a/tests/tcg/aarch64/sme-outprod1.c b/tests/tcg/aarch64/sme-outprod1.c new file mode 100644 index 0000000000..6e5972d75e --- /dev/null +++ b/tests/tcg/aarch64/sme-outprod1.c @@ -0,0 +1,83 @@ +/* + * SME outer product, 1 x 1. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include + +extern void foo(float *dst); + +asm( +" .arch_extension sme\n" +" .type foo, @function\n" +"foo:\n" +" stp x29, x30, [sp, -80]!\n" +" mov x29, sp\n" +" stp d8, d9, [sp, 16]\n" +" stp d10, d11, [sp, 32]\n" +" stp d12, d13, [sp, 48]\n" +" stp d14, d15, [sp, 64]\n" +" smstart\n" +" ptrue p0.s, vl4\n" +" fmov z0.s, #1.0\n" +/* + * An outer product of a vector of 1.0 by itself should be a matrix of 1.0. + * Note that we are using tile 1 here (za1.s) rather than tile 0. + */ +" zero {za}\n" +" fmopa za1.s, p0/m, p0/m, z0.s, z0.s\n" +/* + * Read the first 4x4 sub-matrix of elements from tile 1: + * Note that za1h should be interchangable here. + */ +" mov w12, #0\n" +" mova z0.s, p0/m, za1v.s[w12, #0]\n" +" mova z1.s, p0/m, za1v.s[w12, #1]\n" +" mova z2.s, p0/m, za1v.s[w12, #2]\n" +" mova z3.s, p0/m, za1v.s[w12, #3]\n" +/* + * And store them to the input pointer (dst in the C code): + */ +" st1w {z0.s}, p0, [x0]\n" +" add x0, x0, #16\n" +" st1w {z1.s}, p0, [x0]\n" +" add x0, x0, #16\n" +" st1w {z2.s}, p0, [x0]\n" +" add x0, x0, #16\n" +" st1w {z3.s}, p0, [x0]\n" +" smstop\n" +" ldp d8, d9, [sp, 16]\n" +" ldp d10, d11, [sp, 32]\n" +" ldp d12, d13, [sp, 48]\n" +" ldp d14, d15, [sp, 64]\n" +" ldp x29, x30, [sp], 80\n" +" ret\n" +" .size foo, . - foo" +); + +int main() +{ + float dst[16]; + int i, j; + + foo(dst); + + for (i = 0; i < 16; i++) { + if (dst[i] != 1.0f) { + break; + } + } + + if (i == 16) { + return 0; /* success */ + } + + /* failure */ + for (i = 0; i < 4; ++i) { + for (j = 0; j < 4; ++j) { + printf("%f ", (double)dst[i * 4 + j]); + } + printf("\n"); + } + return 1; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 3430fd3cd8..253ea9c481 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -26,7 +26,7 @@ config-cc.mak: Makefile $(call cc-option,-march=armv8.5-a, CROSS_CC_HAS_ARMV8_5); \ $(call cc-option,-mbranch-protection=standard, CROSS_CC_HAS_ARMV8_BTI); \ $(call cc-option,-march=armv8.5-a+memtag, CROSS_CC_HAS_ARMV8_MTE); \ - $(call cc-option,-march=armv9-a+sme, CROSS_CC_HAS_ARMV9_SME)) 3> config-cc.mak + $(call cc-option,-Wa$(COMMA)-march=armv9-a+sme, CROSS_AS_HAS_ARMV9_SME)) 3> config-cc.mak -include config-cc.mak ifneq ($(CROSS_CC_HAS_ARMV8_2),) @@ -61,11 +61,15 @@ AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-5 mte-6 mte-7 mte-%: CFLAGS += -march=armv8.5-a+memtag endif +ifneq ($(CROSS_AS_HAS_ARMV9_SME),) +AARCH64_TESTS += sme-outprod1 +endif + ifneq ($(CROSS_CC_HAS_SVE),) # System Registers Tests AARCH64_TESTS += sysregs -ifneq ($(CROSS_CC_HAS_ARMV9_SME),) -sysregs: CFLAGS+=-march=armv9-a+sme -DHAS_ARMV9_SME +ifneq ($(CROSS_AS_HAS_ARMV9_SME),) +sysregs: CFLAGS+=-Wa,-march=armv9-a+sme -DHAS_ARMV9_SME else sysregs: CFLAGS+=-march=armv8.1-a+sve endif