From patchwork Thu Jun 15 09:30:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Martin Kaiser X-Patchwork-Id: 1795331 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QhcXl5Trcz20QH for ; Thu, 15 Jun 2023 19:33:11 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9jLM-0007L1-09; Thu, 15 Jun 2023 05:32:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9jLK-0007KY-MC; Thu, 15 Jun 2023 05:32:38 -0400 Received: from viti.kaiser.cx ([2a01:238:43fe:e600:cd0c:bd4a:7a3:8e9f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9jLJ-0004Pf-48; Thu, 15 Jun 2023 05:32:38 -0400 Received: from [167.98.155.120] (helo=martin-debian-2.paytec.ch) by viti.kaiser.cx with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1q9jLD-0008SN-Hb; Thu, 15 Jun 2023 11:32:31 +0200 From: Martin Kaiser To: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Paolo Bonzini Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Martin Kaiser Subject: [PATCH v2] imx_serial: set wake bit when we receive a data byte Date: Thu, 15 Jun 2023 10:30:54 +0100 Message-Id: <20230615093054.1084972-1-martin@kaiser.cx> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230608154129.133169-1-martin@kaiser.cx> References: <20230608154129.133169-1-martin@kaiser.cx> MIME-Version: 1.0 Received-SPF: none client-ip=2a01:238:43fe:e600:cd0c:bd4a:7a3:8e9f; envelope-from=postmaster@kaiser.cx; helo=viti.kaiser.cx X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The linux kernel added a flood check for rx data recently in commmit 496a4471b7c3 ("serial: imx: work-around for hardware RX flood"). This check uses the wake bit in the uart status register 2. The wake bit indicates that the receiver detected a start bit on the rx line. If the kernel sees a number of rx interrupts without the wake bit being set, it treats this as spurious data and resets the uart port. imx_serial does never set the wake bit and triggers the kernel's flood check. This patch adds support for the wake bit. wake is set when we receive a new character (it's not set for break events). It seems that wake is cleared by the kernel driver, the hardware does not have to clear it automatically after data was read. The wake bit can be configured as an interrupt source. Support this mechanism as well. Co-developed-by: Philippe Mathieu-Daudé Signed-off-by: Martin Kaiser Reviewed-by: Philippe Mathieu-Daudé --- v2: - support interrupts from wake - clean up the commit message hw/char/imx_serial.c | 5 ++++- include/hw/char/imx_serial.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c index ee1375e26d..1b75a89588 100644 --- a/hw/char/imx_serial.c +++ b/hw/char/imx_serial.c @@ -80,7 +80,7 @@ static void imx_update(IMXSerialState *s) * TCEN and TXDC are both bit 3 * RDR and DREN are both bit 0 */ - mask |= s->ucr4 & (UCR4_TCEN | UCR4_DREN); + mask |= s->ucr4 & (UCR4_WKEN | UCR4_TCEN | UCR4_DREN); usr2 = s->usr2 & mask; @@ -321,6 +321,9 @@ static void imx_put_data(void *opaque, uint32_t value) static void imx_receive(void *opaque, const uint8_t *buf, int size) { + IMXSerialState *s = (IMXSerialState *)opaque; + + s->usr2 |= USR2_WAKE; imx_put_data(opaque, *buf); } diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h index 91c9894ad5..b823f94519 100644 --- a/include/hw/char/imx_serial.h +++ b/include/hw/char/imx_serial.h @@ -71,6 +71,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL) #define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */ #define UCR4_TCEN BIT(3) /* TX complete interrupt enable */ +#define UCR4_WKEN BIT(7) /* WAKE interrupt enable */ #define UTS1_TXEMPTY (1<<6) #define UTS1_RXEMPTY (1<<5)