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[85.226.240.245]) by smtp.gmail.com with ESMTPSA id t5-20020a2e9c45000000b002b1a872c826sm276682ljj.61.2023.06.08.08.16.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jun 2023 08:16:04 -0700 (PDT) Received: by flawful.org (Postfix, from userid 112) id D682B1543; Thu, 8 Jun 2023 17:16:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1686237363; bh=JupprQojrdw2iPIgmo9yMMB9PX3VO+98r8Mxh4PDiQU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=t3B8yXXm7fVRz/sdfVhpWDgWNjaeSokDIpyzoe7zRniH9x19GGRoVycWBKsVUOEXV 3ULlPTHm71VRQAOkVLQbijrbecwURU1vbjD3caQhCWkyzv/Au6k/4nWEj4096rFci6 zvjaSjsE8chpX9rMvRdNOKxUv8H9DGhDhORBkW9E= Received: from x1-carbon.wireless.wdc (unknown [129.253.182.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by flawful.org (Postfix) with ESMTPSA id D9CED12C6; Thu, 8 Jun 2023 17:15:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1686237346; bh=JupprQojrdw2iPIgmo9yMMB9PX3VO+98r8Mxh4PDiQU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y0vRrpXZMiMiNGORwSSIHFvFdmofbqzYKD3RrZ47PnZTE8E0R/OaPgjfM2NWaO7t7 IRAD0ZuKx3N6husDgruxDf0wTJN3E70zivx/cOju3X9m0JvxaTt/mOLm9t106dALaY yOmn4TsjzyjgGcjnyWwliTLu6Khg9Use/TcO0FzI= From: Niklas Cassel To: John Snow Cc: qemu-block@nongnu.org, qemu-devel@nongnu.org, Damien Le Moal , Niklas Cassel Subject: [PATCH 1/5] libqos/ahci: fix ahci_command_wait() Date: Thu, 8 Jun 2023 17:15:24 +0200 Message-Id: <20230608151528.143950-2-nks@flawful.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230608151528.143950-1-nks@flawful.org> References: <20230608151528.143950-1-nks@flawful.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::236; envelope-from=nks.gnu@gmail.com; helo=mail-lj1-x236.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Niklas Cassel A command that has ERR_STAT set, does not get to clear PxCI. See AHCI 1.3.1, section 5.3.8, states RegFIS:Entry and RegFIS:ClearCI, and 5.3.16.5 ERR:FatalTaskfile. Some tests, e.g. test_atapi_tray() call ahci_atapi_test_ready() with ready == false, intentionally sending a command that will cause an error. Thus, ahci_command_wait() cannot simply wait indefinitely for PxCI to be cleared, it also has to take ERR_STAT into account. Signed-off-by: Niklas Cassel --- tests/qtest/libqos/ahci.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/tests/qtest/libqos/ahci.c b/tests/qtest/libqos/ahci.c index f53f12aa99..c1d571e477 100644 --- a/tests/qtest/libqos/ahci.c +++ b/tests/qtest/libqos/ahci.c @@ -1207,9 +1207,10 @@ void ahci_command_wait(AHCIQState *ahci, AHCICommand *cmd) #define RSET(REG, MASK) (BITSET(ahci_px_rreg(ahci, cmd->port, (REG)), (MASK))) - while (RSET(AHCI_PX_TFD, AHCI_PX_TFD_STS_BSY) || - RSET(AHCI_PX_CI, 1 << cmd->slot) || - (cmd->props->ncq && RSET(AHCI_PX_SACT, 1 << cmd->slot))) { + while (!RSET(AHCI_PX_TFD, AHCI_PX_TFD_STS_ERR) && + (RSET(AHCI_PX_TFD, AHCI_PX_TFD_STS_BSY) || + RSET(AHCI_PX_CI, 1 << cmd->slot) || + (cmd->props->ncq && RSET(AHCI_PX_SACT, 1 << cmd->slot)))) { usleep(50); } From patchwork Thu Jun 8 15:15:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1792358 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=flawful.org header.i=@flawful.org header.a=rsa-sha256 header.s=mail header.b=TYCkTQFB; dkim=pass (1024-bit key) header.d=flawful.org header.i=@flawful.org header.a=rsa-sha256 header.s=mail header.b=oTJBWr2J; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QcSVP4DYCz20Wn for ; Fri, 9 Jun 2023 01:16:45 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q7HNK-0000Sj-Iu; Thu, 08 Jun 2023 11:16:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q7HNG-0000HG-56; Thu, 08 Jun 2023 11:16:31 -0400 Received: from mail-lf1-x133.google.com ([2a00:1450:4864:20::133]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q7HNE-0000Lt-DS; Thu, 08 Jun 2023 11:16:29 -0400 Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4f62d93f38aso914422e87.0; Thu, 08 Jun 2023 08:16:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686237386; x=1688829386; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature:dkim-signature :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=oyd1ZZA7m/AHJ3cyF1hjSoNsM5QHw15/nooY2h1ILic=; b=TRg9DtfoV2wJHE8+QuhW3sFviyrhOqSZcXiNiDlf6mi6U3ewFR7EMwLTvUl84jND0p 3YJmjo45hVdJ7kDZQcA7HnBPceWjF40e0divB79TM+UQxIrEoBKn1cw6VJwpX7Zy4dKk 1BFBgRml+LkUpsov2JKdU8zJu6MXPLIAE40kiNiW7P3w8QNv4tsefqiSIH3TCrW5dtFV Rk65oEOlvZA3/OcHNZ/nu0MEtMAKMz0bWpdfNRR2F0eNjFbKby/yVezKEWOzti4M6jdy sTCsnpcNufq60tOFURvfJm35OP4qmRSvWgVWrEn6zBW1/3saC4fEaWph2jhqdsm52jOw MdDQ== X-Gm-Message-State: AC+VfDz+BfWndxh7Qbl3FBXPjMJtvgm17VsKtt6sIpysPLxtUPtpiHDd tkyQfanDCtqcuIQC8nMN7egVixhNzt93tOEqOYU= X-Google-Smtp-Source: ACHHUZ6Ztc35WuxNxYcqGpcGm5NSMKfL5yYdFMH/atz7K47wyJ2g539MsfCXxRXwoR3ur+T7UfRObw== X-Received: by 2002:a2e:9b94:0:b0:2a8:ce32:867 with SMTP id z20-20020a2e9b94000000b002a8ce320867mr3547313lji.53.1686237386042; Thu, 08 Jun 2023 08:16:26 -0700 (PDT) Received: from flawful.org (c-f5f0e255.011-101-6d6c6d3.bbcust.telenor.se. [85.226.240.245]) by smtp.gmail.com with ESMTPSA id j21-20020a2e6e15000000b002b1e6a78d3esm285408ljc.82.2023.06.08.08.16.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jun 2023 08:16:25 -0700 (PDT) Received: by flawful.org (Postfix, from userid 112) id 3C414155F; Thu, 8 Jun 2023 17:16:22 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1686237384; bh=KMCa7O4aMdqxNjdQMEzjY2v/i140Djc85D2Q1z90VOw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TYCkTQFBdCL+amv5pmbtwWRCVUdrwVlUD23OMVPiOPQAcovZvffnbzLhUpeXQ98A6 lb/dxd9Z+4oJfLdBxdvUs2+XNhlAXohTSgtMkcBZ2x3QtSWSA1Oc3gI/R0KE8H1vK+ wc43Qk5uDDHDE0CuraBBHDbQE9sN2ODqtS+vqxzo= Received: from x1-carbon.wireless.wdc (unknown [129.253.182.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by flawful.org (Postfix) with ESMTPSA id 418D1148C; Thu, 8 Jun 2023 17:15:48 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1686237352; bh=KMCa7O4aMdqxNjdQMEzjY2v/i140Djc85D2Q1z90VOw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oTJBWr2J4y51t89tjHADpKzMr6+ws9OhNC8PJ5XL/IzTrpjpEggvEypdlpDED1rzT 4NJe4tF1CzgN5MKcg7JceR/pw0oVadmZ22bCuzYa6anofbtJSFWpuLDu9oeDlUcVeV g41JAOvd3cOuy8xSzFEklLQYxEyt4IxkqsWP9O7A= From: Niklas Cassel To: John Snow Cc: qemu-block@nongnu.org, qemu-devel@nongnu.org, Damien Le Moal , Niklas Cassel Subject: [PATCH 2/5] libqos/ahci: fix ahci_port_check_nonbusy() Date: Thu, 8 Jun 2023 17:15:25 +0200 Message-Id: <20230608151528.143950-3-nks@flawful.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230608151528.143950-1-nks@flawful.org> References: <20230608151528.143950-1-nks@flawful.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=nks.gnu@gmail.com; helo=mail-lf1-x133.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Niklas Cassel A command that has ERR_STAT set, does not get to clear PxCI. See AHCI 1.3.1, section 5.3.8, states RegFIS:Entry and RegFIS:ClearCI, and 5.3.16.5 ERR:FatalTaskfile. Some tests, e.g. test_atapi_tray() call ahci_atapi_test_ready() with ready == false, intentionally sending a command that will cause an error. Thus, ahci_port_check_nonbusy() cannot assume that PxCI and PxSACT will always be cleared for the executed command. Signed-off-by: Niklas Cassel --- tests/qtest/libqos/ahci.c | 27 +++++++++++++++++++++------ tests/qtest/libqos/ahci.h | 2 +- 2 files changed, 22 insertions(+), 7 deletions(-) diff --git a/tests/qtest/libqos/ahci.c b/tests/qtest/libqos/ahci.c index c1d571e477..2d4981dae4 100644 --- a/tests/qtest/libqos/ahci.c +++ b/tests/qtest/libqos/ahci.c @@ -444,17 +444,32 @@ void ahci_port_check_interrupts(AHCIQState *ahci, uint8_t port, g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0); } -void ahci_port_check_nonbusy(AHCIQState *ahci, uint8_t port, uint8_t slot) +void ahci_port_check_nonbusy(AHCIQState *ahci, AHCICommand *cmd) { + uint8_t slot = cmd->slot; + uint8_t port = cmd->port; uint32_t reg; - /* Assert that the command slot is no longer busy (NCQ) */ + /* For NCQ command with error PxSACT bit should still be set. + * For NCQ command without error, PxSACT bit should be cleared. + * For non-NCQ command, PxSACT bit should always be cleared. */ reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT); - ASSERT_BIT_CLEAR(reg, (1 << slot)); + if (cmd->props->ncq && cmd->errors) { + ASSERT_BIT_SET(reg, (1 << slot)); + } else { + ASSERT_BIT_CLEAR(reg, (1 << slot)); + } - /* Non-NCQ */ + /* For non-NCQ command with error, PxCI bit should still be set. + * For non-NCQ command without error, PxCI bit should be cleared. + * For NCQ command without error, PxCI bit should be cleared. + * For NCQ command with error, PxCI bit may or may not be cleared. */ reg = ahci_px_rreg(ahci, port, AHCI_PX_CI); - ASSERT_BIT_CLEAR(reg, (1 << slot)); + if (!cmd->props->ncq && cmd->errors) { + ASSERT_BIT_SET(reg, (1 << slot)); + } else if (!cmd->errors) { + ASSERT_BIT_CLEAR(reg, (1 << slot)); + } /* And assert that we are generally not busy. */ reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD); @@ -1229,7 +1244,7 @@ void ahci_command_verify(AHCIQState *ahci, AHCICommand *cmd) ahci_port_check_error(ahci, port, cmd->interrupts, cmd->errors); ahci_port_check_interrupts(ahci, port, cmd->interrupts); - ahci_port_check_nonbusy(ahci, port, slot); + ahci_port_check_nonbusy(ahci, cmd); ahci_port_check_cmd_sanity(ahci, cmd); if (cmd->interrupts & AHCI_PX_IS_DHRS) { ahci_port_check_d2h_sanity(ahci, port, slot); diff --git a/tests/qtest/libqos/ahci.h b/tests/qtest/libqos/ahci.h index 88835b6228..2234f46862 100644 --- a/tests/qtest/libqos/ahci.h +++ b/tests/qtest/libqos/ahci.h @@ -594,7 +594,7 @@ void ahci_port_check_error(AHCIQState *ahci, uint8_t port, uint32_t imask, uint8_t emask); void ahci_port_check_interrupts(AHCIQState *ahci, uint8_t port, uint32_t intr_mask); -void ahci_port_check_nonbusy(AHCIQState *ahci, uint8_t port, uint8_t slot); +void ahci_port_check_nonbusy(AHCIQState *ahci, AHCICommand *cmd); void ahci_port_check_d2h_sanity(AHCIQState *ahci, uint8_t port, uint8_t slot); void ahci_port_check_pio_sanity(AHCIQState *ahci, AHCICommand *cmd); void ahci_port_check_cmd_sanity(AHCIQState *ahci, AHCICommand *cmd); From patchwork Thu Jun 8 15:15:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1792360 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[85.226.240.245]) by smtp.gmail.com with ESMTPSA id d19-20020ac244d3000000b004f37b88eacfsm217043lfm.187.2023.06.08.08.16.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jun 2023 08:16:26 -0700 (PDT) Received: by flawful.org (Postfix, from userid 112) id 40BED148C; Thu, 8 Jun 2023 17:16:24 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1686237385; bh=a5SkxRTfz+p1TvOllAPLUVa9px3KY3l+AXj78TtaLFE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ixSXKW96olrnQ6/8QmhFMT5kkcFvGrFD2bFDxOMBiMoF90GcYESAcnaOceGznCDe3 6Pt6oTyr+N+6hLsLYEWl3x58Gz7v6TrxwSCrArSanCZzckz5E8JihPMvSWqdKaJUn/ WSOv0YkiXtyH2RtVpcEEvpRNVxxOFYUDaIESXEQQ= Received: from x1-carbon.wireless.wdc (unknown [129.253.182.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by flawful.org (Postfix) with ESMTPSA id EAFF212FF; Thu, 8 Jun 2023 17:15:54 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1686237358; bh=a5SkxRTfz+p1TvOllAPLUVa9px3KY3l+AXj78TtaLFE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XyeTqJpRgCECiEMYrDfi+nGAOEO6RM1Gto3vr1gUH+DsODFDzB7a2Yu/FznEKFx+W 8/A8YIxUMh4YdXiHCgaNSK15BrVw5IozXeSO8gA1HUCcLOvRNwuQr4of5S85s7CjP+ +Lyy8zxxX9FMe/zNBU1spp8tMc0bxbURwfhFFwJo= From: Niklas Cassel To: John Snow Cc: qemu-block@nongnu.org, qemu-devel@nongnu.org, Damien Le Moal , Niklas Cassel Subject: [PATCH 3/5] libqos/ahci: simplify ahci_port_check_error() Date: Thu, 8 Jun 2023 17:15:26 +0200 Message-Id: <20230608151528.143950-4-nks@flawful.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230608151528.143950-1-nks@flawful.org> References: <20230608151528.143950-1-nks@flawful.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=nks.gnu@gmail.com; helo=mail-lf1-x131.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Niklas Cassel Modify ahci_port_check_error() to simply take a struct AHCICommand. This way, the conditionals are in line which the existing code, e.g. ahci_port_check_nonbusy(), which checks for cmd->errors. This makes the code easier to reason with, we don't want to use cmd->errors in some functions and emask in some functions. No functional changes intended. Signed-off-by: Niklas Cassel --- tests/qtest/libqos/ahci.c | 14 +++++++------- tests/qtest/libqos/ahci.h | 3 +-- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/tests/qtest/libqos/ahci.c b/tests/qtest/libqos/ahci.c index 2d4981dae4..644ed7e79f 100644 --- a/tests/qtest/libqos/ahci.c +++ b/tests/qtest/libqos/ahci.c @@ -404,14 +404,14 @@ void ahci_port_clear(AHCIQState *ahci, uint8_t port) /** * Check a port for errors. */ -void ahci_port_check_error(AHCIQState *ahci, uint8_t port, - uint32_t imask, uint8_t emask) +void ahci_port_check_error(AHCIQState *ahci, AHCICommand *cmd) { + uint8_t port = cmd->port; uint32_t reg; /* The upper 9 bits of the IS register all indicate errors. */ reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); - reg &= ~imask; + reg &= ~cmd->interrupts; reg >>= 23; g_assert_cmphex(reg, ==, 0); @@ -421,13 +421,13 @@ void ahci_port_check_error(AHCIQState *ahci, uint8_t port, /* The TFD also has two error sections. */ reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD); - if (!emask) { + if (!cmd->errors) { ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_ERR); } else { ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR); } - ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR & (~emask << 8)); - ASSERT_BIT_SET(reg, AHCI_PX_TFD_ERR & (emask << 8)); + ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR & (~cmd->errors << 8)); + ASSERT_BIT_SET(reg, AHCI_PX_TFD_ERR & (cmd->errors << 8)); } void ahci_port_check_interrupts(AHCIQState *ahci, uint8_t port, @@ -1242,7 +1242,7 @@ void ahci_command_verify(AHCIQState *ahci, AHCICommand *cmd) uint8_t slot = cmd->slot; uint8_t port = cmd->port; - ahci_port_check_error(ahci, port, cmd->interrupts, cmd->errors); + ahci_port_check_error(ahci, cmd); ahci_port_check_interrupts(ahci, port, cmd->interrupts); ahci_port_check_nonbusy(ahci, cmd); ahci_port_check_cmd_sanity(ahci, cmd); diff --git a/tests/qtest/libqos/ahci.h b/tests/qtest/libqos/ahci.h index 2234f46862..137858d79c 100644 --- a/tests/qtest/libqos/ahci.h +++ b/tests/qtest/libqos/ahci.h @@ -590,8 +590,7 @@ void ahci_set_command_header(AHCIQState *ahci, uint8_t port, void ahci_destroy_command(AHCIQState *ahci, uint8_t port, uint8_t slot); /* AHCI sanity check routines */ -void ahci_port_check_error(AHCIQState *ahci, uint8_t port, - uint32_t imask, uint8_t emask); +void ahci_port_check_error(AHCIQState *ahci, AHCICommand *cmd); void ahci_port_check_interrupts(AHCIQState *ahci, uint8_t port, uint32_t intr_mask); void ahci_port_check_nonbusy(AHCIQState *ahci, AHCICommand *cmd); From patchwork Thu Jun 8 15:15:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1792361 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=flawful.org header.i=@flawful.org header.a=rsa-sha256 header.s=mail header.b=BeLppSoT; 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[85.226.240.245]) by smtp.gmail.com with ESMTPSA id b11-20020ac2562b000000b004f63d35d396sm213003lff.250.2023.06.08.08.16.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jun 2023 08:16:34 -0700 (PDT) Received: by flawful.org (Postfix, from userid 112) id F375B1474; Thu, 8 Jun 2023 17:16:33 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1686237394; bh=qHEpLcC2bs/b4ArbT2xps8PdOQ8V+R2bzrWbKodWxrA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BeLppSoTfqkZUKnWHGUUY00Z/vFNFbiRHUUlM43if2EnjnUr3dVg20wa42qbb7hCX nXlJ6SbI69GLOHqYmUKqBkPK5n4TH1Nflfr+SyaW/IVE+fSeOBPTmjwhNCI4RGNrbb FIfXH2JXx++M88MZ40LSiWASICmNq2nu2nU1g+AY= Received: from x1-carbon.wireless.wdc (unknown [129.253.182.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by flawful.org (Postfix) with ESMTPSA id 6203A1403; Thu, 8 Jun 2023 17:16:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1686237366; bh=qHEpLcC2bs/b4ArbT2xps8PdOQ8V+R2bzrWbKodWxrA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SJwEUjpdCzAqPvetreMeTVa2+gkCYtL73ZAFGuj+O/y/8cmYFCtG0KL9kinK3klKT 0E8qLDLND913MlTpQ3ZyDns8KKKJh9XTlFrqsfS8MwsuZ14GINn8UJ0Ci9unFi79JO cMIa3pv2/JAPYMt+SYhh5QGt73q5iFmr8dZ9wou8= From: Niklas Cassel To: John Snow Cc: qemu-block@nongnu.org, qemu-devel@nongnu.org, Damien Le Moal , Niklas Cassel Subject: [PATCH 4/5] libqos/ahci: improve ahci_port_check_error() Date: Thu, 8 Jun 2023 17:15:27 +0200 Message-Id: <20230608151528.143950-5-nks@flawful.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230608151528.143950-1-nks@flawful.org> References: <20230608151528.143950-1-nks@flawful.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=nks.gnu@gmail.com; helo=mail-lf1-x135.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Niklas Cassel Improve ahci_port_check_error() to also assert that PxIS.TFES is set when expecting errors. Signed-off-by: Niklas Cassel --- tests/qtest/libqos/ahci.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/tests/qtest/libqos/ahci.c b/tests/qtest/libqos/ahci.c index 644ed7e79f..b216f61f14 100644 --- a/tests/qtest/libqos/ahci.c +++ b/tests/qtest/libqos/ahci.c @@ -409,13 +409,19 @@ void ahci_port_check_error(AHCIQState *ahci, AHCICommand *cmd) uint8_t port = cmd->port; uint32_t reg; - /* The upper 9 bits of the IS register all indicate errors. */ - reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); - reg &= ~cmd->interrupts; - reg >>= 23; - g_assert_cmphex(reg, ==, 0); + /* If expecting TF error, ensure that TFES is set. */ + if (cmd->errors) { + reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); + ASSERT_BIT_SET(reg, AHCI_PX_IS_TFES); + } else { + /* The upper 9 bits of the IS register all indicate errors. */ + reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); + reg &= ~cmd->interrupts; + reg >>= 23; + g_assert_cmphex(reg, ==, 0); + } - /* The Sata Error Register should be empty. */ + /* The Sata Error Register should be empty, even when expecting TF error. */ reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR); g_assert_cmphex(reg, ==, 0); From patchwork Thu Jun 8 15:15:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1792364 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=flawful.org header.i=@flawful.org header.a=rsa-sha256 header.s=mail header.b=KTKhx16J; dkim=pass (1024-bit key) header.d=flawful.org header.i=@flawful.org header.a=rsa-sha256 header.s=mail header.b=t8SF7Eoc; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QcSWN4sjDz20Wn for ; Fri, 9 Jun 2023 01:17:36 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q7HO1-0001fX-TH; Thu, 08 Jun 2023 11:17:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q7HNo-0001D6-ER; Thu, 08 Jun 2023 11:17:04 -0400 Received: from mail-lf1-x133.google.com ([2a00:1450:4864:20::133]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q7HNk-0000RN-Ro; Thu, 08 Jun 2023 11:17:03 -0400 Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4f61d79b0f2so908902e87.3; Thu, 08 Jun 2023 08:16:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686237415; x=1688829415; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature:dkim-signature :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=4wsnlAkJObVDEQrtDWr3eBzH6P5Qhy1QwLNGwN1nHhc=; b=dNuIFWS2SK4GoaMuNdHVBZEzg2B2CeICTLNv68NbwHjrU4eza7zQvvTsJCRC6DM9Xu 5eRpsAq76+l+/ybmAJ4DQ0EW0iK8JCvyY27jaVmeiwK+d6C5n3ZrmjQrolKhIJkPw+Di ACadLU2NisM8M/DyZFhua9hTHBwq5IJ1vXTBsjl0MJXtIgn1NkW2O6c4ef67Rh3OBPTq LPt0G5NVEUZdJQB2o+o1sz5+COmX/rxEBeqtCDjw6hLipCkaKdMLETr3wrNX2ojLNOJ4 KfmHPh9QPck0gffDv3LAzRci3P93a57roCW0e1GP538OdxfZxHP3Lyd0CA/IdShxUQpl disQ== X-Gm-Message-State: AC+VfDy2j5LJWHMXfgEeUQU51r9XUpU1MzGnN2riEYP1oxRMXlXj3JHK lc4daRPyIr+iWVdYwQgIqLpRABpPkpXP6E2VkIs= X-Google-Smtp-Source: ACHHUZ7hxAUlfl/74vaC9daxciR+5Dp/D27YXP3q1ptftfeWKxuzGZwmxNxh2CupjOCsF7/1aN/nMQ== X-Received: by 2002:ac2:43c8:0:b0:4f4:2b83:f4a3 with SMTP id u8-20020ac243c8000000b004f42b83f4a3mr3164896lfl.51.1686237414948; Thu, 08 Jun 2023 08:16:54 -0700 (PDT) Received: from flawful.org (c-f5f0e255.011-101-6d6c6d3.bbcust.telenor.se. [85.226.240.245]) by smtp.gmail.com with ESMTPSA id d15-20020ac2544f000000b004f62771eed4sm214000lfn.300.2023.06.08.08.16.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jun 2023 08:16:54 -0700 (PDT) Received: by flawful.org (Postfix, from userid 112) id C430012F3; Thu, 8 Jun 2023 17:16:52 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1686237413; bh=Cmjam1Ms+un7s+nyCpGIwgVVjGdS79mfE/ZWH8XfDV8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KTKhx16JGZc6+paU+qUzQvYNybdkgxM1JJF20y4yTKYOsfB5LJsVDZsPFxmzBi5KE j8S2GXizFYkhi4xy8jVa0JC/DOltPIhllwvSmmV+XALShJNUSouHTHZJZbquv7ZEDk 9YiQ7KWY5byPGHZEaQaN5Zq39ODBMMo9pXzK/G7E= Received: from x1-carbon.wireless.wdc (unknown [129.253.182.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by flawful.org (Postfix) with ESMTPSA id 01F1612C6; Thu, 8 Jun 2023 17:16:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1686237371; bh=Cmjam1Ms+un7s+nyCpGIwgVVjGdS79mfE/ZWH8XfDV8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=t8SF7EocoNdNU3+8/uQ3/feCn4cwYITSXtGn3V28j5GPRRTs4CChwigOOy24pOlrG CTcoVf4Rn8kK6GkFBcHe0adtZ2coXtb8bJJs4Fltt0nIW+K6hvvQ4qIZD+SQfcHhER 10DetK93ajud+omBOrd/CiQXNSHTvx1xbPYQ3btg= From: Niklas Cassel To: John Snow Cc: qemu-block@nongnu.org, qemu-devel@nongnu.org, Damien Le Moal , Niklas Cassel Subject: [PATCH 5/5] libqos/ahci: perform mandatory error recovery on error Date: Thu, 8 Jun 2023 17:15:28 +0200 Message-Id: <20230608151528.143950-6-nks@flawful.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230608151528.143950-1-nks@flawful.org> References: <20230608151528.143950-1-nks@flawful.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=nks.gnu@gmail.com; helo=mail-lf1-x133.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Niklas Cassel When the HBA encouters an error, the host has to perform error recovery, see AHCI 1.3.1 section 6.2.2.1, in order to be able issue new commands. If we don't do this, all the commands that we queue will get aborted. Some tests, e.g. test_atapi_tray() call ahci_atapi_test_ready() with ready == false, intentionally sending a command that will cause an error. After test_atapi_tray() has called ahci_atapi_test_ready(), it directly calls ahci_atapi_get_sense() to send a REQUEST SENSE command. If we don't perform error recovery, the REQUEST SENSE command will get aborted, and will not return the sense data that the test case expects. Since the error recovery will clear PxCI, we also need to move the ahci_port_check_nonbusy() call to before the error handling takes place. Signed-off-by: Niklas Cassel --- tests/qtest/libqos/ahci.c | 44 +++++++++++++++++++++++++++++++++------ tests/qtest/libqos/ahci.h | 3 +-- 2 files changed, 39 insertions(+), 8 deletions(-) diff --git a/tests/qtest/libqos/ahci.c b/tests/qtest/libqos/ahci.c index b216f61f14..a2c94c6e06 100644 --- a/tests/qtest/libqos/ahci.c +++ b/tests/qtest/libqos/ahci.c @@ -425,6 +425,31 @@ void ahci_port_check_error(AHCIQState *ahci, AHCICommand *cmd) reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR); g_assert_cmphex(reg, ==, 0); + /* If expecting TF error, and TFES was set, perform error recovery + * (see AHCI 1.3 section 6.2.2.1) such that we can send new commands. */ + if (cmd->errors) { + /* This will clear PxCI. */ + ahci_px_clr(ahci, port, AHCI_PX_CMD, AHCI_PX_CMD_ST); + + /* The port has 500ms to disengage. */ + usleep(500000); + reg = ahci_px_rreg(ahci, port, AHCI_PX_CMD); + ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR); + + /* Clear PxIS. */ + reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); + ahci_px_wreg(ahci, port, AHCI_PX_IS, reg); + + /* Check if we need to perform a COMRESET. + * Not implemented right now, as there is no reason why our QEMU model + * should need a COMRESET when expecting TF error. */ + reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD); + ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY | AHCI_PX_TFD_STS_DRQ); + + /* Enable issuing new commands. */ + ahci_px_set(ahci, port, AHCI_PX_CMD, AHCI_PX_CMD_ST); + } + /* The TFD also has two error sections. */ reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD); if (!cmd->errors) { @@ -436,17 +461,24 @@ void ahci_port_check_error(AHCIQState *ahci, AHCICommand *cmd) ASSERT_BIT_SET(reg, AHCI_PX_TFD_ERR & (cmd->errors << 8)); } -void ahci_port_check_interrupts(AHCIQState *ahci, uint8_t port, - uint32_t intr_mask) +void ahci_port_check_interrupts(AHCIQState *ahci, AHCICommand *cmd) { + uint8_t port = cmd->port; uint32_t reg; + /* If we expect errors, error handling in ahci_port_check_error() will + * already have cleared PxIS, so in that case this function cannot verify + * and clear expected interrupts. */ + if (cmd->errors) { + return; + } + /* Check for expected interrupts */ reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); - ASSERT_BIT_SET(reg, intr_mask); + ASSERT_BIT_SET(reg, cmd->interrupts); /* Clear expected interrupts and assert all interrupts now cleared. */ - ahci_px_wreg(ahci, port, AHCI_PX_IS, intr_mask); + ahci_px_wreg(ahci, port, AHCI_PX_IS, cmd->interrupts); g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0); } @@ -1248,9 +1280,9 @@ void ahci_command_verify(AHCIQState *ahci, AHCICommand *cmd) uint8_t slot = cmd->slot; uint8_t port = cmd->port; - ahci_port_check_error(ahci, cmd); - ahci_port_check_interrupts(ahci, port, cmd->interrupts); ahci_port_check_nonbusy(ahci, cmd); + ahci_port_check_error(ahci, cmd); + ahci_port_check_interrupts(ahci, cmd); ahci_port_check_cmd_sanity(ahci, cmd); if (cmd->interrupts & AHCI_PX_IS_DHRS) { ahci_port_check_d2h_sanity(ahci, port, slot); diff --git a/tests/qtest/libqos/ahci.h b/tests/qtest/libqos/ahci.h index 137858d79c..48017864bf 100644 --- a/tests/qtest/libqos/ahci.h +++ b/tests/qtest/libqos/ahci.h @@ -591,8 +591,7 @@ void ahci_destroy_command(AHCIQState *ahci, uint8_t port, uint8_t slot); /* AHCI sanity check routines */ void ahci_port_check_error(AHCIQState *ahci, AHCICommand *cmd); -void ahci_port_check_interrupts(AHCIQState *ahci, uint8_t port, - uint32_t intr_mask); +void ahci_port_check_interrupts(AHCIQState *ahci, AHCICommand *cmd); void ahci_port_check_nonbusy(AHCIQState *ahci, AHCICommand *cmd); void ahci_port_check_d2h_sanity(AHCIQState *ahci, uint8_t port, uint8_t slot); void ahci_port_check_pio_sanity(AHCIQState *ahci, AHCICommand *cmd);