From patchwork Fri Apr 14 16:01:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mayuresh Chitale X-Patchwork-Id: 1769103 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=CKbl05Ew; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Pyh7c13WQz1yZr for ; Sat, 15 Apr 2023 02:03:22 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pnLt5-0002BY-V2; Fri, 14 Apr 2023 12:02:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pnLsk-0001mo-Ms for qemu-devel@nongnu.org; Fri, 14 Apr 2023 12:02:38 -0400 Received: from mail-oa1-x35.google.com ([2001:4860:4864:20::35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pnLsh-0007GH-ET for qemu-devel@nongnu.org; Fri, 14 Apr 2023 12:02:38 -0400 Received: by mail-oa1-x35.google.com with SMTP id 586e51a60fabf-187bee46f9dso796622fac.11 for ; Fri, 14 Apr 2023 09:02:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1681488152; x=1684080152; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WQVbdHSbmA0N99G9XPF6TNlMG0xte3LZeN6z59ov+BU=; b=CKbl05EwbGpv1672ElGDinynLnpWITeK/Hz8LH139VwpFsQhoH0fYmpOVvVuwqafXZ xgV4FXJYtLjI2slkG/JXrF6vw4d7rXNcm3BAiUpJiRbWxMglwxRu5RDHlFXPnRzOGEa1 8C8fRol7vENWicDA7rh0AyWwA9ZEZR86GAkMy65ieOEnlrG+5mcX9NVvjdK+M01LxZS3 fcrHOJojI4lMBfCMOqw2LgRLbLBdkdXcJE1MiYevAzEjt0Eqd1EB+DhG2U3B5GUjnQzu lwLBu4McBJCAuYNwi2ykudGtAk1LrbB0OFvKIF+IqCy+CzIX5Gj/3tQI9irgsE6sH6mG 4LhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681488152; x=1684080152; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WQVbdHSbmA0N99G9XPF6TNlMG0xte3LZeN6z59ov+BU=; b=da6UfT88Lcs+3trMvZ26vj4uA5zpynvCXNE4AIXMIZaZbvSsa741RLYYhwkldEamSm Cll956ZobMUp9XhmgkqWUB0a/39sNHld/4BrQohSSbTB9dIRAZga1PX/yalod61HRx29 ElLfydLCzXUmeOGpdGGgGSGH4L29VfKA9vVQEA1zDa7z3uDwC17nDxDtHuPWaxofNfPn rFQfjbze/ggye+ZajIlYsxQvytiERaTyM/PfTod/sj4vEjwYZ5fqFb6z9aeFAQqSfXyG Fssmyv2iz86vt6nHogEcFqh+09r24vyINaaRbz5BncX34lieKo5v36EbC7XWawaSoyxE UDAQ== X-Gm-Message-State: AAQBX9eOGYYTzy0NTpUrestdOzoEaKnYnrvAVhzRXbx2KMPexnZ5RJdH ePwlZDDjhwmMxv6IfyOio58wEKLWQQ7yxZnh+m/NmQ== X-Google-Smtp-Source: AKy350ag/su92qFhP7++e91lFdSfaje/inSkP2rzTqQ911z55exq5oB6Q7CTv/Szx0Zwd+eEnNVFRQ== X-Received: by 2002:a05:6870:14d2:b0:17f:7dca:8926 with SMTP id l18-20020a05687014d200b0017f7dca8926mr4181249oab.20.1681488152316; Fri, 14 Apr 2023 09:02:32 -0700 (PDT) Received: from mchitale-vm.. ([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id u6-20020a4a5706000000b00524fe20aee5sm1794323ooa.34.2023.04.14.09.02.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 09:02:32 -0700 (PDT) From: Mayuresh Chitale To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Cc: Mayuresh Chitale , Alistair Francis , Daniel Barboza , liweiwei@iscas.ac.cn, Richard Henderson Subject: [RFC PATCH v2 1/4] target/riscv: smstateen check for fcsr Date: Fri, 14 Apr 2023 21:31:59 +0530 Message-Id: <20230414160202.1298242-2-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230414160202.1298242-1-mchitale@ventanamicro.com> References: <20230414160202.1298242-1-mchitale@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::35; envelope-from=mchitale@ventanamicro.com; helo=mail-oa1-x35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org If smstateen is implemented and smtateen0.fcsr is clear and misa.F is off then the floating point operations must return illegal instruction exception or virtual instruction trap, if relevant. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f4d2dcfdc8..8ae9e95f9f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -82,6 +82,10 @@ static RISCVException fs(CPURISCVState *env, int csrno) !riscv_cpu_cfg(env)->ext_zfinx) { return RISCV_EXCP_ILLEGAL_INST; } + + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { + return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR); + } #endif return RISCV_EXCP_NONE; } @@ -2081,6 +2085,9 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno, target_ulong new_val) { uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; + if (!riscv_has_ext(env, RVF)) { + wr_mask |= SMSTATEEN0_FCSR; + } return write_mstateen(env, csrno, wr_mask, new_val); } @@ -2117,6 +2124,10 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, { uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; + if (!riscv_has_ext(env, RVF)) { + wr_mask |= SMSTATEEN0_FCSR; + } + return write_mstateenh(env, csrno, wr_mask, new_val); } @@ -2154,6 +2165,10 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno, { uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; + if (!riscv_has_ext(env, RVF)) { + wr_mask |= SMSTATEEN0_FCSR; + } + return write_hstateen(env, csrno, wr_mask, new_val); } @@ -2193,6 +2208,10 @@ static RISCVException write_hstateen0h(CPURISCVState *env, int csrno, { uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; + if (!riscv_has_ext(env, RVF)) { + wr_mask |= SMSTATEEN0_FCSR; + } + return write_hstateenh(env, csrno, wr_mask, new_val); } @@ -2240,6 +2259,10 @@ static RISCVException write_sstateen0(CPURISCVState *env, int csrno, { uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; + if (!riscv_has_ext(env, RVF)) { + wr_mask |= SMSTATEEN0_FCSR; + } + return write_sstateen(env, csrno, wr_mask, new_val); } From patchwork Fri Apr 14 16:02:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mayuresh Chitale X-Patchwork-Id: 1769104 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id u6-20020a4a5706000000b00524fe20aee5sm1794323ooa.34.2023.04.14.09.02.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 09:02:39 -0700 (PDT) From: Mayuresh Chitale To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Cc: Mayuresh Chitale , Alistair Francis , Daniel Barboza , liweiwei@iscas.ac.cn, Richard Henderson Subject: [RFC PATCH v2 2/4] target/riscv: Reuse TB_FLAGS.MSTATUS_HFS_FS Date: Fri, 14 Apr 2023 21:32:00 +0530 Message-Id: <20230414160202.1298242-3-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230414160202.1298242-1-mchitale@ventanamicro.com> References: <20230414160202.1298242-1-mchitale@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::30; envelope-from=mchitale@ventanamicro.com; helo=mail-oa1-x30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org When misa.F is clear, TB_FLAGS.MSTATUS_HS_FS field is unused and can be used to save the current state of smstateen0.FCSR check which is needed by the floating point translation routines. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li --- target/riscv/cpu_helper.c | 12 ++++++++++++ target/riscv/translate.c | 7 +++++++ 2 files changed, 19 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 433ea529b0..fd1731cc39 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -105,6 +105,18 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, get_field(env->mstatus_hs, MSTATUS_VS)); } + /* + * If misa.F is 0 then the MSTATUS_HS_FS field of the tb->flags + * can be used to pass the current state of the smstateen.FCSR bit + * which must be checked for in the floating point translation routines + */ + if (!riscv_has_ext(env, RVF)) { + if (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE) { + flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, 1); + } else { + flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, 0); + } + } if (cpu->cfg.debug && !icount_enabled()) { flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d0094922b6..e29bbb8b70 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -79,6 +79,7 @@ typedef struct DisasContext { int frm; RISCVMXL ol; bool virt_inst_excp; + bool smstateen_fcsr_ok; bool virt_enabled; const RISCVCPUConfig *cfg_ptr; bool hlsx; @@ -1202,6 +1203,12 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->zero = tcg_constant_tl(0); ctx->virt_inst_excp = false; + if (has_ext(ctx, RVF)) { + ctx->smstateen_fcsr_ok = 1; + } else { + ctx->smstateen_fcsr_ok = FIELD_EX32(tb_flags, TB_FLAGS, + MSTATUS_HS_FS); + } } static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) From patchwork Fri Apr 14 16:02:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mayuresh Chitale X-Patchwork-Id: 1769107 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id u6-20020a4a5706000000b00524fe20aee5sm1794323ooa.34.2023.04.14.09.02.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 09:02:46 -0700 (PDT) From: Mayuresh Chitale To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Cc: Mayuresh Chitale , Alistair Francis , Daniel Barboza , liweiwei@iscas.ac.cn, Richard Henderson Subject: [RFC PATCH v2 3/4] target/riscv: check smstateen fcsr flag Date: Fri, 14 Apr 2023 21:32:01 +0530 Message-Id: <20230414160202.1298242-4-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230414160202.1298242-1-mchitale@ventanamicro.com> References: <20230414160202.1298242-1-mchitale@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::30; envelope-from=mchitale@ventanamicro.com; helo=mail-oa1-x30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org If misa.F and smstateen_fcsr_ok flag are clear then all the floating point instructions must generate an appropriate exception. Signed-off-by: Mayuresh Chitale --- target/riscv/insn_trans/trans_rvd.c.inc | 13 ++++++++---- target/riscv/insn_trans/trans_rvf.c.inc | 24 +++++++++++++++++++---- target/riscv/insn_trans/trans_rvzfh.c.inc | 18 ++++++++++++++--- 3 files changed, 44 insertions(+), 11 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc index 2c51e01c40..d9e0cf116f 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -18,10 +18,15 @@ * this program. If not, see . */ -#define REQUIRE_ZDINX_OR_D(ctx) do { \ - if (!ctx->cfg_ptr->ext_zdinx) { \ - REQUIRE_EXT(ctx, RVD); \ - } \ +#define REQUIRE_ZDINX_OR_D(ctx) do { \ + if (!has_ext(ctx, RVD)) { \ + if (!ctx->cfg_ptr->ext_zdinx) { \ + return false; \ + } \ + if (!smstateen_fcsr_check(ctx)) { \ + return false; \ + } \ + } \ } while (0) #define REQUIRE_EVEN(ctx, reg) do { \ diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index 9e9fa2087a..6bf6fe16be 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -24,10 +24,26 @@ return false; \ } while (0) -#define REQUIRE_ZFINX_OR_F(ctx) do {\ - if (!ctx->cfg_ptr->ext_zfinx) { \ - REQUIRE_EXT(ctx, RVF); \ - } \ +static inline bool smstateen_fcsr_check(DisasContext *ctx) +{ +#ifndef CONFIG_USER_ONLY + if (!has_ext(ctx, RVF) && !ctx->smstateen_fcsr_ok) { + ctx->virt_inst_excp = ctx->virt_enabled; + return false; + } +#endif + return true; +} + +#define REQUIRE_ZFINX_OR_F(ctx) do { \ + if (!has_ext(ctx, RVF)) { \ + if (!ctx->cfg_ptr->ext_zfinx) { \ + return false; \ + } \ + if (!smstateen_fcsr_check(ctx)) { \ + return false; \ + } \ + } \ } while (0) #define REQUIRE_ZCF(ctx) do { \ diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc index 74dde37ff7..74a125e4c0 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -16,28 +16,40 @@ * this program. If not, see . */ -#define REQUIRE_ZFH(ctx) do { \ +#define REQUIRE_ZFH(ctx) do { \ if (!ctx->cfg_ptr->ext_zfh) { \ - return false; \ - } \ + return false; \ + } \ + if (!smstateen_fcsr_check(ctx)) { \ + return false; \ + } \ } while (0) #define REQUIRE_ZHINX_OR_ZFH(ctx) do { \ if (!ctx->cfg_ptr->ext_zhinx && !ctx->cfg_ptr->ext_zfh) { \ return false; \ } \ + if (!smstateen_fcsr_check(ctx)) { \ + return false; \ + } \ } while (0) #define REQUIRE_ZFHMIN(ctx) do { \ if (!ctx->cfg_ptr->ext_zfhmin) { \ return false; \ } \ + if (!smstateen_fcsr_check(ctx)) { \ + return false; \ + } \ } while (0) #define REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx) do { \ if (!(ctx->cfg_ptr->ext_zfhmin || ctx->cfg_ptr->ext_zhinxmin)) { \ return false; \ } \ + if (!smstateen_fcsr_check(ctx)) { \ + return false; \ + } \ } while (0) static bool trans_flh(DisasContext *ctx, arg_flh *a) From patchwork Fri Apr 14 16:02:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mayuresh Chitale X-Patchwork-Id: 1769106 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=LZiXPXOX; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Pyh7r6Tqxz1yZr for ; Sat, 15 Apr 2023 02:03:36 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pnLt7-0002Gv-LT; Fri, 14 Apr 2023 12:03:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pnLt5-0002A3-Ck for qemu-devel@nongnu.org; Fri, 14 Apr 2023 12:02:59 -0400 Received: from mail-oa1-x33.google.com ([2001:4860:4864:20::33]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pnLt2-0007LQ-LB for qemu-devel@nongnu.org; Fri, 14 Apr 2023 12:02:59 -0400 Received: by mail-oa1-x33.google.com with SMTP id 586e51a60fabf-187878a90e6so8465329fac.0 for ; Fri, 14 Apr 2023 09:02:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1681488173; x=1684080173; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zEmvHHbBbKmeVHVaRiMbrmPg34zyJnxsV36tsik2vpc=; b=LZiXPXOXUfDfy8ihUPmUThWiyrIlRBBpdaR4HVD6IU0Zr/6SDPnZAczT/53674Sp+H ydLGG+RpJZS0DMdqPYzYuFZbA47019jUyxUgvgnl9Zj1RMvwVdxLPfHxAN4SRwlLP0rz Hlc8Ho6r448E/D+RQ+GWQ4yBq23BXHVEadi6MurXLO2HpDd2GN5zIoweMI6YKHoJpWsu bO2s9D9QYwcxDDKFj6Bxf7mOK02IgJLsrLGsNLnVo5FYiNvXjD6PALgp/qAZtt+iwW0K qfnn/PrOGmf+JrrPwe5NqHfgXuBI/6GmVm6QY/nQPUmeIYrB0d+8f/YMFy1n3AWKS4Hi Bqug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681488173; x=1684080173; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zEmvHHbBbKmeVHVaRiMbrmPg34zyJnxsV36tsik2vpc=; b=O1FhCB65rUeXFghzHioxBz2j1fA7M8NqpHe0cf/LFGRhBhcCfNF21bqkanFAWldu+H J3rM/WjGBZ/J8YgUo0IqRN6NF6gzwPRuWlrrvnuT8XL1CmiLNJl5FEvgMc60pyjBWxOC pXiXiHUehDGdP3m75NMG5x1hlDSsR21g7yMEbTQGiCDoksr2oaJj4wI81YY+LZje8WsB 9012FthO/M6Buy3dUV61FaZicEuzDm/oNtRE4w6QzRr0QgZhuRIcGQr9UHjhM6ZCfWhN aAT///y6k29C2Zl+AVTq6aQbPmOqHX/tgi9Z+3JmjbXNZBKBYIWSoOLTo1CLDX2ly3BZ 0QLw== X-Gm-Message-State: AAQBX9eUvKfsrHhrUaKu56QfHXc64sFoRmkPLUwCUr/gQMJkHMny/w7k b5YaY8PU8ecFHRupI6mBL0VG8PvuYXJ27ZH+2mVbNg== X-Google-Smtp-Source: AKy350Z3eqfxueJTtDn0vUbSkyrfNwMwP8AcxnZauPVDcqBMJKe6fNG/1Fr1bQtdR+UKHporNa++ow== X-Received: by 2002:a05:6870:4722:b0:187:98c4:2766 with SMTP id b34-20020a056870472200b0018798c42766mr3673563oaq.14.1681488173757; Fri, 14 Apr 2023 09:02:53 -0700 (PDT) Received: from mchitale-vm.. ([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id u6-20020a4a5706000000b00524fe20aee5sm1794323ooa.34.2023.04.14.09.02.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 09:02:53 -0700 (PDT) From: Mayuresh Chitale To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Cc: Mayuresh Chitale , Alistair Francis , Daniel Barboza , liweiwei@iscas.ac.cn, Richard Henderson Subject: [RFC PATCH v2 4/4] target/riscv: smstateen knobs Date: Fri, 14 Apr 2023 21:32:02 +0530 Message-Id: <20230414160202.1298242-5-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230414160202.1298242-1-mchitale@ventanamicro.com> References: <20230414160202.1298242-1-mchitale@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::33; envelope-from=mchitale@ventanamicro.com; helo=mail-oa1-x33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add knobs to allow users to enable smstateen and also export it via the ISA extension string. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fab38859ec..5c00106899 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -119,6 +119,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), + ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), @@ -1498,8 +1499,8 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), + DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false), DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), - DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),