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[61.68.215.123]) by smtp.gmail.com with ESMTPSA id jc11-20020a17090325cb00b001a1abc93eabsm10609438plb.226.2023.03.22.19.22.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Mar 2023 19:22:46 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org Subject: [PATCH 1/6] target/ppc: Fix width of some 32-bit SPRs Date: Thu, 23 Mar 2023 12:22:32 +1000 Message-Id: <20230323022237.1807512-1-npiggin@gmail.com> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Some 32-bit SPRs are incorrectly implemented as 64-bits on 64-bit targets. This changes VRSAVE, DSISR, HDSISR, DAWRX0, PIDR, LPIDR, DEXCR, HDEXCR, CTRL, TSCR, MMCRH, and PMC[1-6] from to be 32-bit registers. This only goes by the 32/64 classification in the architecture, it does not try to implement finer details of SPR implementation (e.g., not all bits implemented as simple read/write storage). Signed-off-by: Nicholas Piggin --- target/ppc/cpu_init.c | 18 +++++++++--------- target/ppc/helper_regs.c | 2 +- target/ppc/misc_helper.c | 4 ++-- target/ppc/power8-pmu.c | 2 +- target/ppc/translate.c | 2 +- 5 files changed, 14 insertions(+), 14 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 0ce2e3c91d..5aa0b3f0f1 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5085,8 +5085,8 @@ static void register_book3s_altivec_sprs(CPUPPCState *env) } spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", - &spr_read_generic, &spr_write_generic, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic32, + &spr_read_generic, &spr_write_generic32, KVM_REG_PPC_VRSAVE, 0x00000000); } @@ -5120,7 +5120,7 @@ static void register_book3s_207_dbg_sprs(CPUPPCState *env) spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic32, KVM_REG_PPC_DAWRX, 0x00000000); spr_register_kvm_hv(env, SPR_CIABR, "CIABR", SPR_NOACCESS, SPR_NOACCESS, @@ -5376,7 +5376,7 @@ static void register_book3s_ids_sprs(CPUPPCState *env) spr_register_hv(env, SPR_TSCR, "TSCR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic32, 0x00000000); spr_register_hv(env, SPR_HMER, "HMER", SPR_NOACCESS, SPR_NOACCESS, @@ -5406,7 +5406,7 @@ static void register_book3s_ids_sprs(CPUPPCState *env) spr_register_hv(env, SPR_MMCRC, "MMCRC", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic32, 0x00000000); spr_register_hv(env, SPR_MMCRH, "MMCRH", SPR_NOACCESS, SPR_NOACCESS, @@ -5441,7 +5441,7 @@ static void register_book3s_ids_sprs(CPUPPCState *env) spr_register_hv(env, SPR_HDSISR, "HDSISR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic32, 0x00000000); spr_register_hv(env, SPR_HRMOR, "HRMOR", SPR_NOACCESS, SPR_NOACCESS, @@ -5665,7 +5665,7 @@ static void register_power7_book4_sprs(CPUPPCState *env) KVM_REG_PPC_ACOP, 0); spr_register_kvm(env, SPR_BOOKS_PID, "PID", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic32, KVM_REG_PPC_PID, 0); #endif } @@ -5730,7 +5730,7 @@ static void register_power10_dexcr_sprs(CPUPPCState *env) { spr_register(env, SPR_DEXCR, "DEXCR", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic32, 0); spr_register(env, SPR_UDEXCR, "DEXCR", @@ -5741,7 +5741,7 @@ static void register_power10_dexcr_sprs(CPUPPCState *env) spr_register_hv(env, SPR_HDEXCR, "HDEXCR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic32, 0); spr_register(env, SPR_UHDEXCR, "HDEXCR", diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 779e7db513..fb351c303f 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -448,7 +448,7 @@ void register_non_embedded_sprs(CPUPPCState *env) /* Exception processing */ spr_register_kvm(env, SPR_DSISR, "DSISR", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic32, KVM_REG_PPC_DSISR, 0x00000000); spr_register_kvm(env, SPR_DAR, "DAR", SPR_NOACCESS, SPR_NOACCESS, diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index a9bc1522e2..40ddc5c08c 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -190,13 +190,13 @@ void helper_store_dpdes(CPUPPCState *env, target_ulong val) void helper_store_pidr(CPUPPCState *env, target_ulong val) { - env->spr[SPR_BOOKS_PID] = val; + env->spr[SPR_BOOKS_PID] = (uint32_t)val; tlb_flush(env_cpu(env)); } void helper_store_lpidr(CPUPPCState *env, target_ulong val) { - env->spr[SPR_LPIDR] = val; + env->spr[SPR_LPIDR] = (uint32_t)val; /* * We need to flush the TLB on LPID changes as we only tag HV vs diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 1381072b9e..64a64865d7 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -272,7 +272,7 @@ void helper_store_pmc(CPUPPCState *env, uint32_t sprn, uint64_t value) { pmu_update_cycles(env); - env->spr[sprn] = value; + env->spr[sprn] = (uint32_t)value; pmc_update_overflow_timer(env, sprn); } diff --git a/target/ppc/translate.c b/target/ppc/translate.c index df324fc7ff..58fa509057 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -413,7 +413,7 @@ void spr_write_generic(DisasContext *ctx, int sprn, int gprn) void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) { - spr_write_generic(ctx, sprn, gprn); + spr_write_generic32(ctx, sprn, gprn); /* * SPR_CTRL writes must force a new translation block, From patchwork Thu Mar 23 02:22:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1760101 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; 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[61.68.215.123]) by smtp.gmail.com with ESMTPSA id jc11-20020a17090325cb00b001a1abc93eabsm10609438plb.226.2023.03.22.19.22.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Mar 2023 19:22:49 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org Subject: [PATCH 2/6] target/ppc: Better CTRL SPR implementation Date: Thu, 23 Mar 2023 12:22:33 +1000 Message-Id: <20230323022237.1807512-2-npiggin@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230323022237.1807512-1-npiggin@gmail.com> References: <20230323022237.1807512-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=npiggin@gmail.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The CTRL register is able to write bit zero, and that is reflected in a bit field in the register that reflects the state of all threads in the core. TCG does not implement SMT, so this just requires mirroring that bit into the first bit of the thread state field. Signed-off-by: Nicholas Piggin --- target/ppc/translate.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 58fa509057..d699acb3d0 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -413,7 +413,14 @@ void spr_write_generic(DisasContext *ctx, int sprn, int gprn) void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) { - spr_write_generic32(ctx, sprn, gprn); + /* This does not implement >1 thread */ + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */ + tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ + tcg_gen_or_tl(t1, t1, t0); + gen_store_spr(sprn, t1); + spr_store_dump_spr(sprn); /* * SPR_CTRL writes must force a new translation block, From patchwork Thu Mar 23 02:22:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1760100 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=cDxSxVfb; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Phpzc3sjGz1yXq for ; Thu, 23 Mar 2023 13:23:23 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pfAbV-00025k-02; Wed, 22 Mar 2023 22:23:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pfAbQ-000244-Ee; Wed, 22 Mar 2023 22:22:59 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pfAbO-00083v-Ud; Wed, 22 Mar 2023 22:22:56 -0400 Received: by mail-pj1-x102f.google.com with SMTP id l9-20020a17090a3f0900b0023d32684e7fso2310318pjc.1; Wed, 22 Mar 2023 19:22:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679538173; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MAmH7/Wnz26mjPPEDwoTsOT+dBQ23DDMqUzeKxGlxjs=; b=cDxSxVfbSbdG5Lbq6bt2zQeUc48N2b2gABG2n6c3ofY1GjsoLjyRtv32MwkM+Q/oJE W1Lcc7pbDXJS5Wr7buNGhg/HdJ/CLMUrtgGIY32mZ3xaXm+Ug5IV4RUMVT47cH7gsaxk NVXLAGP/qDrZHypxT1KGrsKkydO1nxAOTl3azrDnAHtXWyu3qkNKDu2b+D4AxQvhTYzC DdJZNj9b1tKdBXR6Udqhnz921HIXBo+Gw87Ep+4luE8ptxa8PTSRQZSC878+90D7BGEe FDCqDK9rIqVak5jliukrz5nGCC01jsdBots+tmpXc1ezxd9BBfl5z2Y6/k8NEVwCCcly mqzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679538173; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MAmH7/Wnz26mjPPEDwoTsOT+dBQ23DDMqUzeKxGlxjs=; b=NvkQcPRQ76iYXY7Y7hu0Tv1L8ZsNymAx4Vwlt2mrJZI0w+WUc31qiMojJ9wrLQyA9v hOn55d6Ac0QpJxMKeKCzdfAet2YGi1e72SEC8yySGR7fjt3rrUYBAex9+mRjWkEXlgV0 EurHH3zxkGMnAcnWxwx207js6wHxfoTb/ELiLYuqnl/55Ws1GbDBnn+f/OPbNuXtKWJx rpN0IpR9L191zs0QEA0cFwhdsEyewT0anP4eH8aIsgPOvc6ODO8vxVVqnAwC+RyP9i06 ec5S3LH3u3DEth0iYz/hzlCsVpbDHqp6FbvRf5g7LmSVfupEnZIQ1Uou4g6T5KibSPYp Tw6w== X-Gm-Message-State: AO0yUKUgwG0MXr5YLIpDMklUEr4qkqS2Kqd/XFsVx0nnQgGikz0hitgl OlRjzxc0OiikIBK6TVDorL/1vwJC+AwtNQ== X-Google-Smtp-Source: AK7set/EVAbGAiTR/jFFxPX1Xw8gtYqBcd3RQ/HADAuRcxVyiYwnMu/qTZ6LKZ4QtjvH14t+OwPLLQ== X-Received: by 2002:a17:90b:1d8c:b0:237:b4c0:e15b with SMTP id pf12-20020a17090b1d8c00b00237b4c0e15bmr6026827pjb.44.1679538172924; Wed, 22 Mar 2023 19:22:52 -0700 (PDT) Received: from bobo.ozlabs.ibm.com (61-68-215-123.tpgi.com.au. [61.68.215.123]) by smtp.gmail.com with ESMTPSA id jc11-20020a17090325cb00b001a1abc93eabsm10609438plb.226.2023.03.22.19.22.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Mar 2023 19:22:52 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org Subject: [PATCH 3/6] target/ppc: Fix instruction loading endianness in alignment interrupt Date: Thu, 23 Mar 2023 12:22:34 +1000 Message-Id: <20230323022237.1807512-3-npiggin@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230323022237.1807512-1-npiggin@gmail.com> References: <20230323022237.1807512-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=npiggin@gmail.com; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org powerpc ifetch endianness depends on MSR[LE] so it has to byteswap after cpu_ldl_code(). This corrects DSISR bits in alignment interrupts when running in little endian mode. Signed-off-by: Nicholas Piggin --- target/ppc/excp_helper.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 287659c74d..5f0e363363 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -133,6 +133,31 @@ static void dump_hcall(CPUPPCState *env) env->nip); } +/* Return true iff byteswap is needed in a scalar memop */ +static inline bool need_byteswap(CPUArchState *env) +{ +#if TARGET_BIG_ENDIAN + return !!(env->msr & ((target_ulong)1 << MSR_LE)); +#else + return !(env->msr & ((target_ulong)1 << MSR_LE)); +#endif +} + +static uint32_t ppc_ldl_code(CPUArchState *env, abi_ptr addr) +{ + uint32_t insn = cpu_ldl_code(env, addr); +#if TARGET_BIG_ENDIAN + if (env->msr & ((target_ulong)1 << MSR_LE)) { + insn = bswap32(insn); + } +#else + if (!(env->msr & ((target_ulong)1 << MSR_LE))) { + insn = bswap32(insn); + } +#endif + return insn; +} + static void ppc_excp_debug_sw_tlb(CPUPPCState *env, int excp) { const char *es; @@ -3097,7 +3122,7 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, /* Restore state and reload the insn we executed, for filling in DSISR. */ cpu_restore_state(cs, retaddr); - insn = cpu_ldl_code(env, env->nip); + insn = ppc_ldl_code(env, env->nip); switch (env->mmu_model) { case POWERPC_MMU_SOFT_4xx: From patchwork Thu Mar 23 02:22:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1760109 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=a1OvQ/sn; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Phq0l6qX2z1yXq for ; Thu, 23 Mar 2023 13:24:23 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pfAbV-00026A-L0; Wed, 22 Mar 2023 22:23:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pfAbT-00024m-Nm; Wed, 22 Mar 2023 22:22:59 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pfAbS-00084E-5p; Wed, 22 Mar 2023 22:22:59 -0400 Received: by mail-pl1-x62b.google.com with SMTP id iw3so21013489plb.6; Wed, 22 Mar 2023 19:22:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679538176; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ED9m53P2RqmgU/d0l92tXekBAwOFR1U7QW39zIg74MM=; b=a1OvQ/snx6pQ/Bbl+GW14vKXy8Z2V5X6BKB2J5SEHFsiyOgeWzIIcp//beX4oQU1AM TYX0XSmizAw49ePyHO9onEVEjS1N4uBBYuLwQx+tiqocxejub+T40TMeCrthJxlDUoE3 qRMFnx8uI2A+Vac+PUXNMtQqogVSFuC/VFsGR1RPKZPz6yUM0acV/xJkaXClO/L7LZBW 11KPu4zqtUengVkK/h+rjpexh5WKUP1VJiyp8XOTyd9vihlsUccIajqDdQfJTbKhisTb rJncZV2+lHe+mmPu5FcUYB8ckQhdewsB2sg6YCOoCZhbdd5tA5o2UbAc2BZMDQC6Hf+r B41g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679538176; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ED9m53P2RqmgU/d0l92tXekBAwOFR1U7QW39zIg74MM=; b=YKOLx5WfQ0nwL5KLPIxYZLubKb0U086lIisp8Ci2vs/k9QSROO3qfCj0yFDnT1EKGZ 1IQaR4tacTJxSffHiWJjkmhWhN2d0jqentKecBJDgH18aGsUZcag2zgwmm4Uo37h5DJB ulADUqsM982GeJFrt5Zs/ObJN8PvXgySah77SMxfSg3HZMqy5tQM6/t8weA2cgss6DYo d2s6Kx12Tb3am1wtu6XnalO2vmHPwaJNgg3gQVfvO7oc+chCry7tRiWGxEpLZpWxiFhJ rQuwg160IodhCp2lkmuNNU5HtH/D7ZjsPQuF1CDFUZltOm6MeiYnjJ7vx2ZsgYgmzgey 8v3w== X-Gm-Message-State: AAQBX9eBbOa1lTZDMisWFQIXHqmrOOjl7E0+r4q5hohRD7LOjoxvn2tB QfPcGtGltEOPBeKUIwg0CM1jM3rg9b2LhQ== X-Google-Smtp-Source: AKy350ZIEL67Y2eLYMtskAZAPKkB+spzkKYH6y6pXKX3YG7eaao192m0liriYx5qY2y4c6jUERZxgw== X-Received: by 2002:a17:903:2291:b0:1a1:a727:a802 with SMTP id b17-20020a170903229100b001a1a727a802mr4034219plh.19.1679538175541; Wed, 22 Mar 2023 19:22:55 -0700 (PDT) Received: from bobo.ozlabs.ibm.com (61-68-215-123.tpgi.com.au. [61.68.215.123]) by smtp.gmail.com with ESMTPSA id jc11-20020a17090325cb00b001a1abc93eabsm10609438plb.226.2023.03.22.19.22.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Mar 2023 19:22:55 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org Subject: [PATCH 4/6] target/ppc: Alignment faults do not set DSISR in ISA v3.0 onward Date: Thu, 23 Mar 2023 12:22:35 +1000 Message-Id: <20230323022237.1807512-4-npiggin@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230323022237.1807512-1-npiggin@gmail.com> References: <20230323022237.1807512-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This optional behavior was removed from the ISA in v3.0, see Summary of Changes preface: Data Storage Interrupt Status Register for Alignment Interrupt: Simplifies the Alignment interrupt by remov- ing the Data Storage Interrupt Status Register (DSISR) from the set of registers modified by the Alignment interrupt. Signed-off-by: Nicholas Piggin --- target/ppc/excp_helper.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 5f0e363363..c8b8eca3b1 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1456,13 +1456,22 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp) break; } case POWERPC_EXCP_ALIGN: /* Alignment exception */ - /* Get rS/rD and rA from faulting opcode */ - /* - * Note: the opcode fields will not be set properly for a - * direct store load/store, but nobody cares as nobody - * actually uses direct store segments. - */ - env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; + switch (env->excp_model) { + case POWERPC_EXCP_970: + case POWERPC_EXCP_POWER7: + case POWERPC_EXCP_POWER8: + /* Get rS/rD and rA from faulting opcode */ + /* + * Note: the opcode fields will not be set properly for a + * direct store load/store, but nobody cares as nobody + * actually uses direct store segments. + */ + env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; + break; + default: + /* Optional DSISR update was removed from ISA v3.0 */ + break; + } break; case POWERPC_EXCP_PROGRAM: /* Program exception */ switch (env->error_code & ~0xF) { From patchwork Thu Mar 23 02:22:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1760111 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=AE94hz3R; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Phq114YCkz1yXq for ; Thu, 23 Mar 2023 13:24:37 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pfAbX-00027P-HK; Wed, 22 Mar 2023 22:23:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pfAbV-000268-Hw; Wed, 22 Mar 2023 22:23:01 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pfAbT-00084c-V1; Wed, 22 Mar 2023 22:23:01 -0400 Received: by mail-pj1-x102c.google.com with SMTP id p13-20020a17090a284d00b0023d2e945aebso2556961pjf.0; Wed, 22 Mar 2023 19:22:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679538178; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rQjn+SgGWwIP+Z7DlxmY0MZS5wesalzthIICvbdpCMQ=; b=AE94hz3Rz7CwRvzvpF9hxlia1ug8ejSngn9gUWjTYZWTNAABF3K2xvZ9aDPAhBEpgX EuKpuQE/d+VqvrSwx+bkwqPK6ybhBMClmwDn2RlESk+WnRe1NbL3xxC3bJur00GZMzqL S25UbtKxsvrh5WTim9VSU8BJgZfEz9rTEyrUjdhHBm+ayEtGPIIjw36RyHzegaDo6DsD QrLP2JwWN3ns5GzVcPv6dEXg5bUHVni2Kc+NU5Im8tlKXXhmWRAQsNd+wbePb2Y/hI/k cosoz7vRAYIR24lSi9c3FROQqIfTRVL4zehoaq6z3fqR9VXfVQwJEDvCgRYc3SgyzV5U JnGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679538178; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rQjn+SgGWwIP+Z7DlxmY0MZS5wesalzthIICvbdpCMQ=; b=KGDuiO7gXxtI5aIPZS17hLaOpYwV5hG6glfuijE8T9racqeI1y8rwRoTiSrZy8rIEq WxA34PQwFipB1VXb7m+Wh6A7qe9GJSpemsXXvrKpNN9fAdV1IGoKm+m96s2LpDlOZWLQ 5HTd47XpMoas65D4DlMsxfCSYXZoJBdkUu5wqDCPhc3kFqO3DEE6Qms3xyWFWl/W+hqK v09jV0mKz1Lotxei+jHP797NRYxpybdo7fLOLnf2UIhHvNl+mBXLPoGIvI17IGfwZyyx fEE6RT/78zQCt6uAfXGoXGifAym8QsQBnPO1NIqec4pl3/IutL91ueLKYDy4y3f0/Ho5 i4YQ== X-Gm-Message-State: AAQBX9cfYgBRk/9BQpRZLWBeCNq6i70S2miZcYgIts+NYBkDWWtSK+WG xWY+tioO2VNOC3bNnGU+BexAWZqvD4YU4g== X-Google-Smtp-Source: AKy350YDwtswbzTGzqYWYFBT8QWjJWVgtDVevApOeR6gJdXSLkuDg3kJdg9e5rLfutbfegjSKVUbig== X-Received: by 2002:a17:902:da84:b0:19a:727e:d4f3 with SMTP id j4-20020a170902da8400b0019a727ed4f3mr4122870plx.5.1679538178112; Wed, 22 Mar 2023 19:22:58 -0700 (PDT) Received: from bobo.ozlabs.ibm.com (61-68-215-123.tpgi.com.au. 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Among the changes, various synchronous interrupts report whether they were caused by a prefix instruction in (H)SRR1. Signed-off-by: Nicholas Piggin --- target/ppc/excp_helper.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index c8b8eca3b1..2e0321ab69 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1353,12 +1353,26 @@ static bool books_vhyp_handles_hv_excp(PowerPCCPU *cpu) return false; } +static bool is_prefix_excp(CPUPPCState *env, uint32_t insn) +{ + switch (env->excp_model) { + case POWERPC_EXCP_970: + case POWERPC_EXCP_POWER7: + case POWERPC_EXCP_POWER8: + case POWERPC_EXCP_POWER9: + return false; + default: /* POWER10 / ISAv3.1 onward */ + return ((insn & 0xfc000000) == 0x04000000); + } +} + static void powerpc_excp_books(PowerPCCPU *cpu, int excp) { CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; target_ulong msr, new_msr, vector; int srr0, srr1, lev = -1; + uint32_t insn = 0; /* new srr1 value excluding must-be-zero bits */ msr = env->msr & ~0x783f0000ULL; @@ -1397,6 +1411,29 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp) vector |= env->excp_prefix; + switch (excp) { + case POWERPC_EXCP_MCHECK: + case POWERPC_EXCP_DSI: + case POWERPC_EXCP_DSEG: + case POWERPC_EXCP_ALIGN: + case POWERPC_EXCP_PROGRAM: + case POWERPC_EXCP_FPU: + case POWERPC_EXCP_TRACE: + case POWERPC_EXCP_HDSI: + case POWERPC_EXCP_HV_EMU: + case POWERPC_EXCP_VPU: + case POWERPC_EXCP_VSXU: + case POWERPC_EXCP_FU: + case POWERPC_EXCP_HV_FU: + insn = ppc_ldl_code(env, env->nip); + if (is_prefix_excp(env, insn)) { + msr |= PPC_BIT(34); + } + break; + default: + break; + } + switch (excp) { case POWERPC_EXCP_MCHECK: /* Machine check exception */ if (!FIELD_EX64(env->msr, MSR, ME)) { From patchwork Thu Mar 23 02:22:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1760105 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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[61.68.215.123]) by smtp.gmail.com with ESMTPSA id jc11-20020a17090325cb00b001a1abc93eabsm10609438plb.226.2023.03.22.19.22.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Mar 2023 19:23:00 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org Subject: [PATCH 6/6] target/ppc: Implement HEIR SPR Date: Thu, 23 Mar 2023 12:22:37 +1000 Message-Id: <20230323022237.1807512-6-npiggin@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230323022237.1807512-1-npiggin@gmail.com> References: <20230323022237.1807512-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=npiggin@gmail.com; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The hypervisor emulation assistance interrupt modifies HEIR to contain the value of the instruction which caused the exception. Signed-off-by: Nicholas Piggin --- target/ppc/cpu.h | 1 + target/ppc/cpu_init.c | 23 +++++++++++++++++++++++ target/ppc/excp_helper.c | 12 +++++++++++- 3 files changed, 35 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 557d736dab..8c4a203ecb 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1653,6 +1653,7 @@ void ppc_compat_add_property(Object *obj, const char *name, #define SPR_HMER (0x150) #define SPR_HMEER (0x151) #define SPR_PCR (0x152) +#define SPR_HEIR (0x153) #define SPR_BOOKE_LPIDR (0x152) #define SPR_BOOKE_TCR (0x154) #define SPR_BOOKE_TLB0PS (0x158) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 5aa0b3f0f1..ff73be1812 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -1629,6 +1629,7 @@ static void register_8xx_sprs(CPUPPCState *env) * HSRR0 => SPR 314 (Power 2.04 hypv) * HSRR1 => SPR 315 (Power 2.04 hypv) * LPIDR => SPR 317 (970) + * HEIR => SPR 339 (Power 2.05 hypv) (64-bit reg from 3.1) * EPR => SPR 702 (Power 2.04 emb) * perf => 768-783 (Power 2.04) * perf => 784-799 (Power 2.04) @@ -5522,6 +5523,24 @@ static void register_power6_common_sprs(CPUPPCState *env) 0x00000000); } +static void register_HEIR32_spr(CPUPPCState *env) +{ + spr_register_hv(env, SPR_HEIR, "HEIR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic32, + 0x00000000); +} + +static void register_HEIR64_spr(CPUPPCState *env) +{ + spr_register_hv(env, SPR_HEIR, "HEIR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + static void register_power8_tce_address_control_sprs(CPUPPCState *env) { spr_register_kvm(env, SPR_TAR, "TAR", @@ -5950,6 +5969,7 @@ static void init_proc_POWER7(CPUPPCState *env) register_power5p_ear_sprs(env); register_power5p_tb_sprs(env); register_power6_common_sprs(env); + register_HEIR32_spr(env); register_power6_dbg_sprs(env); register_power7_book4_sprs(env); @@ -6072,6 +6092,7 @@ static void init_proc_POWER8(CPUPPCState *env) register_power5p_ear_sprs(env); register_power5p_tb_sprs(env); register_power6_common_sprs(env); + register_HEIR32_spr(env); register_power6_dbg_sprs(env); register_power8_tce_address_control_sprs(env); register_power8_ids_sprs(env); @@ -6234,6 +6255,7 @@ static void init_proc_POWER9(CPUPPCState *env) register_power5p_ear_sprs(env); register_power5p_tb_sprs(env); register_power6_common_sprs(env); + register_HEIR32_spr(env); register_power6_dbg_sprs(env); register_power8_tce_address_control_sprs(env); register_power8_ids_sprs(env); @@ -6409,6 +6431,7 @@ static void init_proc_POWER10(CPUPPCState *env) register_power5p_ear_sprs(env); register_power5p_tb_sprs(env); register_power6_common_sprs(env); + register_HEIR64_spr(env); register_power6_dbg_sprs(env); register_power8_tce_address_control_sprs(env); register_power8_ids_sprs(env); diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 2e0321ab69..d206903562 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1614,13 +1614,23 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp) case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */ - case POWERPC_EXCP_HV_EMU: case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */ srr0 = SPR_HSRR0; srr1 = SPR_HSRR1; new_msr |= (target_ulong)MSR_HVB; new_msr |= env->msr & ((target_ulong)1 << MSR_RI); break; + case POWERPC_EXCP_HV_EMU: + env->spr[SPR_HEIR] = insn; + if (is_prefix_excp(env, insn)) { + uint32_t insn2 = ppc_ldl_code(env, env->nip + 4); + env->spr[SPR_HEIR] |= (uint64_t)insn2 << 32; + } + srr0 = SPR_HSRR0; + srr1 = SPR_HSRR1; + new_msr |= (target_ulong)MSR_HVB; + new_msr |= env->msr & ((target_ulong)1 << MSR_RI); + break; case POWERPC_EXCP_VPU: /* Vector unavailable exception */ case POWERPC_EXCP_VSXU: /* VSX unavailable exception */ case POWERPC_EXCP_FU: /* Facility unavailable exception */