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Wed, 22 Feb 2023 09:01:23 +0000 (GMT) Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5C24F20040; Wed, 22 Feb 2023 09:01:20 +0000 (GMT) Received: from li-a450e7cc-27df-11b2-a85c-b5a9ac31e8ef.ibm.com (unknown [9.43.123.148]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 22 Feb 2023 09:01:19 +0000 (GMT) From: Kautuk Consul To: Michael Ellerman , Nicholas Piggin , Christophe Leroy , Rohan McLure Subject: [PATCH] arch/powerpc/include/asm/barrier.h: redefine rmb and wmb to lwsync Date: Wed, 22 Feb 2023 14:31:12 +0530 Message-Id: <20230222090112.187583-1-kconsul@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: QSyD09S1KL2OukIdwsFLPU76kYkEd2ei X-Proofpoint-ORIG-GUID: zGfMT4bp9Ocw1RK_BS4iUcheaR5QJK7k X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-22_04,2023-02-20_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 adultscore=0 phishscore=0 suspectscore=0 mlxlogscore=774 impostorscore=0 mlxscore=0 bulkscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302220078 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Kautuk Consul Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" A link from ibm.com states: "Ensures that all instructions preceding the call to __lwsync complete before any subsequent store instructions can be executed on the processor that executed the function. Also, it ensures that all load instructions preceding the call to __lwsync complete before any subsequent load instructions can be executed on the processor that executed the function. This allows you to synchronize between multiple processors with minimal performance impact, as __lwsync does not wait for confirmation from each processor." Thats why smp_rmb() and smp_wmb() are defined to lwsync. But this same understanding applies to parallel pipeline execution on each PowerPC processor. So, use the lwsync instruction for rmb() and wmb() on the PPC architectures that support it. Also removed some useless spaces. Signed-off-by: Kautuk Consul --- arch/powerpc/include/asm/barrier.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/include/asm/barrier.h b/arch/powerpc/include/asm/barrier.h index e80b2c0e9315..553f5a5d20bd 100644 --- a/arch/powerpc/include/asm/barrier.h +++ b/arch/powerpc/include/asm/barrier.h @@ -41,11 +41,17 @@ /* The sub-arch has lwsync */ #if defined(CONFIG_PPC64) || defined(CONFIG_PPC_E500MC) -# define SMPWMB LWSYNC +#undef rmb +#undef wmb +/* Redefine rmb() to lwsync. */ +#define rmb() ({__asm__ __volatile__ ("lwsync" : : : "memory"); }) +/* Redefine wmb() to lwsync. */ +#define wmb() ({__asm__ __volatile__ ("lwsync" : : : "memory"); }) +#define SMPWMB LWSYNC #elif defined(CONFIG_BOOKE) -# define SMPWMB mbar +#define SMPWMB mbar #else -# define SMPWMB eieio +#define SMPWMB eieio #endif /* clang defines this macro for a builtin, which will not work with runtime patching */